wu-arch/vortex
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

rtl gpr multicore fix

Browse Source
This commit is contained in:
Blaise Tine
2020-05-06 09:05:10 -04:00
parent b1fdf0a947
commit 330bbc4f56
18 changed files with 210 additions and 200 deletions
Download Patch File Download Diff File Expand all files Collapse all files

39
hw/rtl/cache/VX_bank.v vendored
View File

@@ -69,7 +69,7 @@ module VX_bank #(
// Core Response
output wire core_rsp_valid,
output wire [`LOG2UP(NUM_REQUESTS)-1:0] core_rsp_tid,
output wire [`REQS_BITS-1:0] core_rsp_tid,
output wire [`WORD_WIDTH-1:0] core_rsp_data,
output wire [CORE_TAG_WIDTH-1:0] core_rsp_tag,
input wire core_rsp_pop,
@@ -156,18 +156,18 @@ module VX_bank #(
.full (dfpq_full)
);
wire reqq_pop;
wire reqq_push;
wire reqq_empty;
wire reqq_req_st0;
wire[`LOG2UP(NUM_REQUESTS)-1:0] reqq_req_tid_st0;
wire reqq_pop;
wire reqq_push;
wire reqq_empty;
wire reqq_req_st0;
wire[`REQS_BITS-1:0] reqq_req_tid_st0;
`IGNORE_WARNINGS_BEGIN
wire [31:0] reqq_req_addr_st0;
wire [31:0] reqq_req_addr_st0;
`IGNORE_WARNINGS_END
wire [`WORD_WIDTH-1:0] reqq_req_writeword_st0;
wire [CORE_TAG_WIDTH-1:0] reqq_req_tag_st0;
wire [`BYTE_EN_BITS-1:0] reqq_req_mem_read_st0;
wire [`BYTE_EN_BITS-1:0] reqq_req_mem_write_st0;
wire [`WORD_WIDTH-1:0] reqq_req_writeword_st0;
wire [CORE_TAG_WIDTH-1:0] reqq_req_tag_st0;
wire [`BYTE_EN_BITS-1:0] reqq_req_mem_read_st0;
wire [`BYTE_EN_BITS-1:0] reqq_req_mem_write_st0;
assign reqq_push = core_req_ready && (| core_req_valids);
@@ -218,7 +218,7 @@ module VX_bank #(
wire mrvq_full;
wire mrvq_stop;
wire mrvq_valid_st0;
wire[`LOG2UP(NUM_REQUESTS)-1:0] mrvq_tid_st0;
wire[`REQS_BITS-1:0] mrvq_tid_st0;
wire [`LINE_ADDR_WIDTH-1:0] mrvq_addr_st0;
wire [`BASE_ADDR_BITS-1:0] mrvq_wsel_st0;
wire [`WORD_WIDTH-1:0] mrvq_writeword_st0;
@@ -230,7 +230,7 @@ module VX_bank #(
wire[`LINE_ADDR_WIDTH-1:0] miss_add_addr;
wire[`BASE_ADDR_BITS-1:0] miss_add_wsel;
wire[`WORD_WIDTH-1:0] miss_add_data;
wire[`LOG2UP(NUM_REQUESTS)-1:0] miss_add_tid;
wire[`REQS_BITS-1:0] miss_add_tid;
wire[CORE_TAG_WIDTH-1:0] miss_add_tag;
wire[`BYTE_EN_BITS-1:0] miss_add_mem_read;
wire[`BYTE_EN_BITS-1:0] miss_add_mem_write;
@@ -348,7 +348,7 @@ module VX_bank #(
wire dirty_st1e;
`DEBUG_BEGIN
wire [CORE_TAG_WIDTH-1:0] tag_st1e;
wire [`LOG2UP(NUM_REQUESTS)-1:0] tid_st1e;
wire [`REQS_BITS-1:0] tid_st1e;
`DEBUG_END
wire [`BYTE_EN_BITS-1:0] mem_read_st1e;
wire [`BYTE_EN_BITS-1:0] mem_write_st1e;
@@ -515,14 +515,15 @@ module VX_bank #(
|| (valid_st2 && miss_st2 && mrvq_full)
|| (valid_st2 && miss_st2 && !invalidate_fill && dram_fill_req_full));
wire [`WORD_WIDTH-1:0] cwbq_data = readword_st2;
wire [`LOG2UP(NUM_REQUESTS)-1:0] cwbq_tid = miss_add_tid;
wire [CORE_TAG_WIDTH-1:0] cwbq_tag = miss_add_tag;
wire [`WORD_WIDTH-1:0] cwbq_data = readword_st2;
wire [`REQS_BITS-1:0] cwbq_tid = miss_add_tid;
wire [CORE_TAG_WIDTH-1:0] cwbq_tag = miss_add_tag;
wire cwbq_empty;
wire cwbq_empty;
assign core_rsp_valid = !cwbq_empty;
VX_generic_queue #(
.DATAW(`LOG2UP(NUM_REQUESTS) + CORE_TAG_WIDTH + `WORD_WIDTH),
.DATAW(`REQS_BITS + CORE_TAG_WIDTH + `WORD_WIDTH),
.SIZE(CWBQ_SIZE)
) cwb_queue (
.clk (clk),

4
hw/rtl/cache/VX_cache.v vendored
View File

@@ -109,7 +109,7 @@ module VX_cache #(
wire [NUM_BANKS-1:0] per_bank_core_rsp_pop;
wire [NUM_BANKS-1:0] per_bank_core_rsp_valid;
wire [NUM_BANKS-1:0][`LOG2UP(NUM_REQUESTS)-1:0] per_bank_core_rsp_tid;
wire [NUM_BANKS-1:0][`REQS_BITS-1:0] per_bank_core_rsp_tid;
wire [NUM_BANKS-1:0][`WORD_WIDTH-1:0] per_bank_core_rsp_data;
wire [NUM_BANKS-1:0][CORE_TAG_WIDTH-1:0] per_bank_core_rsp_tag;
@@ -173,7 +173,7 @@ module VX_cache #(
wire curr_bank_core_rsp_pop;
wire curr_bank_core_rsp_valid;
wire [`LOG2UP(NUM_REQUESTS)-1:0] curr_bank_core_rsp_tid;
wire [`REQS_BITS-1:0] curr_bank_core_rsp_tid;
wire [`WORD_WIDTH-1:0] curr_bank_core_rsp_data;
wire [CORE_TAG_WIDTH-1:0] curr_bank_core_rsp_tag;

8
hw/rtl/cache/VX_cache_config.vh vendored
View File

@@ -12,10 +12,14 @@
`define BYTE_EN_BITS 3
// data tid tag read write base addr
`define MRVQ_METADATA_WIDTH (`WORD_WIDTH + `LOG2UP(NUM_REQUESTS) + CORE_TAG_WIDTH + `BYTE_EN_BITS + `BYTE_EN_BITS + `BASE_ADDR_BITS)
`define MRVQ_METADATA_WIDTH (`WORD_WIDTH + `REQS_BITS + CORE_TAG_WIDTH + `BYTE_EN_BITS + `BYTE_EN_BITS + `BASE_ADDR_BITS)
// tag read write reqs
`define REQ_INST_META_WIDTH (CORE_TAG_WIDTH + `BYTE_EN_BITS + `BYTE_EN_BITS + `LOG2UP(NUM_REQUESTS))
`define REQ_INST_META_WIDTH (CORE_TAG_WIDTH + `BYTE_EN_BITS + `BYTE_EN_BITS + `REQS_BITS)
`define REQS_BITS `LOG2UP(NUM_REQUESTS)
`define BANK_BITS `LOG2UP(NUM_BANKS)
`define WORD_WIDTH (8 * WORD_SIZE)
`define BYTE_WIDTH (`WORD_WIDTH / 4)

10
hw/rtl/cache/VX_cache_core_rsp_merge.v vendored
View File

@@ -46,7 +46,7 @@ module VX_cache_core_rsp_merge #(
parameter DRAM_TAG_WIDTH = 1
) (
// Per Bank WB
input wire [NUM_BANKS-1:0][`LOG2UP(NUM_REQUESTS)-1:0] per_bank_core_rsp_tid,
input wire [NUM_BANKS-1:0][`REQS_BITS-1:0] per_bank_core_rsp_tid,
input wire [NUM_BANKS-1:0] per_bank_core_rsp_valid,
input wire [NUM_BANKS-1:0][`WORD_WIDTH-1:0] per_bank_core_rsp_data,
input wire [NUM_BANKS-1:0][CORE_TAG_WIDTH-1:0] per_bank_core_rsp_tag,
@@ -63,8 +63,8 @@ module VX_cache_core_rsp_merge #(
assign per_bank_core_rsp_pop = per_bank_core_rsp_pop_unqual & {NUM_BANKS{core_rsp_ready}};
wire [`LOG2UP(NUM_BANKS)-1:0] main_bank_index;
wire found_bank;
wire [`BANK_BITS-1:0] main_bank_index;
wire found_bank;
VX_generic_priority_encoder #(
.N(NUM_BANKS)
@@ -86,7 +86,7 @@ module VX_cache_core_rsp_merge #(
if (found_bank
&& per_bank_core_rsp_valid[i]
&& !core_rsp_valid[per_bank_core_rsp_tid[i]]
&& ((main_bank_index == `LOG2UP(NUM_BANKS)'(i))
&& ((main_bank_index == `BANK_BITS'(i))
|| (per_bank_core_rsp_tid[i] != per_bank_core_rsp_tid[main_bank_index]))
&& (per_bank_core_rsp_tag[i][CORE_TAG_ID_BITS-1:0] == per_bank_core_rsp_tag[main_bank_index][CORE_TAG_ID_BITS-1:0])) begin
core_rsp_valid[per_bank_core_rsp_tid[i]] = 1;
@@ -106,7 +106,7 @@ module VX_cache_core_rsp_merge #(
if (found_bank
&& per_bank_core_rsp_valid[i]
&& !core_rsp_valid[per_bank_core_rsp_tid[i]]
&& ((main_bank_index == `LOG2UP(NUM_BANKS)'(i))
&& ((main_bank_index == `BANK_BITS'(i))
|| (per_bank_core_rsp_tid[i] != per_bank_core_rsp_tid[main_bank_index]))) begin
core_rsp_valid[per_bank_core_rsp_tid[i]] = 1;
core_rsp_data[per_bank_core_rsp_tid[i]] = per_bank_core_rsp_data[i];

4
hw/rtl/cache/VX_cache_dfq_queue.v vendored
View File

@@ -86,8 +86,8 @@ module VX_cache_dfq_queue #(
assign use_per_bqual_bank_dram_fill_req_valid = use_empty ? (out_per_bank_dram_fill_req_valid & {NUM_BANKS{!o_empty}}) : (use_per_bank_dram_fill_req_valid & {NUM_BANKS{!use_empty}});
assign qual_bank_dram_fill_req_addr = use_empty ? out_per_bank_dram_fill_req_addr : use_per_bank_dram_fill_req_addr;
wire[`LOG2UP(NUM_BANKS)-1:0] qual_request_index;
wire qual_has_request;
wire[`BANK_BITS-1:0] qual_request_index;
wire qual_has_request;
VX_generic_priority_encoder #(
.N(NUM_BANKS)

2
hw/rtl/cache/VX_cache_dram_req_arb.v vendored
View File

@@ -113,7 +113,7 @@ module VX_cache_dram_req_arb #(
.dfqq_full (dfqq_full)
);
wire [`LOG2UP(NUM_BANKS)-1:0] dwb_bank;
wire [`BANK_BITS-1:0] dwb_bank;
wire [NUM_BANKS-1:0] use_wb_valid = per_bank_dram_wb_req_valid;

4
hw/rtl/cache/VX_cache_miss_resrv.v vendored
View File

@@ -48,7 +48,7 @@ module VX_cache_miss_resrv #(
input wire[`LINE_ADDR_WIDTH-1:0] miss_add_addr,
input wire[`BASE_ADDR_BITS-1:0] miss_add_wsel,
input wire[`WORD_WIDTH-1:0] miss_add_data,
input wire[`LOG2UP(NUM_REQUESTS)-1:0] miss_add_tid,
input wire[`REQS_BITS-1:0] miss_add_tid,
input wire[CORE_TAG_WIDTH-1:0] miss_add_tag,
input wire[`BYTE_EN_BITS-1:0] miss_add_mem_read,
input wire[`BYTE_EN_BITS-1:0] miss_add_mem_write,
@@ -69,7 +69,7 @@ module VX_cache_miss_resrv #(
output wire[`LINE_ADDR_WIDTH-1:0] miss_resrv_addr_st0,
output wire[`BASE_ADDR_BITS-1:0] miss_resrv_wsel_st0,
output wire[`WORD_WIDTH-1:0] miss_resrv_data_st0,
output wire[`LOG2UP(NUM_REQUESTS)-1:0] miss_resrv_tid_st0,
output wire[`REQS_BITS-1:0] miss_resrv_tid_st0,
output wire[CORE_TAG_WIDTH-1:0] miss_resrv_tag_st0,
output wire[`BYTE_EN_BITS-1:0] miss_resrv_mem_read_st0,
output wire[`BYTE_EN_BITS-1:0] miss_resrv_mem_write_st0

6
hw/rtl/cache/VX_cache_req_queue.v vendored
View File

@@ -58,7 +58,7 @@ module VX_cache_req_queue #(
// Dequeue Data
input wire reqq_pop,
output wire reqq_req_st0,
output wire [`LOG2UP(NUM_REQUESTS)-1:0] reqq_req_tid_st0,
output wire [`REQS_BITS-1:0] reqq_req_tid_st0,
output wire [`BYTE_EN_BITS-1:0] reqq_req_mem_read_st0,
output wire [`BYTE_EN_BITS-1:0] reqq_req_mem_write_st0,
output wire [`WORD_WIDTH-1:0] reqq_req_writedata_st0,
@@ -126,8 +126,8 @@ module VX_cache_req_queue #(
assign qual_mem_read = use_per_mem_read;
assign qual_mem_write = use_per_mem_write;
wire[`LOG2UP(NUM_REQUESTS)-1:0] qual_request_index;
wire qual_has_request;
wire[`REQS_BITS-1:0] qual_request_index;
wire qual_has_request;
VX_generic_priority_encoder #(
.N(NUM_REQUESTS)

4
hw/rtl/cache/VX_snp_fwd_arb.v vendored
View File

@@ -15,8 +15,8 @@ module VX_snp_fwd_arb #(
wire [NUM_BANKS-1:0] qual_per_bank_snp_fwd = per_bank_snp_fwd_valid & {NUM_BANKS{snp_fwd_ready}};
wire [`LOG2UP(NUM_BANKS)-1:0] fsq_bank;
wire fsq_valid;
wire [`BANK_BITS-1:0] fsq_bank;
wire fsq_valid;
VX_generic_priority_encoder #(
.N(NUM_BANKS)