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refactoring RTL simulator and Makefile

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This commit is contained in:
Blaise Tine
2020-03-26 04:14:36 -04:00
parent acafcceb94
commit 3252d52694
6 changed files with 87 additions and 109 deletions
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44
rtl/simulate/test_bench.h → rtl/simulate/Vortex.h
View File

@@ -16,8 +16,6 @@
#include "VVortex__Syms.h"
#include "verilated.h"
#include "tb_debug.h"
#ifdef VCD_OUTPUT
#include <verilated_vcd_c.h>
#endif
@@ -40,17 +38,16 @@ typedef struct
class Vortex
{
public:
Vortex();
Vortex(RAM* ram);
~Vortex();
bool simulate(std::string);
private:
void ProcessFile(void);
bool simulate();
private:
void print_stats(bool = true);
bool ibus_driver();
bool dbus_driver();
void io_handler();
RAM ram;
RAM* ram;
VVortex * vortex;
@@ -62,7 +59,6 @@ class Vortex
long int curr_cycle;
bool stop;
bool unit_test;
std::string instruction_file_name;
std::ofstream results;
int stats_static_inst;
int stats_dynamic_inst;
@@ -87,11 +83,12 @@ class Vortex
Vortex::Vortex() : start_pc(0), curr_cycle(0), stop(true), unit_test(true), stats_static_inst(0), stats_dynamic_inst(-1),
Vortex::Vortex(RAM* ram) : start_pc(0), curr_cycle(0), stop(true), unit_test(true), stats_static_inst(0), stats_dynamic_inst(-1),
stats_total_cycles(0), stats_fwd_stalls(0), stats_branch_stalls(0),
debug_state(0), ibus_state(0), dbus_state(0), debug_return(0),
debug_wait_num(0), debug_inst_num(0), debug_end_wait(0), debug_debugAddr(0)
{
this->ram = ram;
this->vortex = new VVortex;
#ifdef VCD_OUTPUT
this->m_trace = new VerilatedVcdC;
@@ -110,12 +107,6 @@ Vortex::~Vortex()
delete this->vortex;
}
void Vortex::ProcessFile(void)
{
loadHexImpl(this->instruction_file_name.c_str(), &this->ram);
}
void Vortex::print_stats(bool cycle_test)
{
@@ -139,7 +130,7 @@ void Vortex::print_stats(bool cycle_test)
uint32_t status;
ram.getWord(0, &status);
ram->getWord(0, &status);
if (this->unit_test)
{
@@ -202,7 +193,7 @@ bool Vortex::ibus_driver()
{
unsigned curr_addr = dram_req.base_addr + (i*4);
unsigned data_rd;
ram.getWord(curr_addr, &data_rd);
ram->getWord(curr_addr, &data_rd);
dram_req.data[i] = data_rd;
}
// std::cout << "Fill Req -> Addr: " << std::hex << dram_req.base_addr << std::dec << "\n";
@@ -218,7 +209,7 @@ bool Vortex::ibus_driver()
{
unsigned curr_addr = base_addr + (i*4);
unsigned data_wr = vortex->I_dram_req_data[i];
ram.writeWord(curr_addr, &data_wr);
ram->writeWord(curr_addr, &data_wr);
}
}
}
@@ -301,7 +292,7 @@ bool Vortex::dbus_driver()
{
unsigned curr_addr = dram_req.base_addr + (i*4);
unsigned data_rd;
ram.getWord(curr_addr, &data_rd);
ram->getWord(curr_addr, &data_rd);
dram_req.data[i] = data_rd;
}
// std::cout << "Fill Req -> Addr: " << std::hex << dram_req.base_addr << std::dec << "\n";
@@ -317,7 +308,7 @@ bool Vortex::dbus_driver()
{
unsigned curr_addr = base_addr + (i*4);
unsigned data_wr = vortex->dram_req_data[i];
ram.writeWord(curr_addr, &data_wr);
ram->writeWord(curr_addr, &data_wr);
}
}
}
@@ -347,17 +338,10 @@ bool Vortex::dbus_driver()
bool Vortex::simulate(std::string file_to_simulate)
bool Vortex::simulate()
{
this->instruction_file_name = file_to_simulate;
// this->results << "\n****************\t" << file_to_simulate << "\t****************\n";
this->ProcessFile();
// auto start_time = std::chrono::high_resolution_clock::now();
static bool stop = false;
static int counter = 0;
counter = 0;
@@ -470,7 +454,7 @@ bool Vortex::simulate(std::string file_to_simulate)
// std::cout << "Something: " << result << '\n';
// uint32_t status;
// ram.getWord(0, &status);
// ram->getWord(0, &status);
this->print_stats();
@@ -478,4 +462,4 @@ bool Vortex::simulate(std::string file_to_simulate)
return (status == 1);
// return (1 == 1);
}
}

52
rtl/simulate/multi_test_bench.h → rtl/simulate/Vortex_SOC.h
View File

@@ -15,8 +15,6 @@
#include "VVortex_SOC.h"
#include "verilated.h"
#include "tb_debug.h"
#ifdef VCD_OUTPUT
#include <verilated_vcd_c.h>
#endif
@@ -36,20 +34,19 @@ typedef struct
unsigned * data;
} dram_req_t;
class Vortex
class Vortex_SOC
{
public:
Vortex();
~Vortex();
bool simulate(std::string);
Vortex_SOC(RAM* ram);
~Vortex_SOC();
bool simulate();
private:
void ProcessFile(void);
void print_stats(bool = true);
bool ibus_driver();
bool dbus_driver();
void io_handler();
RAM ram;
RAM* ram;
VVortex_SOC * vortex;
@@ -61,7 +58,6 @@ class Vortex
long int curr_cycle;
bool stop;
bool unit_test;
std::string instruction_file_name;
std::ofstream results;
int stats_static_inst;
int stats_dynamic_inst;
@@ -85,11 +81,12 @@ class Vortex
Vortex::Vortex() : start_pc(0), curr_cycle(0), stop(true), unit_test(true), stats_static_inst(0), stats_dynamic_inst(-1),
Vortex_SOC::Vortex_SOC(RAM* ram) : start_pc(0), curr_cycle(0), stop(true), unit_test(true), stats_static_inst(0), stats_dynamic_inst(-1),
stats_total_cycles(0), stats_fwd_stalls(0), stats_branch_stalls(0),
debug_state(0), ibus_state(0), dbus_state(0), debug_return(0),
debug_wait_num(0), debug_inst_num(0), debug_end_wait(0), debug_debugAddr(0)
{
this->ram = ram;
this->vortex = new VVortex_SOC;
#ifdef VCD_OUTPUT
this->m_trace = new VerilatedVcdC;
@@ -99,7 +96,7 @@ Vortex::Vortex() : start_pc(0), curr_cycle(0), stop(true), unit_test(true), stat
this->results.open("../results.txt");
}
Vortex::~Vortex()
Vortex_SOC::~Vortex_SOC()
{
#ifdef VCD_OUTPUT
m_trace->close();
@@ -108,13 +105,7 @@ Vortex::~Vortex()
delete this->vortex;
}
void Vortex::ProcessFile(void)
{
loadHexImpl(this->instruction_file_name.c_str(), &this->ram);
}
void Vortex::print_stats(bool cycle_test)
void Vortex_SOC::print_stats(bool cycle_test)
{
if (cycle_test)
@@ -137,7 +128,7 @@ void Vortex::print_stats(bool cycle_test)
uint32_t status;
ram.getWord(0, &status);
ram->getWord(0, &status);
if (this->unit_test)
{
@@ -162,14 +153,14 @@ void Vortex::print_stats(bool cycle_test)
}
bool Vortex::ibus_driver()
bool Vortex_SOC::ibus_driver()
{
return false;
}
void Vortex::io_handler()
void Vortex_SOC::io_handler()
{
// std::cout << "Checking\n";
for (int c = 0; c < vortex->number_cores; c++)
@@ -188,7 +179,7 @@ void Vortex::io_handler()
}
bool Vortex::dbus_driver()
bool Vortex_SOC::dbus_driver()
{
// Iterate through each element, and get pop index
@@ -224,7 +215,7 @@ bool Vortex::dbus_driver()
{
unsigned curr_addr = dram_req.base_addr + (i*4);
unsigned data_rd;
ram.getWord(curr_addr, &data_rd);
ram->getWord(curr_addr, &data_rd);
dram_req.data[i] = data_rd;
}
// std::cout << "Fill Req -> Addr: " << std::hex << dram_req.base_addr << std::dec << "\n";
@@ -240,7 +231,7 @@ bool Vortex::dbus_driver()
{
unsigned curr_addr = base_addr + (i*4);
unsigned data_wr = vortex->out_dram_req_data[i];
ram.writeWord(curr_addr, &data_wr);
ram->writeWord(curr_addr, &data_wr);
}
}
}
@@ -270,17 +261,10 @@ bool Vortex::dbus_driver()
bool Vortex::simulate(std::string file_to_simulate)
bool Vortex_SOC::simulate()
{
this->instruction_file_name = file_to_simulate;
// this->results << "\n****************\t" << file_to_simulate << "\t****************\n";
this->ProcessFile();
// auto start_time = std::chrono::high_resolution_clock::now();
static bool stop = false;
static int counter = 0;
counter = 0;
@@ -394,7 +378,7 @@ bool Vortex::simulate(std::string file_to_simulate)
// std::cout << "Something: " << result << '\n';
// uint32_t status;
// ram.getWord(0, &status);
// ram->getWord(0, &status);
this->print_stats();
@@ -402,4 +386,4 @@ bool Vortex::simulate(std::string file_to_simulate)
return (status == 1);
// return (1 == 1);
}
}

25
rtl/simulate/multi_test_bench.cpp
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@@ -1,4 +1,4 @@
#include "multi_test_bench.h"
#include "Vortex_SOC.h"
#define NUM_TESTS 46
@@ -65,13 +65,16 @@ int main(int argc, char **argv)
};
for (std::string s : tests) {
Vortex v;
std::cerr << DEFAULT << "\n---------------------------------------\n";
std::cerr << DEFAULT << "\n---------------------------------------\n";
std::cerr << s << std::endl;
bool curr = v.simulate(s);
RAM ram;
loadHexImpl(s.c_str(), &ram);
Vortex_SOC v(&ram);
bool curr = v.simulate();
if ( curr) std::cerr << GREEN << "Test Passed: " << s << std::endl;
if (!curr) std::cerr << RED << "Test Failed: " << s << std::endl;
std::cerr << DEFAULT;
@@ -90,7 +93,7 @@ int main(int argc, char **argv)
char testing[] = "../../runtime/mains/simple/vx_simple_main.hex";
// char testing[] = "../../emulator/riscv_tests/rv32ui-p-lw.hex";
// char testing[] = "../../emulator/riscv_tests/rv32ui-p-sw.hex";
Vortex v;
// const char *testing;
// if (argc >= 2) {
@@ -99,14 +102,18 @@ int main(int argc, char **argv)
// testing = "../../kernel/vortex_test.hex";
// }
std::cerr << testing << std::endl;
std::cerr << testing << std::endl;
RAM ram;
loadHexImpl(testing, &ram);
Vortex_SOC v(&ram);
bool curr = v.simulate();
bool curr = v.simulate(testing);
if ( curr) std::cerr << GREEN << "Test Passed: " << testing << std::endl;
if (!curr) std::cerr << RED << "Test Failed: " << testing << std::endl;
return !curr;
#endif
}
}

15
rtl/simulate/ram.h
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@@ -1,5 +1,4 @@
#ifndef __RAM__
#define __RAM__
// #include "string.h"
@@ -12,8 +11,8 @@
class RAM;
uint32_t hti(char);
uint32_t hToI(char *, uint32_t);
void loadHexImpl(char *,RAM*);
uint32_t hToI(const char *, uint32_t);
void loadHexImpl(const char *,RAM*);
class RAM{
public:
@@ -26,6 +25,10 @@ public:
for(uint32_t i = 0;i < (1 << 12);i++) if(mem[i]) delete [] mem[i];
}
size_t size() const {
return (1ull << 32);
}
void clear(){
for(uint32_t i = 0;i < (1 << 12);i++)
{
@@ -149,7 +152,7 @@ public:
// MEMORY UTILS
uint32_t hti(char c) {
inline uint32_t hti(char c) {
if (c >= 'A' && c <= 'F')
return c - 'A' + 10;
if (c >= 'a' && c <= 'f')
@@ -157,7 +160,7 @@ uint32_t hti(char c) {
return c - '0';
}
uint32_t hToI(char *c, uint32_t size) {
inline uint32_t hToI(const char *c, uint32_t size) {
uint32_t value = 0;
for (uint32_t i = 0; i < size; i++) {
value += hti(c[i]) << ((size - i - 1) * 4);
@@ -167,7 +170,7 @@ uint32_t hToI(char *c, uint32_t size) {
void loadHexImpl(const char *path, RAM* mem) {
inline void loadHexImpl(const char *path, RAM* mem) {
mem->clear();
FILE *fp = fopen(path, "r");
if(fp == 0){

27
rtl/simulate/test_bench.cpp
View File

@@ -1,4 +1,4 @@
#include "test_bench.h"
#include "Vortex.h"
#define NUM_TESTS 46
@@ -66,13 +66,16 @@ int main(int argc, char **argv)
};
for (std::string s : tests) {
Vortex v;
std::cerr << DEFAULT << "\n---------------------------------------\n";
std::cerr << s << std::endl;
bool curr = v.simulate(s);
RAM ram;
loadHexImpl(s.c_str(), &ram);
Vortex v(&ram);
bool curr = v.simulate();
if ( curr) std::cerr << GREEN << "Test Passed: " << s << std::endl;
if (!curr) std::cerr << RED << "Test Failed: " << s << std::endl;
std::cerr << DEFAULT;
@@ -89,9 +92,9 @@ int main(int argc, char **argv)
#else
char testing[] = "../../runtime/mains/simple/vx_simple_main.hex";
// char testing[] = "../../emulator/riscv_tests/rv32ui-p-lw.hex";
// char testing[] = "../../emulator/riscv_tests/rv32ui-p-sw.hex";
Vortex v;
//char testing[] = "../../emulator/riscv_tests/rv32ui-p-lw.hex";
//char testing[] = "../../emulator/riscv_tests/rv32ui-p-sw.hex";
// const char *testing;
// if (argc >= 2) {
@@ -100,14 +103,18 @@ int main(int argc, char **argv)
// testing = "../../kernel/vortex_test.hex";
// }
std::cerr << testing << std::endl;
std::cerr << testing << std::endl;
RAM ram;
loadHexImpl(testing, &ram);
Vortex v(&ram);
bool curr = v.simulate();
bool curr = v.simulate(testing);
if ( curr) std::cerr << GREEN << "Test Passed: " << testing << std::endl;
if (!curr) std::cerr << RED << "Test Failed: " << testing << std::endl;
return !curr;
#endif
}
}