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Update Vortex core for Blackwell tensor instructions

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- Add Blackwell tensor core support in VX_tensor_blackwell_core.sv
- Update decode, execute, and dispatch logic for new instructions
- Extend VX_define.vh and VX_types.vh with Blackwell ISA definitions
This commit is contained in:
abnerhexu
2026-05-06 14:50:54 +08:00
parent cb912d3b8b
commit 323ed7d7e9
17 changed files with 492 additions and 114 deletions
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35
hw/rtl/core/VX_trace.vh
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@@ -22,6 +22,9 @@ task trace_ex_type(input int level, input [`EX_BITS-1:0] ex_type);
`EX_LSU: `TRACE(level, ("LSU"));
`EX_FPU: `TRACE(level, ("FPU"));
`EX_SFU: `TRACE(level, ("SFU"));
`ifdef EXT_T_ENABLE
`EX_TENSOR: `TRACE(level, ("TENSOR"));
`endif
default: `TRACE(level, ("?"));
endcase
endtask
@@ -36,22 +39,26 @@ task trace_ex_op(input int level,
`UNUSED_ARG(input [`XLEN-1:0] imm)
);
logic fdst_d;
logic fcvt_l;
logic rd_float;
`ifdef FLEN_64
logic fdst_d = imm[0];
fdst_d = imm[0];
`else
logic fdst_d = 0;
fdst_d = 0;
`endif
`ifdef XLEN_64
logic fcvt_l = imm[1];
fcvt_l = imm[1];
`else
logic fcvt_l = 0;
fcvt_l = 0;
`endif
`ifdef EXT_F_ENABLE
logic rd_float = 1'(rd >> 5) || 1'(rs2 >> 5);
rd_float = 1'(rd >> 5) || 1'(rs2 >> 5);
`else
logic rd_float = 0;
rd_float = 0;
`endif
case (ex_type)
@@ -359,6 +366,22 @@ task trace_ex_op(input int level,
default: `TRACE(level, ("?"));
endcase
end
`ifdef EXT_T_ENABLE
`EX_TENSOR: begin
case (`INST_ALU_BITS'(op_type))
`INST_TENSOR_HMMA: `TRACE(level, ("HMMA"));
`INST_TENSOR_HGMMA: `TRACE(level, ("HGMMA"));
`INST_TENSOR_HGMMA_WAIT: `TRACE(level, ("HGMMA_WAIT"));
`INST_TENSOR_TCGEN05_CP: `TRACE(level, ("TCGEN05_CP"));
`INST_TENSOR_TCGEN05_CP_WAIT: `TRACE(level, ("TCGEN05_CP_WAIT"));
`INST_TENSOR_BWGMMA: `TRACE(level, ("BWGMMA"));
`INST_TENSOR_BWGMMA_WAIT: `TRACE(level, ("BWGMMA_WAIT"));
`INST_TENSOR_TCGEN05_LD: `TRACE(level, ("TCGEN05_LD"));
`INST_TENSOR_TCGEN05_ST: `TRACE(level, ("TCGEN05_ST"));
default: `TRACE(level, ("?"));
endcase
end
`endif
default: `TRACE(level, ("?"));
endcase
endtask