Update Vortex core for Blackwell tensor instructions

- Add Blackwell tensor core support in VX_tensor_blackwell_core.sv
- Update decode, execute, and dispatch logic for new instructions
- Extend VX_define.vh and VX_types.vh with Blackwell ISA definitions

hw/rtl/core/VX_ibuffer.sv

@@ -12,6 +12,7 @@
 // limitations under the License.
 
 `include "VX_define.vh"
+`include "VX_trace.vh"
 
 module VX_ibuffer import VX_gpu_pkg::*; #(
     parameter CORE_ID = 0
@@ -36,6 +37,20 @@ module VX_ibuffer import VX_gpu_pkg::*; #(
     
     assign decode_if.ready = ibuf_ready_in[decode_isw];
 
+`ifdef SIMULATION
+`ifdef DBG_TRACE_CORE_PIPELINE_VCS
+    wire decode_probe_pc = (decode_if.data.PC >= 32'h80000240) && (decode_if.data.PC <= 32'h80000260);
+    always @(posedge clk) begin
+        if (!reset && (CORE_ID == 0) && ($time > `TRACE_STARTTIME) && decode_if.valid && decode_probe_pc) begin
+            `TRACE(2, ("%d: core%0d-ibuffer-probe: wid=%0d, PC=0x%0h, valid=%b, ready=%b, isw=%0d, ibuf_ready=%b, tmask=%b, ex=0x%0h, op=0x%0h (#%0d)\n",
+                $time, CORE_ID, decode_if.data.wid, decode_if.data.PC, decode_if.valid, decode_if.ready,
+                decode_isw, ibuf_ready_in, decode_if.data.tmask, decode_if.data.ex_type, decode_if.data.op_type,
+                decode_if.data.uuid));
+        end
+    end
+`endif
+`endif
+
     VX_ibuffer_if uop_sequencer_if [`ISSUE_WIDTH]();
 
     for (genvar i = 0; i < `ISSUE_WIDTH; ++i) begin