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Update Vortex core for Blackwell tensor instructions

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- Add Blackwell tensor core support in VX_tensor_blackwell_core.sv
- Update decode, execute, and dispatch logic for new instructions
- Extend VX_define.vh and VX_types.vh with Blackwell ISA definitions
This commit is contained in:
abnerhexu
2026-05-06 14:50:54 +08:00
parent cb912d3b8b
commit 323ed7d7e9
17 changed files with 492 additions and 114 deletions
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40
hw/rtl/core/VX_decode.sv
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@@ -564,11 +564,45 @@ module VX_decode #(
3'b011: op_type = `INST_TENSOR_TCGEN05_CP_WAIT;
3'b100: op_type = `INST_TENSOR_TCGEN05_LD;
3'b101: op_type = `INST_TENSOR_TCGEN05_ST;
3'b110: op_type = `INST_TENSOR_TCGEN05_CB;
default: ;
endcase
`USED_IREG (rd);
`USED_IREG (rs1);
`USED_IREG (rs2);
case (func3)
3'b000: begin // BWGMMA: rs1=tmem_a, rs2=smem_b, rd field=tmem_c source
`USED_IREG (rs1);
`USED_IREG (rs2);
`ifdef EXT_F_ENABLE
rs3_r = {1'b0, rd};
`else
rs3_r = rd;
`endif
use_rs3 = 1;
end
3'b010, 3'b110: begin // TCGEN05_CP/CB: rs1=tmem, rs2=global memory address
`USED_IREG (rs1);
`USED_IREG (rs2);
end
3'b100: begin // TCGEN05_LD: rs1=tmem, rd=FP destination
`USED_IREG (rs1);
`ifdef EXT_F_ENABLE
`USED_FREG (rd);
`else
`USED_IREG (rd);
`endif
end
3'b101: begin // TCGEN05_ST: rs1=tmem, rd field=FP source
`USED_IREG (rs1);
`ifdef EXT_F_ENABLE
rd_r = {1'b1, rd};
rs3_r = {1'b1, rd};
`else
rd_r = rd;
rs3_r = rd;
`endif
use_rs3 = 1;
end
default: ;
endcase
`else
ex_type = `EX_TENSOR;
op_type = `INST_TENSOR_HMMA;