Update Vortex core for Blackwell tensor instructions

- Add Blackwell tensor core support in VX_tensor_blackwell_core.sv
- Update decode, execute, and dispatch logic for new instructions
- Extend VX_define.vh and VX_types.vh with Blackwell ISA definitions

hw/rtl/core/VX_commit.sv

@@ -208,7 +208,7 @@ module VX_commit import VX_gpu_pkg::*; #(
     // Writeback
 
     for (genvar i = 0; i < `ISSUE_WIDTH; ++i) begin
-        assign writeback_if[i].valid     = commit_if[i].valid && commit_if[i].data.wb;
+        assign writeback_if[i].valid     = commit_if[i].valid && (commit_if[i].data.wb || commit_if[i].data.tensor);
         assign writeback_if[i].data.uuid = commit_if[i].data.uuid; 
         assign writeback_if[i].data.wis  = wid_to_wis(commit_if[i].data.wid);
         assign writeback_if[i].data.PC   = commit_if[i].data.PC; 
@@ -224,7 +224,7 @@ module VX_commit import VX_gpu_pkg::*; #(
     // simulation helper signal to get RISC-V tests Pass/Fail status
     reg [`NUM_REGS-1:0][`XLEN-1:0] sim_wb_value_r;
     always @(posedge clk) begin
-        if (writeback_if[0].valid) begin
+        if (writeback_if[0].valid && !writeback_if[0].data.tensor) begin
             sim_wb_value_r[writeback_if[0].data.rd] <= writeback_if[0].data.data[0];
         end
     end