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fixed all build warnings

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This commit is contained in:
Blaise Tine
2020-04-16 10:22:46 -04:00
parent 81745f08c9
commit 31f906f9fd
42 changed files with 497 additions and 509 deletions
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6
hw/rtl/interfaces/VX_dram_req_rsp_inter.v
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@@ -6,18 +6,18 @@
`define VX_DRAM_REQ_RSP_INTER
interface VX_dram_req_rsp_inter #(
parameter NUMBER_BANKS = 8,
parameter NUM_BANKS = 8,
parameter NUM_WORDS_PER_BLOCK = 4) ();
// Req
wire [31:0] o_m_evict_addr;
wire [31:0] o_m_read_addr;
wire o_m_valid;
wire[NUMBER_BANKS - 1:0][NUM_WORDS_PER_BLOCK-1:0][31:0] o_m_writedata;
wire[NUM_BANKS - 1:0][NUM_WORDS_PER_BLOCK-1:0][31:0] o_m_writedata;
wire o_m_read_or_write;
// Rsp
wire[NUMBER_BANKS - 1:0][NUM_WORDS_PER_BLOCK-1:0][31:0] i_m_readdata;
wire[NUM_BANKS - 1:0][NUM_WORDS_PER_BLOCK-1:0][31:0] i_m_readdata;
wire i_m_ready;

22
hw/rtl/interfaces/VX_gpu_dcache_req_inter.v
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@@ -8,23 +8,23 @@
interface VX_gpu_dcache_req_inter
#(
parameter NUMBER_REQUESTS = 32
parameter NUM_REQUESTS = 32
)
();
// Core Request
wire [NUMBER_REQUESTS-1:0] core_req_valid;
wire [NUMBER_REQUESTS-1:0][31:0] core_req_addr;
wire [NUMBER_REQUESTS-1:0][31:0] core_req_writedata;
wire [NUMBER_REQUESTS-1:0][2:0] core_req_mem_read;
wire [NUMBER_REQUESTS-1:0][2:0] core_req_mem_write;
wire [4:0] core_req_rd;
wire [NUMBER_REQUESTS-1:0][1:0] core_req_wb;
wire [`NW_BITS-1:0] core_req_warp_num;
wire [31:0] core_req_pc;
wire [NUM_REQUESTS-1:0] core_req_valid;
wire [NUM_REQUESTS-1:0][31:0] core_req_addr;
wire [NUM_REQUESTS-1:0][31:0] core_req_writedata;
wire [NUM_REQUESTS-1:0][2:0] core_req_mem_read;
wire [NUM_REQUESTS-1:0][2:0] core_req_mem_write;
wire [4:0] core_req_rd;
wire [NUM_REQUESTS-1:0][1:0] core_req_wb;
wire [`NW_BITS-1:0] core_req_warp_num;
wire [31:0] core_req_pc;
// Can't WB
wire core_no_wb_slot;
wire core_no_wb_slot;
endinterface

16
hw/rtl/interfaces/VX_gpu_dcache_res_inter.v
View File

@@ -8,20 +8,20 @@
interface VX_gpu_dcache_res_inter
#(
parameter NUMBER_REQUESTS = 32
parameter NUM_REQUESTS = 32
)
();
// Cache WB
wire [NUMBER_REQUESTS-1:0] core_wb_valid;
wire [4:0] core_wb_req_rd;
wire [1:0] core_wb_req_wb;
wire [`NW_BITS-1:0] core_wb_warp_num;
wire [NUMBER_REQUESTS-1:0][31:0] core_wb_readdata;
wire [NUMBER_REQUESTS-1:0][31:0] core_wb_pc;
wire [NUM_REQUESTS-1:0] core_wb_valid;
wire [4:0] core_wb_req_rd;
wire [1:0] core_wb_req_wb;
wire [`NW_BITS-1:0] core_wb_warp_num;
wire [NUM_REQUESTS-1:0][31:0] core_wb_readdata;
wire [NUM_REQUESTS-1:0][31:0] core_wb_pc;
// Cache Full
wire delay_req;
wire delay_req;
endinterface