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fixed all build warnings

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This commit is contained in:
Blaise Tine
2020-04-16 10:22:46 -04:00
parent 81745f08c9
commit 31f906f9fd
42 changed files with 497 additions and 509 deletions
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88
hw/rtl/generic_cache/VX_cache_req_queue.v
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@@ -7,11 +7,11 @@ module VX_cache_req_queue
// Size of line inside a bank in bytes
parameter BANK_LINE_SIZE_BYTES = 16,
// Number of banks {1, 2, 4, 8,...}
parameter NUMBER_BANKS = 8,
parameter NUM_BANKS = 8,
// Size of a word in bytes
parameter WORD_SIZE_BYTES = 4,
// Number of Word requests per cycle {1, 2, 4, 8, ...}
parameter NUMBER_REQUESTS = 2,
parameter NUM_REQUESTS = 2,
// Number of cycles to complete stage 1 (read from memory)
parameter STAGE_1_CYCLES = 2,
@@ -50,25 +50,25 @@ module VX_cache_req_queue
// Enqueue Data
input wire reqq_push,
input wire [NUMBER_REQUESTS-1:0] bank_valids,
input wire [NUMBER_REQUESTS-1:0][31:0] bank_addr,
input wire [NUMBER_REQUESTS-1:0][`WORD_SIZE_RNG] bank_writedata,
input wire [NUM_REQUESTS-1:0] bank_valids,
input wire [NUM_REQUESTS-1:0][31:0] bank_addr,
input wire [NUM_REQUESTS-1:0][`WORD_SIZE_RNG] bank_writedata,
input wire [4:0] bank_rd,
input wire [NUMBER_REQUESTS-1:0][1:0] bank_wb,
input wire [`NW_BITS-1:0] bank_warp_num,
input wire [NUMBER_REQUESTS-1:0][2:0] bank_mem_read,
input wire [NUMBER_REQUESTS-1:0][2:0] bank_mem_write,
input wire [NUM_REQUESTS-1:0][1:0] bank_wb,
input wire [`NW_BITS-1:0] bank_warp_num,
input wire [NUM_REQUESTS-1:0][2:0] bank_mem_read,
input wire [NUM_REQUESTS-1:0][2:0] bank_mem_write,
input wire [31:0] bank_pc,
// Dequeue Data
input wire reqq_pop,
output wire reqq_req_st0,
output wire [`vx_clog2(NUMBER_REQUESTS)-1:0] reqq_req_tid_st0,
output wire [`LOG2UP(NUM_REQUESTS)-1:0] reqq_req_tid_st0,
output wire [31:0] reqq_req_addr_st0,
output wire [`WORD_SIZE_RNG] reqq_req_writedata_st0,
output wire [4:0] reqq_req_rd_st0,
output wire [1:0] reqq_req_wb_st0,
output wire [`NW_BITS-1:0] reqq_req_warp_num_st0,
output wire [`NW_BITS-1:0] reqq_req_warp_num_st0,
output wire [2:0] reqq_req_mem_read_st0,
output wire [2:0] reqq_req_mem_write_st0,
output wire [31:0] reqq_req_pc_st0,
@@ -78,39 +78,39 @@ module VX_cache_req_queue
output wire reqq_full
);
wire [NUMBER_REQUESTS-1:0] out_per_valids;
wire [NUMBER_REQUESTS-1:0][31:0] out_per_addr;
wire [NUMBER_REQUESTS-1:0][`WORD_SIZE_RNG] out_per_writedata;
wire [4:0] out_per_rd;
wire [NUMBER_REQUESTS-1:0][1:0] out_per_wb;
wire [`NW_BITS-1:0] out_per_warp_num;
wire [NUMBER_REQUESTS-1:0][2:0] out_per_mem_read;
wire [NUMBER_REQUESTS-1:0][2:0] out_per_mem_write;
wire [31:0] out_per_pc;
wire [NUM_REQUESTS-1:0] out_per_valids;
wire [NUM_REQUESTS-1:0][31:0] out_per_addr;
wire [NUM_REQUESTS-1:0][`WORD_SIZE_RNG] out_per_writedata;
wire [4:0] out_per_rd;
wire [NUM_REQUESTS-1:0][1:0] out_per_wb;
wire [`NW_BITS-1:0] out_per_warp_num;
wire [NUM_REQUESTS-1:0][2:0] out_per_mem_read;
wire [NUM_REQUESTS-1:0][2:0] out_per_mem_write;
wire [31:0] out_per_pc;
reg [NUMBER_REQUESTS-1:0] use_per_valids;
reg [NUMBER_REQUESTS-1:0][31:0] use_per_addr;
reg [NUMBER_REQUESTS-1:0][`WORD_SIZE_RNG] use_per_writedata;
reg [4:0] use_per_rd;
reg [NUMBER_REQUESTS-1:0][1:0] use_per_wb;
reg [31:0] use_per_pc;
reg [`NW_BITS-1:0] use_per_warp_num;
reg [NUMBER_REQUESTS-1:0][2:0] use_per_mem_read;
reg [NUMBER_REQUESTS-1:0][2:0] use_per_mem_write;
reg [NUM_REQUESTS-1:0] use_per_valids;
reg [NUM_REQUESTS-1:0][31:0] use_per_addr;
reg [NUM_REQUESTS-1:0][`WORD_SIZE_RNG] use_per_writedata;
reg [4:0] use_per_rd;
reg [NUM_REQUESTS-1:0][1:0] use_per_wb;
reg [31:0] use_per_pc;
reg [`NW_BITS-1:0] use_per_warp_num;
reg [NUM_REQUESTS-1:0][2:0] use_per_mem_read;
reg [NUM_REQUESTS-1:0][2:0] use_per_mem_write;
wire [NUMBER_REQUESTS-1:0] qual_valids;
wire [NUMBER_REQUESTS-1:0][31:0] qual_addr;
wire [NUMBER_REQUESTS-1:0][`WORD_SIZE_RNG] qual_writedata;
wire [4:0] qual_rd;
wire [NUMBER_REQUESTS-1:0][1:0] qual_wb;
wire [`NW_BITS-1:0] qual_warp_num;
wire [NUMBER_REQUESTS-1:0][2:0] qual_mem_read;
wire [NUMBER_REQUESTS-1:0][2:0] qual_mem_write;
wire [31:0] qual_pc;
wire [NUM_REQUESTS-1:0] qual_valids;
wire [NUM_REQUESTS-1:0][31:0] qual_addr;
wire [NUM_REQUESTS-1:0][`WORD_SIZE_RNG] qual_writedata;
wire [4:0] qual_rd;
wire [NUM_REQUESTS-1:0][1:0] qual_wb;
wire [`NW_BITS-1:0] qual_warp_num;
wire [NUM_REQUESTS-1:0][2:0] qual_mem_read;
wire [NUM_REQUESTS-1:0][2:0] qual_mem_write;
wire [31:0] qual_pc;
reg [NUMBER_REQUESTS-1:0] updated_valids;
reg [NUM_REQUESTS-1:0] updated_valids;
wire o_empty;
@@ -120,7 +120,7 @@ module VX_cache_req_queue
wire push_qual = reqq_push && !reqq_full;
wire pop_qual = !out_empty && use_empty;
VX_generic_queue_ll #(.DATAW( (NUMBER_REQUESTS * (1+32+`WORD_SIZE)) + 5 + (NUMBER_REQUESTS*2) + (`NW_BITS-1+1) + (NUMBER_REQUESTS * (3 + 3)) + 32 ), .SIZE(REQQ_SIZE)) reqq_queue(
VX_generic_queue_ll #(.DATAW( (NUM_REQUESTS * (1+32+`WORD_SIZE)) + 5 + (NUM_REQUESTS*2) + (`NW_BITS-1+1) + (NUM_REQUESTS * (3 + 3)) + 32 ), .SIZE(REQQ_SIZE)) reqq_queue(
.clk (clk),
.reset (reset),
.push (push_qual),
@@ -132,7 +132,7 @@ module VX_cache_req_queue
);
wire[NUMBER_REQUESTS-1:0] real_out_per_valids = out_per_valids & {NUMBER_REQUESTS{~out_empty}};
wire[NUM_REQUESTS-1:0] real_out_per_valids = out_per_valids & {NUM_REQUESTS{~out_empty}};
assign qual_valids = use_per_valids;
assign qual_addr = use_per_addr;
@@ -144,9 +144,9 @@ module VX_cache_req_queue
assign qual_mem_write = use_per_mem_write;
assign qual_pc = use_per_pc;
wire[`vx_clog2(NUMBER_REQUESTS)-1:0] qual_request_index;
wire[`LOG2UP(NUM_REQUESTS)-1:0] qual_request_index;
wire qual_has_request;
VX_generic_priority_encoder #(.N(NUMBER_REQUESTS)) VX_sel_bank(
VX_generic_priority_encoder #(.N(NUM_REQUESTS)) VX_sel_bank(
.valids(qual_valids),
.index (qual_request_index),
.found (qual_has_request)
@@ -155,7 +155,7 @@ module VX_cache_req_queue
assign reqq_empty = !qual_has_request;
assign reqq_req_st0 = qual_has_request;
assign reqq_req_tid_st0 = qual_request_index;
assign reqq_req_addr_st0 = qual_addr [qual_request_index];
assign reqq_req_addr_st0 = qual_addr[qual_request_index];
assign reqq_req_writedata_st0 = qual_writedata[qual_request_index];
assign reqq_req_rd_st0 = qual_rd;
assign reqq_req_wb_st0 = qual_wb[qual_request_index];