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fixed all build warnings

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This commit is contained in:
Blaise Tine
2020-04-16 10:22:46 -04:00
parent 81745f08c9
commit 31f906f9fd
42 changed files with 497 additions and 509 deletions
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4
hw/rtl/cache/VX_Cache_Bank.v vendored
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@@ -57,10 +57,10 @@ module VX_Cache_Bank
evicted_way
);
// localparam NUMBER_BANKS = `CACHE_BANKS;
// localparam NUM_BANKS = `CACHE_BANKS;
// localparam CACHE_BLOCK_PER_BANK = (`CACHE_BLOCK / `CACHE_BANKS);
// localparam NUM_WORDS_PER_BLOCK = `CACHE_BLOCK / (`CACHE_BANKS*4);
// localparam NUMBER_INDEXES = `NUM_IND;
// localparam NUM_INDEXES = `NUM_IND;
localparam CACHE_IDLE = 0; // Idle
localparam SEND_MEM_REQ = 1; // Write back this block into memory

6
hw/rtl/cache/VX_cache_bank_valid.v vendored
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@@ -2,14 +2,14 @@
module VX_cache_bank_valid
#(
parameter NUMBER_BANKS = 8,
parameter NUM_BANKS = 8,
parameter LOG_NUM_BANKS = 3,
parameter NUM_REQ = 1
)
(
input wire [NUM_REQ-1:0] i_p_valid,
input wire [NUM_REQ-1:0][31:0] i_p_addr,
output reg [NUMBER_BANKS - 1 : 0][NUM_REQ-1:0] thread_track_banks
output reg [NUM_BANKS - 1 : 0][NUM_REQ-1:0] thread_track_banks
);
generate
@@ -18,7 +18,7 @@ module VX_cache_bank_valid
thread_track_banks = 0;
for (t_id = 0; t_id < NUM_REQ; t_id = t_id + 1)
begin
if (NUMBER_BANKS != 1) begin
if (NUM_BANKS != 1) begin
thread_track_banks[i_p_addr[t_id][2+LOG_NUM_BANKS-1:2]][t_id] = i_p_valid[t_id];
end else begin
thread_track_banks[0][t_id] = i_p_valid[t_id];

4
hw/rtl/cache/VX_cache_data.v vendored
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@@ -46,10 +46,10 @@ module VX_cache_data
);
//localparam NUMBER_BANKS = CACHE_BANKS;
//localparam NUM_BANKS = CACHE_BANKS;
//localparam CACHE_BLOCK_PER_BANK = (CACHE_BLOCK / CACHE_BANKS);
// localparam NUM_WORDS_PER_BLOCK = CACHE_BLOCK / (CACHE_BANKS*4);
//localparam NUMBER_INDEXES = NUM_IND;
//localparam NUM_INDEXES = NUM_IND;
wire currently_writing = (|we);
wire update_dirty = ((!dirty_use) && currently_writing) || (evict);

4
hw/rtl/cache/VX_cache_data_per_index.v vendored
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@@ -33,10 +33,10 @@ module VX_cache_data_per_index
output wire dirty_use
);
//localparam NUMBER_BANKS = CACHE_BANKS;
//localparam NUM_BANKS = CACHE_BANKS;
//localparam CACHE_BLOCK_PER_BANK = (CACHE_BLOCK / CACHE_BANKS);
// localparam NUM_WORDS_PER_BLOCK = CACHE_BLOCK / (CACHE_BANKS*4);
//localparam NUMBER_INDEXES = `DCACHE_NUM_IND;
//localparam NUM_INDEXES = `DCACHE_NUM_IND;
wire [CACHE_WAYS-1:0][TAG_SIZE_END:TAG_SIZE_START] tag_use_per_way;
wire [CACHE_WAYS-1:0][NUM_WORDS_PER_BLOCK-1:0][31:0] data_use_per_way;

6
hw/rtl/cache/VX_d_cache.v vendored
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@@ -66,7 +66,7 @@ module VX_d_cache
i_m_ready
);
//parameter NUMBER_BANKS = `CACHE_BANKS;
//parameter NUM_BANKS = `CACHE_BANKS;
//localparam NUM_WORDS_PER_BLOCK = `CACHE_BLOCK / (`CACHE_BANKS*4);
//localparam CACHE_BLOCK_PER_BANK = (`CACHE_BLOCK / `CACHE_BANKS);
@@ -148,7 +148,7 @@ module VX_d_cache
VX_cache_bank_valid #(.NUMBER_BANKS (CACHE_BANKS),
VX_cache_bank_valid #(.NUM_BANKS (CACHE_BANKS),
.LOG_NUM_BANKS (LOG_NUM_BANKS),
.NUM_REQ (NUM_REQ)) multip_banks(
.i_p_valid (use_valid),
@@ -261,7 +261,7 @@ module VX_d_cache
miss_addr <= 0;
// evict_addr <= 0;
// threads_serviced_Qual = 0;
// for (init_b = 0; init_b < NUMBER_BANKS; init_b=init_b+1)
// for (init_b = 0; init_b < NUM_BANKS; init_b=init_b+1)
// begin
// debug_hit_per_bank_mask[init_b] <= 0;
// end

12
hw/rtl/cache/VX_d_cache_encapsulate.v vendored
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@@ -25,7 +25,7 @@ module VX_d_cache_encapsulate (
i_m_ready
);
parameter NUMBER_BANKS = 8;
parameter NUM_BANKS = 8;
@@ -39,7 +39,7 @@ module VX_d_cache_encapsulate (
input wire [31:0] i_p_writedata[`NUM_THREADS-1:0];
input wire i_p_read_or_write;
input wire [31:0] i_m_readdata[NUMBER_BANKS - 1:0][`NUM_WORDS_PER_BLOCK-1:0];
input wire [31:0] i_m_readdata[NUM_BANKS - 1:0][`NUM_WORDS_PER_BLOCK-1:0];
input wire i_m_ready;
output reg [31:0] o_p_readdata[`NUM_THREADS-1:0];
@@ -48,7 +48,7 @@ module VX_d_cache_encapsulate (
output reg [31:0] o_m_addr;
output reg o_m_valid;
output reg [31:0] o_m_writedata[NUMBER_BANKS - 1:0][`NUM_WORDS_PER_BLOCK-1:0];
output reg [31:0] o_m_writedata[NUM_BANKS - 1:0][`NUM_WORDS_PER_BLOCK-1:0];
output reg o_m_read_or_write;
@@ -60,8 +60,8 @@ module VX_d_cache_encapsulate (
reg [`NUM_THREADS-1:0][31:0] o_p_readdata_inter;
reg [`NUM_THREADS-1:0] o_p_readdata_valid_inter;
reg[NUMBER_BANKS - 1:0][`NUM_WORDS_PER_BLOCK-1:0][31:0] o_m_writedata_inter;
wire[NUMBER_BANKS - 1:0][`NUM_WORDS_PER_BLOCK-1:0][31:0] i_m_readdata_inter;
reg[NUM_BANKS - 1:0][`NUM_WORDS_PER_BLOCK-1:0][31:0] o_m_writedata_inter;
wire[NUM_BANKS - 1:0][`NUM_WORDS_PER_BLOCK-1:0][31:0] i_m_readdata_inter;
genvar curr_thraed, curr_bank, curr_word;
@@ -74,7 +74,7 @@ module VX_d_cache_encapsulate (
assign o_p_readdata_valid[curr_thraed] = o_p_readdata_valid_inter[curr_thraed];
end
for (curr_bank = 0; curr_bank < NUMBER_BANKS; curr_bank = curr_bank + 1) begin : banks
for (curr_bank = 0; curr_bank < NUM_BANKS; curr_bank = curr_bank + 1) begin : banks
for (curr_word = 0; curr_word < `NUM_WORDS_PER_BLOCK; curr_word = curr_word + 1) begin : words
assign o_m_writedata[curr_bank][curr_word] = o_m_writedata_inter[curr_bank][curr_word];

6
hw/rtl/cache/VX_d_cache_tb.v vendored
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@@ -3,7 +3,7 @@
module VX_d_cache_tb;
parameter NUMBER_BANKS = 8;
parameter NUM_BANKS = 8;
reg clk, reset, im_ready;
reg [`NUM_THREADS-1:0] i_p_valid;
@@ -16,9 +16,9 @@ module VX_d_cache_tb;
reg o_p_waitrequest;
reg [13:0] o_m_addr; // Only one address is sent out at a time to memory
reg o_m_valid;
reg [(NUMBER_BANKS * 32) - 1:0] o_m_writedata;
reg [(NUM_BANKS * 32) - 1:0] o_m_writedata;
reg o_m_read_or_write; //, o_m_write;
reg [(NUMBER_BANKS * 32) - 1:0] i_m_readdata; // Read Data that is passed from the memory module back to the controller
reg [(NUM_BANKS * 32) - 1:0] i_m_readdata; // Read Data that is passed from the memory module back to the controller
VX_d_cache d_cache(.clk(clk),

16
hw/rtl/cache/d_cache_test_bench.h vendored
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@@ -38,9 +38,9 @@ class VX_d_cache
long int curr_cycle;
int stats_total_cycles = 0;
int stats_dram_accesses = 0;
#ifdef VCD_OUTPUT
#ifdef VCD_OUTPUT
VerilatedVcdC *m_trace;
#endif
#endif
};
@@ -49,22 +49,20 @@ VX_d_cache::VX_d_cache() : curr_cycle(0), stats_total_cycles(0), stats_dram_acce
{
this->vx_d_cache_ = new VVX_d_cache_encapsulate;
#ifdef VCD_OUTPUT
#ifdef VCD_OUTPUT
this->m_trace = new VerilatedVcdC;
this->vx_d_cache_->trace(m_trace, 99);
this->m_trace->open("trace.vcd");
#endif
#endif
//this->results.open("../results.txt");
}
VX_d_cache::~VX_d_cache()
{
{
delete this->vx_d_cache_;
#ifdef VCD_OUTPUT
#ifdef VCD_OUTPUT
m_trace->close();
#endif
#endif
}
bool VX_d_cache::operation(int counter_value, bool do_op) {