merged fpu_port branch

2020-07-31 17:13:22 -04:00
parent 4bdab8903e 836a735555
commit 31ee824862
508 changed files with 45407 additions and 41832 deletions
--- a/hw/simulate/Makefile
+++ b/hw/simulate/Makefile
@@ -17,7 +17,8 @@ DBG_PRINT_FLAGS += -DDBG_PRINT_OPAE
 DBG_FLAGS += $(DBG_PRINT_FLAGS)
 DBG_FLAGS += -DDBG_CORE_REQ_INFO

-INCLUDE = -I../rtl/ -I../rtl/libs -I../rtl/interfaces -I../rtl/cache -I../rtl/simulate
+FPU_INCLUDE = -I../rtl/fp_cores/fpnew/src/common_cells/include -I../rtl/fp_cores/fpnew/src/common_cells/src -I../rtl/fp_cores/fpnew/src/fpu_div_sqrt_mvp/hdl -I../rtl/fp_cores/fpnew/src 
+INCLUDE = -I../rtl/ -I../rtl/libs -I../rtl/interfaces -I../rtl/cache -I../rtl/fp_cores -I../rtl/simulate $(FPU_INCLUDE)

 SRCS = simulator.cpp testbench.cpp

@@ -28,30 +29,31 @@ CF += -std=c++11 -fms-extensions -I../..
 VF += --language 1800-2009 --assert -Wall -Wpedantic
 VF += -Wno-DECLFILENAME
 VF += --x-initial unique --x-assign unique
-VF += -exe $(SRCS) $(INCLUDE)
+VF += --exe $(SRCS) $(INCLUDE)
+VF += --cc Vortex.v --top-module Vortex
+VF += verilator.vlt

 DBG += -DVCD_OUTPUT $(DBG_FLAGS)
-DBG += -DDBG_CORE_REQ_INFO

 THREADS ?= $(shell python3 -c 'import multiprocessing as mp; print(max(1, mp.cpu_count() // 2))')

 gen-s:
-	verilator $(VF) -DNDEBUG -cc Vortex.v $(SINGLECORE) -CFLAGS '$(CF) -DNDEBUG $(SINGLECORE)'
+	verilator $(VF) -DNDEBUG  $(SINGLECORE) -CFLAGS '$(CF) -DNDEBUG $(SINGLECORE)'

 gen-sd:
-	verilator $(VF) -cc Vortex.v $(SINGLECORE) -CFLAGS '$(CF) -g -O0  $(DBG) $(SINGLECORE)' --trace $(DBG)
+	verilator $(VF) $(SINGLECORE) -CFLAGS '$(CF) -g -O0 $(DBG) $(SINGLECORE)' --trace $(DBG)

 gen-st:
-	verilator $(VF) -DNDEBUG -cc Vortex.v $(SINGLECORE) -CFLAGS '$(CF) -DNDEBUG -O2 $(SINGLECORE)' --threads $(THREADS)
+	verilator $(VF) -DNDEBUG $(SINGLECORE) -CFLAGS '$(CF) -DNDEBUG -O2 $(SINGLECORE)' --threads $(THREADS)

 gen-m:
-	verilator $(VF) -DNDEBUG -cc Vortex.v $(MULTICORE) -CFLAGS '$(CF) -DNDEBUG $(MULTICORE)'
+	verilator $(VF) -DNDEBUG $(MULTICORE) -CFLAGS '$(CF) -DNDEBUG $(MULTICORE)'
 	
 gen-md:
-	verilator $(VF) -cc Vortex.v $(MULTICORE) -CFLAGS '$(CF) -g -O0 $(DBG) $(MULTICORE)' --trace $(DBG)
+	verilator $(VF) $(MULTICORE) -CFLAGS '$(CF) -g -O0 $(DBG) $(MULTICORE)' --trace $(DBG)

 gen-mt:
-	verilator $(VF) -DNDEBUG -cc Vortex.v $(MULTICORE) -CFLAGS '$(CF) -DNDEBUG -O2 $(MULTICORE)' --threads $(THREADS)
+	verilator $(VF) -DNDEBUG $(MULTICORE) -CFLAGS '$(CF) -DNDEBUG -O2 $(MULTICORE)' --threads $(THREADS)

 build-s: gen-s
 	(cd obj_dir && make -j -f VVortex.mk)
--- a/hw/simulate/simulator.cpp
+++ b/hw/simulate/simulator.cpp
@@ -24,7 +24,8 @@ Simulator::Simulator() {

 #ifdef VCD_OUTPUT
  Verilated::traceEverOn(true);
-  trace_ = new VerilatedVcdC;
+  trace_ = new VerilatedVcdC();
+  trace_->set_time_unit("1ns");
  vortex_->trace(trace_, 99);
  trace_->open("trace.vcd");
 #endif  
@@ -105,9 +106,8 @@ void Simulator::eval_dram_bus() {
  if (!dram_rsp_active_) {
    if (dequeue_index != -1) {
      vortex_->dram_rsp_valid = 1;
-      memcpy((uint8_t*)vortex_->dram_rsp_data, dram_rsp_vec_[dequeue_index].data, GLOBAL_BLOCK_SIZE);
-      vortex_->dram_rsp_tag = dram_rsp_vec_[dequeue_index].tag;    
-      free(dram_rsp_vec_[dequeue_index].data);
+      memcpy((uint8_t*)vortex_->dram_rsp_data, dram_rsp_vec_[dequeue_index].block.data(), GLOBAL_BLOCK_SIZE);
+      vortex_->dram_rsp_tag = dram_rsp_vec_[dequeue_index].tag;   
      dram_rsp_vec_.erase(dram_rsp_vec_.begin() + dequeue_index);
      dram_rsp_active_ = true;
    } else {
@@ -141,9 +141,8 @@ void Simulator::eval_dram_bus() {
      } else {
        dram_req_t dram_req;
        dram_req.cycles_left = DRAM_LATENCY;     
-        dram_req.data = (uint8_t*)malloc(GLOBAL_BLOCK_SIZE);
        dram_req.tag = vortex_->dram_req_tag;
-        ram_->read(vortex_->dram_req_addr * GLOBAL_BLOCK_SIZE, GLOBAL_BLOCK_SIZE, dram_req.data);
+        ram_->read(vortex_->dram_req_addr * GLOBAL_BLOCK_SIZE, GLOBAL_BLOCK_SIZE, dram_req.block.data());
        dram_rsp_vec_.push_back(dram_req);
      } 
    }    
@@ -211,7 +210,7 @@ void Simulator::wait(uint32_t cycles) {
  }
 }

-bool Simulator::is_busy() {
+bool Simulator::is_busy() const {
  return vortex_->busy || snp_req_active_;
 }

@@ -238,7 +237,7 @@ void Simulator::flush_caches(uint32_t mem_addr, uint32_t size) {
  #endif  
 }

-bool Simulator::run() {
+void Simulator::run() {
 #ifndef NDEBUG
  std::cout << timestamp << ": [sim] run()" << std::endl;
 #endif 
@@ -253,20 +252,15 @@ bool Simulator::run() {
  }

  // wait 5 cycles to flush the pipeline
-  this->wait(5);
+  this->wait(5);  
+}

-  // check riscv-tests PASSED/FAILED status
-#if (NUM_CLUSTERS == 1 && NUM_CORES == 1)
-  int status = (int)vortex_->Vortex->genblk1__DOT__cluster->genblk1__BRA__0__KET____DOT__core->pipeline->commit->writeback->last_data_wb & 0xf;
-#else
-#if (NUM_CLUSTERS == 1)
-  int status = (int)vortex_->Vortex->genblk1__DOT__cluster->genblk1__BRA__0__KET____DOT__core->pipeline->commit->writeback->last_data_wb & 0xf;
-#else
-  int status = (int)vortex_->Vortex->genblk2__DOT__genblk1__BRA__0__KET____DOT__cluster->genblk1__BRA__0__KET____DOT__core->pipeline->commit->writeback->last_data_wb & 0xf;
-#endif
-#endif
-
-  return (status == 1);
+int Simulator::get_last_wb_value(int reg) const {
+  #if (NUM_CLUSTERS != 1)
+    return (int)vortex_->Vortex->genblk2__DOT__genblk1__BRA__0__KET____DOT__cluster->genblk1__BRA__0__KET____DOT__core->pipeline->commit->writeback->last_wb_value[reg];    
+  #else
+    return (int)vortex_->Vortex->genblk1__DOT__cluster->genblk1__BRA__0__KET____DOT__core->pipeline->commit->writeback->last_wb_value[reg];
+  #endif
 }

 void Simulator::load_bin(const char* program_file) {
--- a/hw/simulate/simulator.h
+++ b/hw/simulate/simulator.h
@@ -15,13 +15,13 @@
 #include <vector>

 #define ENABLE_DRAM_STALLS
-#define DRAM_LATENCY 100
+#define DRAM_LATENCY 4
 #define DRAM_RQ_SIZE 16
 #define DRAM_STALLS_MODULO 16

 typedef struct {
  int cycles_left;  
-  uint8_t *data;
+  std::array<uint8_t, GLOBAL_BLOCK_SIZE> block;
  unsigned tag;
 } dram_req_t;

@@ -34,7 +34,7 @@ public:
  void load_bin(const char* program_file);
  void load_ihex(const char* program_file);
  
-  bool is_busy();  
+  bool is_busy() const;  

  void reset();
  void step();
@@ -43,7 +43,8 @@ public:

  void attach_ram(RAM* ram);

-  bool run();  
+  void run();  
+  int get_last_wb_value(int reg) const;  
  void print_stats(std::ostream& out);

 private:  
--- a/hw/simulate/testbench.cpp
+++ b/hw/simulate/testbench.cpp
@@ -3,100 +3,162 @@
 #include <fstream>
 #include <iomanip>

-int main(int argc, char *argv[])
-{
-	if(argc == 1) {
-		bool passed = true;
+int main(int argc, char **argv) {
+	if (argc == 1) {
+#define ALL_TESTS
+#ifdef ALL_TESTS
+	bool passed = true;

-  		std::string tests[] = {
-	 		"../../../benchmarks/riscv_tests/rv32ui-p-add.hex",
-	 		"../../../benchmarks/riscv_tests/rv32ui-p-addi.hex",
-	 		"../../../benchmarks/riscv_tests/rv32ui-p-and.hex",
-	 		"../../../benchmarks/riscv_tests/rv32ui-p-andi.hex",
-	 		"../../../benchmarks/riscv_tests/rv32ui-p-auipc.hex",
-	 		"../../../benchmarks/riscv_tests/rv32ui-p-beq.hex",
-	 		"../../../benchmarks/riscv_tests/rv32ui-p-bge.hex",
-	 		"../../../benchmarks/riscv_tests/rv32ui-p-bgeu.hex",
-	 		"../../../benchmarks/riscv_tests/rv32ui-p-blt.hex",
-	 		"../../../benchmarks/riscv_tests/rv32ui-p-bltu.hex",
-	 		"../../../benchmarks/riscv_tests/rv32ui-p-bne.hex",
-	 		"../../../benchmarks/riscv_tests/rv32ui-p-jal.hex",
-	 		"../../../benchmarks/riscv_tests/rv32ui-p-jalr.hex",		
-	 		"../../../benchmarks/riscv_tests/rv32ui-p-lb.hex",
-	 		"../../../benchmarks/riscv_tests/rv32ui-p-lbu.hex",
-	 		"../../../benchmarks/riscv_tests/rv32ui-p-lh.hex",
-	 		"../../../benchmarks/riscv_tests/rv32ui-p-lhu.hex",
-	 		"../../../benchmarks/riscv_tests/rv32ui-p-lui.hex",
-	 		"../../../benchmarks/riscv_tests/rv32ui-p-lw.hex",
-	 		"../../../benchmarks/riscv_tests/rv32ui-p-or.hex",
-	 		"../../../benchmarks/riscv_tests/rv32ui-p-ori.hex",
-	 		"../../../benchmarks/riscv_tests/rv32ui-p-sb.hex",
-	 		"../../../benchmarks/riscv_tests/rv32ui-p-sh.hex",
-	 		"../../../benchmarks/riscv_tests/rv32ui-p-simple.hex",
-	 		"../../../benchmarks/riscv_tests/rv32ui-p-sll.hex",
-	 		"../../../benchmarks/riscv_tests/rv32ui-p-slli.hex",
-	 		"../../../benchmarks/riscv_tests/rv32ui-p-slt.hex",
-	 		"../../../benchmarks/riscv_tests/rv32ui-p-slti.hex",
-	 		"../../../benchmarks/riscv_tests/rv32ui-p-sltiu.hex",
-	 		"../../../benchmarks/riscv_tests/rv32ui-p-sltu.hex",
-	 		"../../../benchmarks/riscv_tests/rv32ui-p-sra.hex",
-	 		"../../../benchmarks/riscv_tests/rv32ui-p-srai.hex",
-	 		"../../../benchmarks/riscv_tests/rv32ui-p-srl.hex",
-	 		"../../../benchmarks/riscv_tests/rv32ui-p-srli.hex",
-	 		"../../../benchmarks/riscv_tests/rv32ui-p-sub.hex",
-	 		"../../../benchmarks/riscv_tests/rv32ui-p-sw.hex",
-	 		"../../../benchmarks/riscv_tests/rv32ui-p-xor.hex",
-	 		"../../../benchmarks/riscv_tests/rv32ui-p-xori.hex",
-	 		"../../../benchmarks/riscv_tests/rv32um-p-div.hex",
-	 		"../../../benchmarks/riscv_tests/rv32um-p-divu.hex",
-	 		"../../../benchmarks/riscv_tests/rv32um-p-mul.hex",
-	 		"../../../benchmarks/riscv_tests/rv32um-p-mulh.hex",
-	 		"../../../benchmarks/riscv_tests/rv32um-p-mulhsu.hex",
-	 		"../../../benchmarks/riscv_tests/rv32um-p-mulhu.hex",
-	 		"../../../benchmarks/riscv_tests/rv32um-p-rem.hex",
-	 		"../../../benchmarks/riscv_tests/rv32um-p-remu.hex"
-	 	};
+  std::string tests[] = {
+	  "../../../benchmarks/riscv_tests/isa/rv32ui-p-add.hex",
+	 	"../../../benchmarks/riscv_tests/isa/rv32ui-p-addi.hex",
+	 	"../../../benchmarks/riscv_tests/isa/rv32ui-p-and.hex",
+	 	"../../../benchmarks/riscv_tests/isa/rv32ui-p-andi.hex",
+	 	"../../../benchmarks/riscv_tests/isa/rv32ui-p-auipc.hex",
+	 	"../../../benchmarks/riscv_tests/isa/rv32ui-p-beq.hex",
+	 	"../../../benchmarks/riscv_tests/isa/rv32ui-p-bge.hex",
+	 	"../../../benchmarks/riscv_tests/isa/rv32ui-p-bgeu.hex",
+	 	"../../../benchmarks/riscv_tests/isa/rv32ui-p-blt.hex",
+	 	"../../../benchmarks/riscv_tests/isa/rv32ui-p-bltu.hex",
+	 	"../../../benchmarks/riscv_tests/isa/rv32ui-p-bne.hex",
+	 	"../../../benchmarks/riscv_tests/isa/rv32ui-p-jal.hex",
+	 	"../../../benchmarks/riscv_tests/isa/rv32ui-p-jalr.hex",
+	 	"../../../benchmarks/riscv_tests/isa/rv32ui-p-lb.hex",
+	 	"../../../benchmarks/riscv_tests/isa/rv32ui-p-lbu.hex",
+	 	"../../../benchmarks/riscv_tests/isa/rv32ui-p-lh.hex",
+	 	"../../../benchmarks/riscv_tests/isa/rv32ui-p-lhu.hex",
+	 	"../../../benchmarks/riscv_tests/isa/rv32ui-p-lui.hex",
+	 	"../../../benchmarks/riscv_tests/isa/rv32ui-p-lw.hex",
+	 	"../../../benchmarks/riscv_tests/isa/rv32ui-p-or.hex",
+	 	"../../../benchmarks/riscv_tests/isa/rv32ui-p-ori.hex",
+	 	"../../../benchmarks/riscv_tests/isa/rv32ui-p-sb.hex",
+	 	"../../../benchmarks/riscv_tests/isa/rv32ui-p-sh.hex",
+	 	"../../../benchmarks/riscv_tests/isa/rv32ui-p-simple.hex",
+	 	"../../../benchmarks/riscv_tests/isa/rv32ui-p-sll.hex",
+	 	"../../../benchmarks/riscv_tests/isa/rv32ui-p-slli.hex",
+	 	"../../../benchmarks/riscv_tests/isa/rv32ui-p-slt.hex",
+	 	"../../../benchmarks/riscv_tests/isa/rv32ui-p-slti.hex",
+	 	"../../../benchmarks/riscv_tests/isa/rv32ui-p-sltiu.hex",
+	 	"../../../benchmarks/riscv_tests/isa/rv32ui-p-sltu.hex",
+	 	"../../../benchmarks/riscv_tests/isa/rv32ui-p-sra.hex",
+	 	"../../../benchmarks/riscv_tests/isa/rv32ui-p-srai.hex",
+	 	"../../../benchmarks/riscv_tests/isa/rv32ui-p-srl.hex",
+	 	"../../../benchmarks/riscv_tests/isa/rv32ui-p-srli.hex",
+	 	"../../../benchmarks/riscv_tests/isa/rv32ui-p-sub.hex",
+	 	"../../../benchmarks/riscv_tests/isa/rv32ui-p-sw.hex",
+	 	"../../../benchmarks/riscv_tests/isa/rv32ui-p-xor.hex",
+	 	"../../../benchmarks/riscv_tests/isa/rv32ui-p-xori.hex",
+#ifdef EXT_M_ENABLE
+	 	"../../../benchmarks/riscv_tests/isa/rv32um-p-div.hex",
+	 	"../../../benchmarks/riscv_tests/isa/rv32um-p-divu.hex",
+	 	"../../../benchmarks/riscv_tests/isa/rv32um-p-mul.hex",
+	 	"../../../benchmarks/riscv_tests/isa/rv32um-p-mulh.hex",
+	 	"../../../benchmarks/riscv_tests/isa/rv32um-p-mulhsu.hex",
+	 	"../../../benchmarks/riscv_tests/isa/rv32um-p-mulhu.hex",
+	 	"../../../benchmarks/riscv_tests/isa/rv32um-p-rem.hex",
+	 	"../../../benchmarks/riscv_tests/isa/rv32um-p-remu.hex",
+#endif
+	 };

-		for (std::string test : tests) {
-			std::cerr << DEFAULT << "\n---------------------------------------\n";
+	 std::string tests_fp[] = {
+#ifdef EXT_F_ENABLE
+    "../../../benchmarks/riscv_tests/isa/rv32uf-p-fadd.hex",
+		"../../../benchmarks/riscv_tests/isa/rv32uf-p-fdiv.hex",
+		"../../../benchmarks/riscv_tests/isa/rv32uf-p-fmadd.hex",		
+		"../../../benchmarks/riscv_tests/isa/rv32uf-p-fmin.hex",
+		"../../../benchmarks/riscv_tests/isa/rv32uf-p-fcmp.hex",		
+		"../../../benchmarks/riscv_tests/isa/rv32uf-p-ldst.hex",	 
+		"../../../benchmarks/riscv_tests/isa/rv32uf-p-fcvt.hex",
+		"../../../benchmarks/riscv_tests/isa/rv32uf-p-fcvt_w.hex",
+		"../../../benchmarks/riscv_tests/isa/rv32uf-p-fclass.hex",		
+		"../../../benchmarks/riscv_tests/isa/rv32uf-p-move.hex",	
+		"../../../benchmarks/riscv_tests/isa/rv32uf-p-recoding.hex",
+#endif
+	 };

-			std::cerr << test << std::endl;
+	for (std::string test : tests) {
+		std::cerr << DEFAULT << "\n---------------------------------------\n";

-			RAM ram;
-			Simulator simulator;
-			simulator.attach_ram(&ram);
-			simulator.load_ihex(test.c_str());
-			bool curr = simulator.run();
+		std::cerr << test << std::endl;

-			if (curr) std::cerr << GREEN << "Test Passed: " << test << std::endl;
-			if (!curr) std::cerr << RED   << "Test Failed: " << test << std::endl;
-			std::cerr << DEFAULT;
-			passed = passed && curr;
-		}
+		RAM ram;
+		Simulator simulator;
+		simulator.attach_ram(&ram);
+		simulator.load_ihex(test.c_str());
+		simulator.run();

-		std::cerr << DEFAULT << "\n***************************************\n";
+		bool status = (1 == simulator.get_last_wb_value(3));

-		if (passed) std::cerr << DEFAULT << "PASSED ALL TESTS\n";
-		if (!passed) std::cerr << DEFAULT << "Failed one or more tests\n";
-
-		return !passed;
+		if (status) std::cerr << GREEN << "Test Passed: " << test << std::endl;
+		if (!status) std::cerr << RED   << "Test Failed: " << test << std::endl;
+		std::cerr << DEFAULT;
+		passed = passed && status;
+		if (!passed)
+			break;
 	}

-	else {
-		char* test = argv[2];
+	for (std::string test : tests_fp) {
+		std::cerr << DEFAULT << "\n---------------------------------------\n";
+
+		std::cerr << test << std::endl;
+
+		RAM ram;
+		Simulator simulator;
+		simulator.attach_ram(&ram);
+		simulator.load_ihex(test.c_str());
+		simulator.run();
+
+		bool status = (1 == simulator.get_last_wb_value(3));
+
+		if (status) std::cerr << GREEN << "Test Passed: " << test << std::endl;
+		if (!status) std::cerr << RED   << "Test Failed: " << test << std::endl;
+		std::cerr << DEFAULT;
+		passed = passed && status;
+		if (!passed)
+			break;
+	}
+
+	std::cerr << DEFAULT << "\n***************************************\n";
+
+	if (passed) std::cerr << DEFAULT << "PASSED ALL TESTS\n";
+	if (!passed) std::cerr << DEFAULT << "Failed one or more tests\n";
+
+	return !passed;
+
+#else
+
+	char test[] = "../../../runtime/tests/simple/vx_simple.hex";
+
+  std::cerr << test << std::endl;
+
+  RAM ram;
+	Simulator simulator;
+	simulator.attach_ram(&ram);
+	simulator.load_ihex(test);
+  simulator.run();
+
+	bool status = (1 == simulator.get_last_wb_value(3));
+
+	if (status) std::cerr << GREEN << "Test Passed: " << test << std::endl;
+	if (!status) std::cerr << RED   << "Test Failed: " << test << std::endl;
+
+  return !status;
+
+#endif
+
+}	else {
+
+	char* test = argv[2];
 	
-  		std::cerr << test << std::endl;
+	std::cerr << test << std::endl;

-  		RAM ram;
-			Simulator simulator;
-			simulator.attach_ram(&ram);
-			simulator.load_ihex(test);
-			bool curr = simulator.run();
-
-			if (curr) std::cerr << GREEN << "Test Passed: " << test << std::endl;
-			if (!curr) std::cerr << RED   << "Test Failed: " << test << std::endl;
-
-		return !curr;
-	}
+	RAM ram;
+	Simulator simulator;
+	simulator.attach_ram(&ram);
+	simulator.load_ihex(test);
+	simulator.run();

+	return 0;
 }
+
+}
--- a/hw/simulate/verilator.vlt
+++ b/hw/simulate/verilator.vlt
@@ -0,0 +1,9 @@
+`verilator_config
+
+lint_off -rule BLKANDNBLK -file "../rtl/fp_cores/fpnew/*"
+lint_off -rule UNOPTFLAT -file "../rtl/fp_cores/fpnew/*"
+lint_off -rule WIDTH -file "../rtl/fp_cores/fpnew/*"
+lint_off -rule UNUSED -file "../rtl/fp_cores/fpnew/*"
+lint_off -rule LITENDIAN -file "../rtl/fp_cores/fpnew/*"
+lint_off -rule IMPORTSTAR -file "../rtl/fp_cores/fpnew/*"
+lint_off -rule PINCONNECTEMPTY -file "../rtl/fp_cores/fpnew/*"