merged fpu_port branch
This commit is contained in:
Blaise Tine
87
hw/rtl/fp_cores/VX_fp_fpga.v
Normal file
87
hw/rtl/fp_cores/VX_fp_fpga.v
Normal file
@@ -0,0 +1,87 @@
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`include "VX_define.vh"
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module VX_fp_fpga (
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input wire clk,
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input wire reset,
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output wire in_ready,
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input wire in_valid,
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input wire [`ISTAG_BITS-1:0] in_tag,
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input wire [`FPU_BITS-1:0] op,
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input wire [`FRM_BITS-1:0] frm,
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input wire [`NUM_THREADS-1:0][31:0] dataa,
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input wire [`NUM_THREADS-1:0][31:0] datab,
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input wire [`NUM_THREADS-1:0][31:0] datac,
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output wire [`NUM_THREADS-1:0][31:0] result,
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output wire has_fflags,
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output wire [`NUM_THREADS-1:0][`FFG_BITS-1:0] fflags,
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output wire [`ISTAG_BITS-1:0] out_tag,
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input wire out_ready,
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output wire out_valid
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);
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wire fpnew_in_ready;
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wire [`NUM_THREADS-1:0][31:0] fpnew_result;
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wire fpnew_has_fflags;
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wire [`NUM_THREADS-1:0][`FFG_BITS-1:0] fpnew_fflags;
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wire [`ISTAG_BITS-1:0] fpnew_out_tag;
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wire fpnew_out_ready;
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wire fpnew_out_valid;
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wire [`NUM_THREADS-1:0][31:0] add_result;
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wire add_out_ready;
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VX_fpnew #(
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.FMULADD (0),
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.FDIVSQRT (1),
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.FNONCOMP (1),
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.FCONV (1)
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) fp_core (
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.clk (clk),
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.reset (reset),
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.in_valid (in_valid),
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.in_ready (fpnew_in_ready),
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.in_tag (in_tag),
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.op (op),
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.frm (frm),
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.dataa (dataa),
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.datab (datab),
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.datac (datac),
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.result (fpnew_result),
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.has_fflags (fpnew_has_fflags),
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.fflags (fpnew_fflags),
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.out_tag (fpnew_out_tag),
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.out_ready (fpnew_out_ready),
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.out_valid (fpnew_out_valid)
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);
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acl_fp_add fp_add (
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.clock (clk),
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.dataa (dataa),
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.datab (datab),
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.enable (add_out_ready),
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.result (add_result)
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);
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assign in_reqady = fpnew_in_ready;
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assign has_fflags = fpnew_has_fflags;
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assign fflags = fpnew_fflags;
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assign out_tag = fpnew_out_tag;
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assign fpnew_out_ready = out_ready;
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assign result = fpnew_out_valid ? fpnew_result : add_result;
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assign out_valid = fpnew_out_valid;
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endmodule
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217
hw/rtl/fp_cores/VX_fpnew.v
Normal file
217
hw/rtl/fp_cores/VX_fpnew.v
Normal file
@@ -0,0 +1,217 @@
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`include "VX_define.vh"
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`include "fpnew_pkg.sv"
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`include "defs_div_sqrt_mvp.sv"
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module VX_fpnew #(
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parameter FMULADD = 1,
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parameter FDIVSQRT = 1,
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parameter FNONCOMP = 1,
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parameter FCONV = 1
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) (
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input wire clk,
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input wire reset,
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output wire in_ready,
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input wire in_valid,
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input wire [`ISTAG_BITS-1:0] in_tag,
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input wire [`FPU_BITS-1:0] op,
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input wire [`FRM_BITS-1:0] frm,
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input wire [`NUM_THREADS-1:0][31:0] dataa,
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input wire [`NUM_THREADS-1:0][31:0] datab,
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input wire [`NUM_THREADS-1:0][31:0] datac,
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output wire [`NUM_THREADS-1:0][31:0] result,
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output wire has_fflags,
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output wire [`NUM_THREADS-1:0][`FFG_BITS-1:0] fflags,
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output wire [`ISTAG_BITS-1:0] out_tag,
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input wire out_ready,
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output wire out_valid
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);
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localparam UNIT_FMULADD = FMULADD ? fpnew_pkg::PARALLEL : fpnew_pkg::DISABLED;
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localparam UNIT_FDIVSQRT = FDIVSQRT ? fpnew_pkg::MERGED : fpnew_pkg::DISABLED;
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localparam UNIT_FNONCOMP = FNONCOMP ? fpnew_pkg::PARALLEL : fpnew_pkg::DISABLED;
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localparam UNIT_FCONV = FCONV ? fpnew_pkg::MERGED : fpnew_pkg::DISABLED;
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localparam FOP_BITS = fpnew_pkg::OP_BITS;
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localparam FMTF_BITS = $clog2(fpnew_pkg::NUM_FP_FORMATS);
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localparam FMTI_BITS = $clog2(fpnew_pkg::NUM_INT_FORMATS);
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localparam FPU_DPATHW = 32'd32;
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localparam fpnew_pkg::fpu_features_t FPU_FEATURES = '{
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Width: FPU_DPATHW,
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EnableVectors: 1'b0,
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EnableNanBox: 1'b1,
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FpFmtMask: 5'b10000,
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IntFmtMask: 4'b0010
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};
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localparam fpnew_pkg::fpu_implementation_t FPU_IMPLEMENTATION = '{
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PipeRegs:'{'{`LATENCY_FMULADD, 0, 0, 0, 0}, // ADDMUL
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'{default: `LATENCY_FDIVSQRT}, // DIVSQRT
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'{default: `LATENCY_FNONCOMP}, // NONCOMP
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'{default: `LATENCY_FCONV}}, // CONV
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UnitTypes:'{'{default: UNIT_FMULADD}, // ADDMUL
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'{default: UNIT_FDIVSQRT}, // DIVSQRT
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'{default: UNIT_FNONCOMP}, // NONCOMP
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'{default: UNIT_FCONV}}, // CONV
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PipeConfig: fpnew_pkg::DISTRIBUTED
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};
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wire fpu_in_ready, fpu_in_valid;
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wire fpu_out_ready, fpu_out_valid;
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reg [`LOG2UP(`FPURQ_SIZE)-1:0] fpu_in_tag, fpu_out_tag;
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reg [2:0][`NUM_THREADS-1:0][31:0] fpu_operands;
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wire [FMTF_BITS-1:0] fpu_src_fmt = fpnew_pkg::FP32;
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wire [FMTF_BITS-1:0] fpu_dst_fmt = fpnew_pkg::FP32;
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wire [FMTI_BITS-1:0] fpu_int_fmt = fpnew_pkg::INT32;
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wire [`NUM_THREADS-1:0][31:0] fpu_result;
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fpnew_pkg::status_t fpu_status [0:`NUM_THREADS-1];
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wire is_class_op_i, is_class_op_o;
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assign is_class_op_i = (op == `FPU_CLASS);
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reg [FOP_BITS-1:0] fpu_op;
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reg [`FRM_BITS-1:0] fpu_rnd;
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reg fpu_op_mod;
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reg fflags_en, fflags_en_o;
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always @(*) begin
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fpu_op = fpnew_pkg::SGNJ;
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fpu_rnd = frm;
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fpu_op_mod = 0;
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fflags_en = 1;
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fpu_operands[0] = dataa;
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fpu_operands[1] = datab;
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fpu_operands[2] = datac;
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case (op)
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`FPU_ADD: begin
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fpu_op = fpnew_pkg::ADD;
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fpu_operands[1] = dataa;
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fpu_operands[2] = datab;
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end
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`FPU_SUB: begin
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fpu_op = fpnew_pkg::ADD;
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fpu_operands[1] = dataa;
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fpu_operands[2] = datab;
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fpu_op_mod = 1;
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end
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`FPU_MUL: begin fpu_op = fpnew_pkg::MUL; end
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`FPU_DIV: begin fpu_op = fpnew_pkg::DIV; end
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`FPU_SQRT: begin fpu_op = fpnew_pkg::SQRT; end
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`FPU_MADD: begin fpu_op = fpnew_pkg::FMADD; end
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`FPU_MSUB: begin fpu_op = fpnew_pkg::FMADD; fpu_op_mod = 1; end
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`FPU_NMSUB: begin fpu_op = fpnew_pkg::FNMSUB; end
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`FPU_NMADD: begin fpu_op = fpnew_pkg::FNMSUB; fpu_op_mod = 1; end
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`FPU_SGNJ: begin fpu_op = fpnew_pkg::SGNJ; fpu_rnd = `FRM_RNE; fflags_en = 0; end
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`FPU_SGNJN: begin fpu_op = fpnew_pkg::SGNJ; fpu_rnd = `FRM_RTZ; fflags_en = 0; end
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`FPU_SGNJX: begin fpu_op = fpnew_pkg::SGNJ; fpu_rnd = `FRM_RDN; fflags_en = 0; end
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`FPU_MIN: begin fpu_op = fpnew_pkg::MINMAX; fpu_rnd = `FRM_RNE; end
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`FPU_MAX: begin fpu_op = fpnew_pkg::MINMAX; fpu_rnd = `FRM_RTZ; end
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`FPU_CVTWS: begin fpu_op = fpnew_pkg::F2I; end
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`FPU_CVTWUS:begin fpu_op = fpnew_pkg::F2I; fpu_op_mod = 1; end
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`FPU_CVTSW: begin fpu_op = fpnew_pkg::I2F; end
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`FPU_CVTSWU:begin fpu_op = fpnew_pkg::I2F; fpu_op_mod = 1; end
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`FPU_MVXW: begin fpu_op = fpnew_pkg::SGNJ; fpu_rnd = `FRM_RUP; fflags_en = 0; end
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`FPU_MVWX: begin fpu_op = fpnew_pkg::SGNJ; fpu_rnd = `FRM_RUP; fflags_en = 0; end
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`FPU_CLASS: begin fpu_op = fpnew_pkg::CLASSIFY; fflags_en = 0; end
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`FPU_CMP: begin fpu_op = fpnew_pkg::CMP; end
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default:;
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endcase
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end
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genvar i;
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`DISABLE_TRACING
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for (i = 0; i < `NUM_THREADS; i++) begin
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if (0 == i) begin
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fpnew_top #(
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.Features (FPU_FEATURES),
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.Implementation (FPU_IMPLEMENTATION),
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.TagType (logic[`LOG2UP(`FPURQ_SIZE)+1+1-1:0])
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) fpnew_core (
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.clk_i (clk),
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.rst_ni (1'b1),
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.operands_i ({fpu_operands[2][0], fpu_operands[1][0], fpu_operands[0][0]}),
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.rnd_mode_i (fpnew_pkg::roundmode_e'(fpu_rnd)),
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.op_i (fpnew_pkg::operation_e'(fpu_op)),
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.op_mod_i (fpu_op_mod),
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.src_fmt_i (fpnew_pkg::fp_format_e'(fpu_src_fmt)),
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.dst_fmt_i (fpnew_pkg::fp_format_e'(fpu_dst_fmt)),
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.int_fmt_i (fpnew_pkg::int_format_e'(fpu_int_fmt)),
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.vectorial_op_i (1'b0),
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.tag_i ({fpu_in_tag, fflags_en, is_class_op_i}),
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.in_valid_i (fpu_in_valid),
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.in_ready_o (fpu_in_ready),
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||||
.flush_i (reset),
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||||
.result_o (fpu_result[0]),
|
||||
.status_o (fpu_status[0]),
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.tag_o ({fpu_out_tag, fflags_en_o, is_class_op_o}),
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||||
.out_valid_o (fpu_out_valid),
|
||||
.out_ready_i (fpu_out_ready),
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||||
`UNUSED_PIN (busy_o)
|
||||
);
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||||
end else begin
|
||||
fpnew_top #(
|
||||
.Features (FPU_FEATURES),
|
||||
.Implementation (FPU_IMPLEMENTATION),
|
||||
.TagType (logic)
|
||||
) fpnew_core (
|
||||
.clk_i (clk),
|
||||
.rst_ni (1'b1),
|
||||
.operands_i ({fpu_operands[2][i], fpu_operands[1][i], fpu_operands[0][i]}),
|
||||
.rnd_mode_i (fpnew_pkg::roundmode_e'(fpu_rnd)),
|
||||
.op_i (fpnew_pkg::operation_e'(fpu_op)),
|
||||
.op_mod_i (fpu_op_mod),
|
||||
.src_fmt_i (fpnew_pkg::fp_format_e'(fpu_src_fmt)),
|
||||
.dst_fmt_i (fpnew_pkg::fp_format_e'(fpu_dst_fmt)),
|
||||
.int_fmt_i (fpnew_pkg::int_format_e'(fpu_int_fmt)),
|
||||
.vectorial_op_i (1'b0),
|
||||
.tag_i (1'b0),
|
||||
.in_valid_i (fpu_in_valid),
|
||||
`UNUSED_PIN (in_ready_o),
|
||||
.flush_i (reset),
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||||
.result_o (fpu_result[i]),
|
||||
.status_o (fpu_status[i]),
|
||||
`UNUSED_PIN (tag_o),
|
||||
`UNUSED_PIN (out_valid_o),
|
||||
.out_ready_i (fpu_out_ready),
|
||||
`UNUSED_PIN (busy_o)
|
||||
);
|
||||
end
|
||||
end
|
||||
|
||||
`ENABLE_TRACING
|
||||
|
||||
assign fpu_in_valid = in_valid;
|
||||
assign in_ready = fpu_in_ready;
|
||||
|
||||
assign fpu_in_tag = in_tag;
|
||||
assign out_tag = fpu_out_tag;
|
||||
|
||||
assign result = fpu_result;
|
||||
|
||||
assign has_fflags = fflags_en_o;
|
||||
|
||||
for (i = 0; i < `NUM_THREADS; i++) begin
|
||||
assign fflags[i][0] = fpu_status[i].NX;
|
||||
assign fflags[i][1] = fpu_status[i].UF;
|
||||
assign fflags[i][2] = fpu_status[i].OF;
|
||||
assign fflags[i][3] = fpu_status[i].DZ;
|
||||
assign fflags[i][4] = fpu_status[i].NV;
|
||||
end
|
||||
|
||||
assign out_valid = fpu_out_valid;
|
||||
assign fpu_out_ready = out_ready;
|
||||
|
||||
endmodule
|
||||
67
hw/rtl/fp_cores/altera/acl_fp_add.v
Normal file
67
hw/rtl/fp_cores/altera/acl_fp_add.v
Normal file
@@ -0,0 +1,67 @@
|
||||
// (C) 1992-2016 Intel Corporation.
|
||||
// Intel, the Intel logo, Intel, MegaCore, NIOS II, Quartus and TalkBack words
|
||||
// and logos are trademarks of Intel Corporation or its subsidiaries in the U.S.
|
||||
// and/or other countries. Other marks and brands may be claimed as the property
|
||||
// of others. See Trademarks on intel.com for full list of Intel trademarks or
|
||||
// the Trademarks & Brands Names Database (if Intel) or See www.Intel.com/legal (if Altera)
|
||||
// Your use of Intel Corporation's design tools, logic functions and other
|
||||
// software and tools, and its AMPP partner logic functions, and any output
|
||||
// files any of the foregoing (including device programming or simulation
|
||||
// files), and any associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Altera Program License Subscription
|
||||
// Agreement, Intel MegaCore Function License Agreement, or other applicable
|
||||
// license agreement, including, without limitation, that your use is for the
|
||||
// sole purpose of programming logic devices manufactured by Intel and sold by
|
||||
// Intel or its authorized distributors. Please refer to the applicable
|
||||
// agreement for further details.
|
||||
|
||||
module acl_fp_add(dataa, datab, clock, enable, result);
|
||||
|
||||
input [31:0] dataa;
|
||||
input [31:0] datab;
|
||||
input clock, enable;
|
||||
|
||||
output [31:0] result;
|
||||
|
||||
// FP MAC wysiwyg
|
||||
twentynm_fp_mac mac_fp_wys (
|
||||
// inputs
|
||||
.accumulate(),
|
||||
.chainin_overflow(),
|
||||
.chainin_invalid(),
|
||||
.chainin_underflow(),
|
||||
.chainin_inexact(),
|
||||
.ax(dataa),
|
||||
.ay(datab),
|
||||
.az(),
|
||||
.clk({2'b00,clock}),
|
||||
.ena({2'b11,enable}),
|
||||
.aclr(2'b00),
|
||||
.chainin(),
|
||||
// outputs
|
||||
.overflow(),
|
||||
.invalid(),
|
||||
.underflow(),
|
||||
.inexact(),
|
||||
.chainout_overflow(),
|
||||
.chainout_invalid(),
|
||||
.chainout_underflow(),
|
||||
.chainout_inexact(),
|
||||
.resulta(result),
|
||||
.chainout()
|
||||
);
|
||||
defparam mac_fp_wys.operation_mode = "sp_add";
|
||||
defparam mac_fp_wys.use_chainin = "false";
|
||||
defparam mac_fp_wys.adder_subtract = "false";
|
||||
defparam mac_fp_wys.ax_clock = "0";
|
||||
defparam mac_fp_wys.ay_clock = "0";
|
||||
defparam mac_fp_wys.az_clock = "none";
|
||||
defparam mac_fp_wys.output_clock = "0";
|
||||
defparam mac_fp_wys.accumulate_clock = "none";
|
||||
defparam mac_fp_wys.ax_chainin_pl_clock = "none";
|
||||
defparam mac_fp_wys.accum_pipeline_clock = "none";
|
||||
defparam mac_fp_wys.mult_pipeline_clock = "none";
|
||||
defparam mac_fp_wys.adder_input_clock = "0";
|
||||
defparam mac_fp_wys.accum_adder_clock = "none";
|
||||
|
||||
endmodule
|
||||
63
hw/rtl/fp_cores/altera/acl_fp_msub.v
Normal file
63
hw/rtl/fp_cores/altera/acl_fp_msub.v
Normal file
@@ -0,0 +1,63 @@
|
||||
// (C) 1992-2014 Altera Corporation. All rights reserved.
|
||||
// Your use of Altera Corporation's design tools, logic functions and other
|
||||
// software and tools, and its AMPP partner logic functions, and any output
|
||||
// files any of the foregoing (including device programming or simulation
|
||||
// files), and any associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Altera Program License Subscription
|
||||
// Agreement, Altera MegaCore Function License Agreement, or other applicable
|
||||
// license agreement, including, without limitation, that your use is for the
|
||||
// sole purpose of programming logic devices manufactured by Altera and sold by
|
||||
// Altera or its authorized distributors. Please refer to the applicable
|
||||
// agreement for further details.
|
||||
|
||||
module acl_fp_multadd(dataa, datab, datac, clock, enable, result);
|
||||
// a*b + c
|
||||
input [31:0] dataa;
|
||||
input [31:0] datab;
|
||||
input [31:0] datac;
|
||||
input clock;
|
||||
input enable;
|
||||
output [31:0] result;
|
||||
|
||||
// FP MAC wysiwyg
|
||||
twentynm_fp_mac mac_fp_wys (
|
||||
// inputs
|
||||
.accumulate(),
|
||||
.chainin_overflow(),
|
||||
.chainin_invalid(),
|
||||
.chainin_underflow(),
|
||||
.chainin_inexact(),
|
||||
.ax(datac),
|
||||
.ay(datab),
|
||||
.az(dataa),
|
||||
.clk({2'b00,clock}),
|
||||
.ena({2'b11,enable}),
|
||||
.aclr(2'b00),
|
||||
.chainin(),
|
||||
// outputs
|
||||
.overflow(),
|
||||
.invalid(),
|
||||
.underflow(),
|
||||
.inexact(),
|
||||
.chainout_overflow(),
|
||||
.chainout_invalid(),
|
||||
.chainout_underflow(),
|
||||
.chainout_inexact(),
|
||||
.resulta(result),
|
||||
.chainout()
|
||||
);
|
||||
defparam mac_fp_wys.operation_mode = "sp_mult_add";
|
||||
defparam mac_fp_wys.use_chainin = "false";
|
||||
defparam mac_fp_wys.adder_subtract = "true";
|
||||
defparam mac_fp_wys.ax_clock = "0";
|
||||
defparam mac_fp_wys.ay_clock = "0";
|
||||
defparam mac_fp_wys.az_clock = "0";
|
||||
defparam mac_fp_wys.output_clock = "0";
|
||||
defparam mac_fp_wys.accumulate_clock = "none";
|
||||
defparam mac_fp_wys.ax_chainin_pl_clock = "0";
|
||||
defparam mac_fp_wys.accum_pipeline_clock = "none";
|
||||
defparam mac_fp_wys.mult_pipeline_clock = "0";
|
||||
defparam mac_fp_wys.adder_input_clock = "0";
|
||||
defparam mac_fp_wys.accum_adder_clock = "none";
|
||||
|
||||
endmodule
|
||||
67
hw/rtl/fp_cores/altera/acl_fp_mul.v
Normal file
67
hw/rtl/fp_cores/altera/acl_fp_mul.v
Normal file
@@ -0,0 +1,67 @@
|
||||
// (C) 1992-2016 Intel Corporation.
|
||||
// Intel, the Intel logo, Intel, MegaCore, NIOS II, Quartus and TalkBack words
|
||||
// and logos are trademarks of Intel Corporation or its subsidiaries in the U.S.
|
||||
// and/or other countries. Other marks and brands may be claimed as the property
|
||||
// of others. See Trademarks on intel.com for full list of Intel trademarks or
|
||||
// the Trademarks & Brands Names Database (if Intel) or See www.Intel.com/legal (if Altera)
|
||||
// Your use of Intel Corporation's design tools, logic functions and other
|
||||
// software and tools, and its AMPP partner logic functions, and any output
|
||||
// files any of the foregoing (including device programming or simulation
|
||||
// files), and any associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Altera Program License Subscription
|
||||
// Agreement, Intel MegaCore Function License Agreement, or other applicable
|
||||
// license agreement, including, without limitation, that your use is for the
|
||||
// sole purpose of programming logic devices manufactured by Intel and sold by
|
||||
// Intel or its authorized distributors. Please refer to the applicable
|
||||
// agreement for further details.
|
||||
|
||||
module acl_fp_mul(dataa, datab, clock, enable, result);
|
||||
|
||||
input [31:0] dataa;
|
||||
input [31:0] datab;
|
||||
input clock, enable;
|
||||
|
||||
output [31:0] result;
|
||||
|
||||
// FP MAC wysiwyg
|
||||
twentynm_fp_mac mac_fp_wys (
|
||||
// inputs
|
||||
.accumulate(),
|
||||
.chainin_overflow(),
|
||||
.chainin_invalid(),
|
||||
.chainin_underflow(),
|
||||
.chainin_inexact(),
|
||||
.ax(),
|
||||
.ay(datab),
|
||||
.az(dataa),
|
||||
.clk({2'b00,clock}),
|
||||
.ena({2'b11,enable}),
|
||||
.aclr(2'b00),
|
||||
.chainin(),
|
||||
// outputs
|
||||
.overflow(),
|
||||
.invalid(),
|
||||
.underflow(),
|
||||
.inexact(),
|
||||
.chainout_overflow(),
|
||||
.chainout_invalid(),
|
||||
.chainout_underflow(),
|
||||
.chainout_inexact(),
|
||||
.resulta(result),
|
||||
.chainout()
|
||||
);
|
||||
defparam mac_fp_wys.operation_mode = "sp_mult";
|
||||
defparam mac_fp_wys.use_chainin = "false";
|
||||
defparam mac_fp_wys.adder_subtract = "false";
|
||||
defparam mac_fp_wys.ax_clock = "none";
|
||||
defparam mac_fp_wys.ay_clock = "0";
|
||||
defparam mac_fp_wys.az_clock = "0";
|
||||
defparam mac_fp_wys.output_clock = "0";
|
||||
defparam mac_fp_wys.accumulate_clock = "none";
|
||||
defparam mac_fp_wys.ax_chainin_pl_clock = "none";
|
||||
defparam mac_fp_wys.accum_pipeline_clock = "none";
|
||||
defparam mac_fp_wys.mult_pipeline_clock = "0";
|
||||
defparam mac_fp_wys.adder_input_clock = "none";
|
||||
defparam mac_fp_wys.accum_adder_clock = "none";
|
||||
|
||||
endmodule
|
||||
63
hw/rtl/fp_cores/altera/acl_fp_nmadd.v
Normal file
63
hw/rtl/fp_cores/altera/acl_fp_nmadd.v
Normal file
@@ -0,0 +1,63 @@
|
||||
// (C) 1992-2014 Altera Corporation. All rights reserved.
|
||||
// Your use of Altera Corporation's design tools, logic functions and other
|
||||
// software and tools, and its AMPP partner logic functions, and any output
|
||||
// files any of the foregoing (including device programming or simulation
|
||||
// files), and any associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Altera Program License Subscription
|
||||
// Agreement, Altera MegaCore Function License Agreement, or other applicable
|
||||
// license agreement, including, without limitation, that your use is for the
|
||||
// sole purpose of programming logic devices manufactured by Altera and sold by
|
||||
// Altera or its authorized distributors. Please refer to the applicable
|
||||
// agreement for further details.
|
||||
|
||||
module acl_fp_multadd(dataa, datab, datac, clock, enable, result);
|
||||
// a*b + c
|
||||
input [31:0] dataa;
|
||||
input [31:0] datab;
|
||||
input [31:0] datac;
|
||||
input clock;
|
||||
input enable;
|
||||
output [31:0] result;
|
||||
|
||||
// FP MAC wysiwyg
|
||||
twentynm_fp_mac mac_fp_wys (
|
||||
// inputs
|
||||
.accumulate(),
|
||||
.chainin_overflow(),
|
||||
.chainin_invalid(),
|
||||
.chainin_underflow(),
|
||||
.chainin_inexact(),
|
||||
.ax(datac),
|
||||
.ay(datab),
|
||||
.az(dataa),
|
||||
.clk({2'b00,clock}),
|
||||
.ena({2'b11,enable}),
|
||||
.aclr(2'b00),
|
||||
.chainin(),
|
||||
// outputs
|
||||
.overflow(),
|
||||
.invalid(),
|
||||
.underflow(),
|
||||
.inexact(),
|
||||
.chainout_overflow(),
|
||||
.chainout_invalid(),
|
||||
.chainout_underflow(),
|
||||
.chainout_inexact(),
|
||||
.resulta(result),
|
||||
.chainout()
|
||||
);
|
||||
defparam mac_fp_wys.operation_mode = "sp_mult_add";
|
||||
defparam mac_fp_wys.use_chainin = "false";
|
||||
defparam mac_fp_wys.adder_subtract = "false";
|
||||
defparam mac_fp_wys.ax_clock = "0";
|
||||
defparam mac_fp_wys.ay_clock = "0";
|
||||
defparam mac_fp_wys.az_clock = "0";
|
||||
defparam mac_fp_wys.output_clock = "0";
|
||||
defparam mac_fp_wys.accumulate_clock = "none";
|
||||
defparam mac_fp_wys.ax_chainin_pl_clock = "0";
|
||||
defparam mac_fp_wys.accum_pipeline_clock = "none";
|
||||
defparam mac_fp_wys.mult_pipeline_clock = "0";
|
||||
defparam mac_fp_wys.adder_input_clock = "0";
|
||||
defparam mac_fp_wys.accum_adder_clock = "none";
|
||||
|
||||
endmodule
|
||||
67
hw/rtl/fp_cores/altera/acl_fp_sub.v
Normal file
67
hw/rtl/fp_cores/altera/acl_fp_sub.v
Normal file
@@ -0,0 +1,67 @@
|
||||
// (C) 1992-2016 Intel Corporation.
|
||||
// Intel, the Intel logo, Intel, MegaCore, NIOS II, Quartus and TalkBack words
|
||||
// and logos are trademarks of Intel Corporation or its subsidiaries in the U.S.
|
||||
// and/or other countries. Other marks and brands may be claimed as the property
|
||||
// of others. See Trademarks on intel.com for full list of Intel trademarks or
|
||||
// the Trademarks & Brands Names Database (if Intel) or See www.Intel.com/legal (if Altera)
|
||||
// Your use of Intel Corporation's design tools, logic functions and other
|
||||
// software and tools, and its AMPP partner logic functions, and any output
|
||||
// files any of the foregoing (including device programming or simulation
|
||||
// files), and any associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Altera Program License Subscription
|
||||
// Agreement, Intel MegaCore Function License Agreement, or other applicable
|
||||
// license agreement, including, without limitation, that your use is for the
|
||||
// sole purpose of programming logic devices manufactured by Intel and sold by
|
||||
// Intel or its authorized distributors. Please refer to the applicable
|
||||
// agreement for further details.
|
||||
|
||||
module acl_fp_add(dataa, datab, clock, enable, result);
|
||||
|
||||
input [31:0] dataa;
|
||||
input [31:0] datab;
|
||||
input clock, enable;
|
||||
|
||||
output [31:0] result;
|
||||
|
||||
// FP MAC wysiwyg
|
||||
twentynm_fp_mac mac_fp_wys (
|
||||
// inputs
|
||||
.accumulate(),
|
||||
.chainin_overflow(),
|
||||
.chainin_invalid(),
|
||||
.chainin_underflow(),
|
||||
.chainin_inexact(),
|
||||
.ax(dataa),
|
||||
.ay(datab),
|
||||
.az(),
|
||||
.clk({2'b00,clock}),
|
||||
.ena({2'b11,enable}),
|
||||
.aclr(2'b00),
|
||||
.chainin(),
|
||||
// outputs
|
||||
.overflow(),
|
||||
.invalid(),
|
||||
.underflow(),
|
||||
.inexact(),
|
||||
.chainout_overflow(),
|
||||
.chainout_invalid(),
|
||||
.chainout_underflow(),
|
||||
.chainout_inexact(),
|
||||
.resulta(result),
|
||||
.chainout()
|
||||
);
|
||||
defparam mac_fp_wys.operation_mode = "sp_add";
|
||||
defparam mac_fp_wys.use_chainin = "false";
|
||||
defparam mac_fp_wys.adder_subtract = "true";
|
||||
defparam mac_fp_wys.ax_clock = "0";
|
||||
defparam mac_fp_wys.ay_clock = "0";
|
||||
defparam mac_fp_wys.az_clock = "none";
|
||||
defparam mac_fp_wys.output_clock = "0";
|
||||
defparam mac_fp_wys.accumulate_clock = "none";
|
||||
defparam mac_fp_wys.ax_chainin_pl_clock = "none";
|
||||
defparam mac_fp_wys.accum_pipeline_clock = "none";
|
||||
defparam mac_fp_wys.mult_pipeline_clock = "none";
|
||||
defparam mac_fp_wys.adder_input_clock = "0";
|
||||
defparam mac_fp_wys.accum_adder_clock = "none";
|
||||
|
||||
endmodule
|
||||
1
hw/rtl/fp_cores/fpnew
Submodule
1
hw/rtl/fp_cores/fpnew
Submodule
Submodule hw/rtl/fp_cores/fpnew added at 1def7bb630
Reference in New Issue
Block a user