minor update

2021-02-15 09:23:40 -08:00
parent 9eed48435c
commit 31b3e380dc
2 changed files with 3 additions and 6 deletions
--- a/hw/syn/quartus/project.sdc
+++ b/hw/syn/quartus/project.sdc
@@ -1,7 +1,4 @@
 create_clock -name {clk} -period "220 MHz" [get_ports {clk}]

 derive_pll_clocks -create_base_clocks
-derive_clock_uncertainty
-
-
-
+derive_clock_uncertainty