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All cache bugs fixed - Handshaking

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This commit is contained in:
felsabbagh3
2020-03-28 21:43:02 -07:00
parent 5dc9493c61 f7e0d1e491
commit 313a8e3b4b
301 changed files with 527762 additions and 30493 deletions
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4
rtl/VX_cache/VX_bank.v
View File

@@ -558,7 +558,7 @@ module VX_bank
wire[`BANK_LINE_SIZE_RNG][`WORD_SIZE-1:0] dwbq_req_data = readdata_st2;
wire dwbq_empty;
wire possible_fill = valid_st2 && miss_st2;
wire possible_fill = valid_st2 && miss_st2 && !dram_fill_req_queue_full;
wire[31:0] fill_invalidator_addr = addr_st2 & `BASE_ADDR_MASK;
VX_fill_invalidator #(
.CACHE_SIZE_BYTES (CACHE_SIZE_BYTES),
@@ -590,7 +590,7 @@ module VX_bank
);
// Enqueu in dram_fill_req
assign dram_fill_req = valid_st2 && miss_st2 && !invalidate_fill && !dram_fill_req_queue_full;
assign dram_fill_req = possible_fill && !invalidate_fill;
assign dram_because_of_snp = is_snp_st2 && valid_st2 && miss_st2;
assign dram_snp_full = snrq_full && snp_req;
assign dram_fill_req_addr = addr_st2 & `BASE_ADDR_MASK;

96
rtl/VX_cache/VX_fill_invalidator.v
View File

@@ -68,35 +68,21 @@ module VX_fill_invalidator
reg[FILL_INVALIDAOR_SIZE-1:0][31:0] fills_address;
reg success_found;
reg[(`vx_clog2(FILL_INVALIDAOR_SIZE))-1:0] success_index;
integer curr_fill;
reg[FILL_INVALIDAOR_SIZE-1:0] matched_fill;
wire matched;
integer fi;
always @(*) begin
invalidate_fill = 0;
success_found = 0;
success_index = 0;
for (curr_fill = 0; curr_fill < FILL_INVALIDAOR_SIZE; curr_fill=curr_fill+1) begin
if (fill_addr[31:`LINE_SELECT_ADDR_START] == fills_address[curr_fill][31:`LINE_SELECT_ADDR_START]) begin
if (possible_fill && fills_active[curr_fill]) begin
invalidate_fill = 1;
end
if (success_fill) begin
success_found = 1;
success_index = curr_fill;
end
end
for (fi = 0; fi < FILL_INVALIDAOR_SIZE; fi+=1) begin
matched_fill[fi] = fills_active[fi] && (fills_address[fi][31:`LINE_SELECT_ADDR_START] == fill_addr[31:`LINE_SELECT_ADDR_START]);
end
end
assign matched = (|(matched_fill));
wire [(`vx_clog2(FILL_INVALIDAOR_SIZE))-1:0] enqueue_index;
wire [(`vx_clog2(FILL_INVALIDAOR_SIZE))-1:0] enqueue_index;
wire enqueue_found;
VX_generic_priority_encoder #(.N(FILL_INVALIDAOR_SIZE)) VX_sel_bank(
.valids(~fills_active),
.index (enqueue_index),
@@ -104,6 +90,7 @@ module VX_fill_invalidator
);
assign invalidate_fill = possible_fill && matched;
always @(posedge clk) begin
@@ -111,19 +98,74 @@ module VX_fill_invalidator
fills_active <= 0;
fills_address <= 0;
end else begin
if (possible_fill && !invalidate_fill) begin
fills_active[enqueue_index] <= 1;
fills_address[enqueue_index] <= fill_addr;
end
if (success_found) begin
fills_active[success_index] <= 0;
if (possible_fill && !matched && enqueue_found) begin
fills_active [enqueue_index] <= 1;
fills_address[enqueue_index] <= fill_addr;
end else if (success_fill && matched) begin
fills_active <= fills_active & (~matched_fill);
end
end
end
// reg success_found;
// reg[(`vx_clog2(FILL_INVALIDAOR_SIZE))-1:0] success_index;
// integer curr_fill;
// always @(*) begin
// invalidate_fill = 0;
// success_found = 0;
// success_index = 0;
// for (curr_fill = 0; curr_fill < FILL_INVALIDAOR_SIZE; curr_fill=curr_fill+1) begin
// if (fill_addr[31:`LINE_SELECT_ADDR_START] == fills_address[curr_fill][31:`LINE_SELECT_ADDR_START]) begin
// if (possible_fill && fills_active[curr_fill]) begin
// invalidate_fill = 1;
// end
// if (success_fill) begin
// success_found = 1;
// success_index = curr_fill;
// end
// end
// end
// end
// wire [(`vx_clog2(FILL_INVALIDAOR_SIZE))-1:0] enqueue_index;
// wire enqueue_found;
// VX_generic_priority_encoder #(.N(FILL_INVALIDAOR_SIZE)) VX_sel_bank(
// .valids(~fills_active),
// .index (enqueue_index),
// .found (enqueue_found)
// );
// always @(posedge clk) begin
// if (reset) begin
// fills_active <= 0;
// fills_address <= 0;
// end else begin
// if (possible_fill && !invalidate_fill) begin
// fills_active[enqueue_index] <= 1;
// fills_address[enqueue_index] <= fill_addr;
// end
// if (success_found) begin
// fills_active[success_index] <= 0;
// end
// end
// end
end

2
rtl/VX_cache/VX_tag_data_access.v
View File

@@ -249,7 +249,7 @@ module VX_tag_data_access
wire normal_write = (block_offset == g[`WORD_SELECT_SIZE_RNG]) && should_write && !real_writefill;
assign we[g] = (force_write) ? 4'b1111 :
(normal_write && (FUNC_ID == `LLFUNC_ID)) ? 4'b1111 :
(should_write && !real_writefill && (FUNC_ID == `LLFUNC_ID)) ? 4'b1111 :
(normal_write && sw) ? 4'b1111 :
(normal_write && sb) ? sb_mask :
(normal_write && sh) ? sh_mask :