RTL code refactoring

2020-04-19 08:45:46 -04:00
parent 164eb5454c
commit 3139d37610
62 changed files with 261 additions and 256 deletions
--- a/hw/rtl/shared_memory/VX_shared_memory_block.v
+++ b/hw/rtl/shared_memory/VX_shared_memory_block.v
@@ -61,7 +61,7 @@ module VX_shared_memory_block
 		end

 		// Using ASIC MEM
-		/* verilator lint_off PINCONNECTEMPTY */
+		`IGNORE_WARNINGS_BEGIN
 	   rf2_128x128_wm1 first_ram (
 	         .CENYA(),
 	         .AYA(),
@@ -98,7 +98,7 @@ module VX_shared_memory_block
 	         .SEB(1'b0),
 	         .COLLDISN(1'b1)
 	   );
-	   /* verilator lint_on PINCONNECTEMPTY */
+	   `IGNORE_WARNINGS_END

 	`endif