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RTL code refactoring

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This commit is contained in:
Blaise Tine
2020-04-19 08:45:46 -04:00
parent 164eb5454c
commit 3139d37610
62 changed files with 261 additions and 256 deletions
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8
hw/rtl/cache/VX_cache_data.v vendored
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@@ -104,7 +104,7 @@ module VX_cache_data #(
assign data_use = data_out_d;
// Using ASIC MEM
/* verilator lint_off PINCONNECTEMPTY */
`IGNORE_WARNINGS_BEGIN
rf2_32x128_wm1 data (
.CENYA(),
.AYA(),
@@ -141,7 +141,7 @@ module VX_cache_data #(
.SEB(1'b0),
.COLLDISN(1'b1)
);
/* verilator lint_on PINCONNECTEMPTY */
`IGNORE_WARNINGS_END
wire[16:0] old_tag;
wire old_valid;
@@ -169,7 +169,7 @@ module VX_cache_data #(
assign valid_use = old_valid;
assign tag_use = old_tag;
/* verilator lint_off PINCONNECTEMPTY */
`IGNORE_WARNINGS_BEGIN
rf2_32x19_wm0 meta (
.CENYA(),
.AYA(),
@@ -206,7 +206,7 @@ module VX_cache_data #(
.SEB(1'b0),
.COLLDISN(1'b1)
);
/* verilator lint_on PINCONNECTEMPTY */
`IGNORE_WARNINGS_END
`endif
endmodule