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RTL code refactoring

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This commit is contained in:
Blaise Tine
2020-04-19 08:45:46 -04:00
parent 164eb5454c
commit 3139d37610
62 changed files with 261 additions and 256 deletions
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40
hw/rtl/Vortex.v
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@@ -99,12 +99,12 @@ module Vortex
wire schedule_delay;
// Dcache Interface
VX_gpu_dcache_rsp_inter #(.NUM_REQUESTS(`DNUM_REQUESTS)) vx_dcache_rsp();
VX_gpu_dcache_req_inter #(.NUM_REQUESTS(`DNUM_REQUESTS)) vx_dcache_req();
VX_gpu_dcache_req_inter #(.NUM_REQUESTS(`DNUM_REQUESTS)) vx_dcache_req_qual();
VX_gpu_dcache_rsp_if #(.NUM_REQUESTS(`DNUM_REQUESTS)) vx_dcache_rsp();
VX_gpu_dcache_req_if #(.NUM_REQUESTS(`DNUM_REQUESTS)) vx_dcache_req();
VX_gpu_dcache_req_if #(.NUM_REQUESTS(`DNUM_REQUESTS)) vx_dcache_req_qual();
VX_gpu_dcache_dram_req_inter #(.BANK_LINE_WORDS(`DBANK_LINE_WORDS)) vx_gpu_dcache_dram_req();
VX_gpu_dcache_dram_rsp_inter #(.BANK_LINE_WORDS(`DBANK_LINE_WORDS)) vx_gpu_dcache_dram_res();
VX_gpu_dcache_dram_req_if #(.BANK_LINE_WORDS(`DBANK_LINE_WORDS)) vx_gpu_dcache_dram_req();
VX_gpu_dcache_dram_rsp_if #(.BANK_LINE_WORDS(`DBANK_LINE_WORDS)) vx_gpu_dcache_dram_res();
assign vx_gpu_dcache_dram_res.dram_rsp_valid = dram_rsp_valid;
assign vx_gpu_dcache_dram_res.dram_rsp_addr = dram_rsp_addr;
@@ -144,11 +144,11 @@ module Vortex
assign vx_dcache_req_qual.core_req_pc = vx_dcache_req.core_req_pc;
assign vx_dcache_req_qual.core_no_wb_slot = vx_dcache_req.core_no_wb_slot;
VX_gpu_dcache_rsp_inter #(.NUM_REQUESTS(`INUM_REQUESTS)) vx_icache_rsp();
VX_gpu_dcache_req_inter #(.NUM_REQUESTS(`INUM_REQUESTS)) vx_icache_req();
VX_gpu_dcache_rsp_if #(.NUM_REQUESTS(`INUM_REQUESTS)) vx_icache_rsp();
VX_gpu_dcache_req_if #(.NUM_REQUESTS(`INUM_REQUESTS)) vx_icache_req();
VX_gpu_dcache_dram_req_inter #(.BANK_LINE_WORDS(`IBANK_LINE_WORDS)) vx_gpu_icache_dram_req();
VX_gpu_dcache_dram_rsp_inter #(.BANK_LINE_WORDS(`IBANK_LINE_WORDS)) vx_gpu_icache_dram_res();
VX_gpu_dcache_dram_req_if #(.BANK_LINE_WORDS(`IBANK_LINE_WORDS)) vx_gpu_icache_dram_req();
VX_gpu_dcache_dram_rsp_if #(.BANK_LINE_WORDS(`IBANK_LINE_WORDS)) vx_gpu_icache_dram_res();
assign vx_gpu_icache_dram_res.dram_rsp_valid = I_dram_rsp_valid;
assign vx_gpu_icache_dram_res.dram_rsp_addr = I_dram_rsp_addr;
@@ -171,19 +171,19 @@ module Vortex
/////////////////////////////////////////////////////////////////////////
// Front-end to Back-end
VX_frE_to_bckE_req_inter vx_bckE_req(); // New instruction request to EXE/MEM
VX_frE_to_bckE_req_if vx_bckE_req(); // New instruction request to EXE/MEM
// Back-end to Front-end
VX_wb_inter vx_writeback_inter(); // Writeback to GPRs
VX_branch_response_inter vx_branch_rsp(); // Branch Resolution to Fetch
VX_jal_response_inter vx_jal_rsp(); // Jump resolution to Fetch
VX_wb_if vx_writeback_if(); // Writeback to GPRs
VX_branch_response_if vx_branch_rsp(); // Branch Resolution to Fetch
VX_jal_response_if vx_jal_rsp(); // Jump resolution to Fetch
// CSR Buses
// VX_csr_write_request_inter vx_csr_w_req();
// VX_csr_write_request_if vx_csr_w_req();
VX_warp_ctl_inter vx_warp_ctl();
VX_gpu_snp_req_rsp vx_gpu_icache_snp_req();
VX_gpu_snp_req_rsp vx_gpu_dcache_snp_req();
VX_warp_ctl_if vx_warp_ctl();
VX_gpu_snp_req_rsp_if vx_gpu_icache_snp_req();
VX_gpu_snp_req_rsp_if vx_gpu_dcache_snp_req();
assign vx_gpu_dcache_snp_req.snp_req_valid = snp_req_valid;
assign vx_gpu_dcache_snp_req.snp_req_addr = snp_req_addr;
@@ -209,7 +209,7 @@ VX_scheduler schedule(
.exec_delay (exec_delay),
.gpr_stage_delay (gpr_stage_delay),
.vx_bckE_req (vx_bckE_req),
.vx_writeback_inter (vx_writeback_inter),
.vx_writeback_if (vx_writeback_if),
.schedule_delay (schedule_delay),
.is_empty (scheduler_empty)
);
@@ -224,7 +224,7 @@ VX_back_end #(.CORE_ID(CORE_ID)) vx_back_end(
.vx_branch_rsp (vx_branch_rsp),
.vx_dcache_rsp (vx_dcache_rsp),
.vx_dcache_req (vx_dcache_req),
.vx_writeback_inter (vx_writeback_inter),
.vx_writeback_if (vx_writeback_if),
.out_mem_delay (memory_delay),
.out_exec_delay (exec_delay),
.gpr_stage_delay (gpr_stage_delay)
@@ -257,7 +257,7 @@ VX_dmem_controller vx_dmem_controller(
// .clk (clk),
// .in_decode_csr_address(decode_csr_address),
// .vx_csr_w_req (vx_csr_w_req),
// .in_wb_valid (vx_writeback_inter.wb_valid[0]),
// .in_wb_valid (vx_writeback_if.wb_valid[0]),
// .out_decode_csr_data (csr_decode_csr_data)
// );