RTL code refactoring
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@@ -3,12 +3,12 @@
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module VX_decode(
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// Fetch Inputs
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VX_inst_meta_inter fd_inst_meta_de,
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VX_inst_meta_if fd_inst_meta_de,
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// Outputs
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VX_frE_to_bckE_req_inter vx_frE_to_bckE_req,
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VX_wstall_inter vx_wstall,
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VX_join_inter vx_join,
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VX_frE_to_bckE_req_if vx_frE_to_bckE_req,
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VX_wstall_if vx_wstall,
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VX_join_if vx_join,
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output wire terminate_sim
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