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adding support for non-cacheable memory addressing

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This commit is contained in:
Blaise Tine
2021-06-06 13:35:55 -07:00
parent 84391c1a06
commit 3071fb7a29
23 changed files with 1605 additions and 205 deletions
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16
hw/rtl/VX_config.vh
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@@ -45,20 +45,20 @@
`define STARTUP_ADDR 32'h80000000
`endif
`ifndef IO_BUS_BASE_ADDR
`define IO_BUS_BASE_ADDR 32'hFF000000
`ifndef IO_BASE_ADDR
`define IO_BASE_ADDR 32'hFF000000
`endif
`ifndef SHARED_MEM_BASE_ADDR
`define SHARED_MEM_BASE_ADDR `IO_BUS_BASE_ADDR
`ifndef IO_ADDR_SIZE
`define IO_ADDR_SIZE (32'hFFFFFFFF - 32'hFF000000 + 1)
`endif
`ifndef SHARED_MEM_BASE_ADDR_ALIGN
`define SHARED_MEM_BASE_ADDR_ALIGN 64
`ifndef IO_ADDR_COUT
`define IO_ADDR_COUT 32'hFFFFFFFC
`endif
`ifndef IO_BUS_ADDR_COUT
`define IO_BUS_ADDR_COUT 32'hFFFFFFFC
`ifndef SMEM_BASE_ADDR
`define SMEM_BASE_ADDR `IO_BASE_ADDR
`endif
`ifndef FRAME_BUFFER_BASE_ADDR