From 2f5ccdcf454d6eea110f08da5455c48091d1506d Mon Sep 17 00:00:00 2001 From: Blaise Tine Date: Mon, 19 Apr 2021 21:29:39 -0700 Subject: [PATCH] quartus synthesis build update --- hw/syn/quartus/Makefile | 50 ++++++++++++++++++++++++-------- hw/syn/quartus/cache/Makefile | 12 ++++---- hw/syn/quartus/core/Makefile | 18 +++++++----- hw/syn/quartus/pipeline/Makefile | 18 +++++++++--- hw/syn/quartus/top1/Makefile | 22 +++++++------- hw/syn/quartus/top16/Makefile | 22 +++++++------- hw/syn/quartus/top2/Makefile | 22 +++++++------- hw/syn/quartus/top32/Makefile | 22 +++++++------- hw/syn/quartus/top4/Makefile | 22 +++++++------- hw/syn/quartus/top64/Makefile | 22 +++++++------- hw/syn/quartus/top8/Makefile | 22 +++++++------- hw/syn/quartus/unittest/Makefile | 18 ++++++++---- hw/syn/quartus/vortex/Makefile | 20 ++++++------- 13 files changed, 167 insertions(+), 123 deletions(-) diff --git a/hw/syn/quartus/Makefile b/hw/syn/quartus/Makefile index 66d95034..4dd40a40 100644 --- a/hw/syn/quartus/Makefile +++ b/hw/syn/quartus/Makefile @@ -1,37 +1,63 @@ +BUILDIR ?= build + .PHONY: unittest pipeline cache core vortex top1 top2 top4 top8 top16 top32 top64 unittest: - $(MAKE) -C unittest clean && $(MAKE) -C unittest > unittest/build.log 2>&1 & + mkdir -p core/$(BUILDIR) + cp core/Makefile core/$(BUILDIR) + $(MAKE) -C unittest/$(BUILDIR) clean && $(MAKE) -C unittest/$(BUILDIR) > unittest//$(BUILDIR)build.log 2>&1 & pipeline: - $(MAKE) -C pipeline clean && $(MAKE) -C pipeline > pipeline/build.log 2>&1 & + mkdir -p core/$(BUILDIR) + cp core/Makefile core/$(BUILDIR) + $(MAKE) -C pipeline/$(BUILDIR) clean && $(MAKE) -C pipeline/$(BUILDIR) > pipeline/$(BUILDIR)/build.log 2>&1 & cache: - $(MAKE) -C cache clean && $(MAKE) -C cache > cache/build.log 2>&1 & + mkdir -p core/$(BUILDIR) + cp core/Makefile core/$(BUILDIR) + $(MAKE) -C cache/$(BUILDIR) clean && $(MAKE) -C cache/$(BUILDIR) > cache/$(BUILDIR)/build.log 2>&1 & core: - $(MAKE) -C core clean && $(MAKE) -C core > core/build.log 2>&1 & + mkdir -p core/$(BUILDIR) + cp core/Makefile core/$(BUILDIR) + $(MAKE) -C core/$(BUILDIR) clean && $(MAKE) -C core/$(BUILDIR) > core/$(BUILDIR)/build.log 2>&1 & vortex: - $(MAKE) -C vortex clean && $(MAKE) -C vortex > vortex/build.log 2>&1 & + mkdir -p core/$(BUILDIR) + cp core/Makefile core/$(BUILDIR) + $(MAKE) -C vortex/$(BUILDIR) clean && $(MAKE) -C vortex/$(BUILDIR) > vortex/$(BUILDIR)/build.log 2>&1 & top1: - $(MAKE) -C top1 clean && $(MAKE) -C top1 > top1/build.log 2>&1 & + mkdir -p core/$(BUILDIR) + cp core/Makefile core/$(BUILDIR) + $(MAKE) -C top1/$(BUILDIR) clean && $(MAKE) -C top1/$(BUILDIR) > top1/$(BUILDIR)/build.log 2>&1 & top2: - $(MAKE) -C top2 clean && $(MAKE) -C top2 > top2/build.log 2>&1 & + mkdir -p core/$(BUILDIR) + cp core/Makefile core/$(BUILDIR) + $(MAKE) -C top2/$(BUILDIR) clean && $(MAKE) -C top2/$(BUILDIR) > top2/$(BUILDIR)/build.log 2>&1 & top4: - $(MAKE) -C top4 clean && $(MAKE) -C top4 > top4/build.log 2>&1 & + mkdir -p core/$(BUILDIR) + cp core/Makefile core/$(BUILDIR) + $(MAKE) -C top4/$(BUILDIR) clean && $(MAKE) -C top4/$(BUILDIR) > top4/$(BUILDIR)/build.log 2>&1 & top8: - $(MAKE) -C top8 clean && $(MAKE) -C top8 > top8/build.log 2>&1 & + mkdir -p core/$(BUILDIR) + cp core/Makefile core/$(BUILDIR) + $(MAKE) -C top8/$(BUILDIR) clean && $(MAKE) -C top8/$(BUILDIR) > top8/$(BUILDIR)/build.log 2>&1 & top16: - $(MAKE) -C top16 clean && $(MAKE) -C top16 > top16/build.log 2>&1 & + mkdir -p core/$(BUILDIR) + cp core/Makefile core/$(BUILDIR) + $(MAKE) -C top16/$(BUILDIR) clean && $(MAKE) -C top16/$(BUILDIR) > top16/$(BUILDIR)build.log 2>&1 & top32: - $(MAKE) -C top32 clean && $(MAKE) -C top32 > top32/build.log 2>&1 & + mkdir -p core/$(BUILDIR) + cp core/Makefile core/$(BUILDIR) + $(MAKE) -C top32/$(BUILDIR) clean && $(MAKE) -C top32/$(BUILDIR) > top32/$(BUILDIR)/build.log 2>&1 & top64: - $(MAKE) -C top64 clean && $(MAKE) -C top64 > top64/build.log 2>&1 & \ No newline at end of file + mkdir -p core/$(BUILDIR) + cp core/Makefile core/$(BUILDIR) + $(MAKE) -C top64/$(BUILDIR) clean && $(MAKE) -C top64/$(BUILDIR) > top64/$(BUILDIR)/build.log 2>&1 & \ No newline at end of file diff --git a/hw/syn/quartus/cache/Makefile b/hw/syn/quartus/cache/Makefile index 34ffd29c..d28d9b18 100755 --- a/hw/syn/quartus/cache/Makefile +++ b/hw/syn/quartus/cache/Makefile @@ -1,14 +1,12 @@ -# Part, Family -FAMILY = "Arria 10" -DEVICE = 10AX115N3F40E2SG - PROJECT = VX_cache TOP_LEVEL_ENTITY = VX_cache SRC_FILE = VX_cache.v +RTL_DIR = ../../../../rtl + +FAMILY = "Arria 10" +DEVICE = 10AX115N3F40E2SG -RTL_DIR=../../../rtl RTL_INCLUDE = $(RTL_DIR);$(RTL_DIR)/libs;$(RTL_DIR)/interfaces;$(RTL_DIR)/cache - PROJECT_FILES = $(PROJECT).qpf $(PROJECT).qsf # Executable Configuration @@ -53,7 +51,7 @@ smart.log: $(PROJECT_FILES) # Project initialization $(PROJECT_FILES): - quartus_sh -t ../project.tcl -project $(PROJECT) -family $(FAMILY) -device $(DEVICE) -top $(TOP_LEVEL_ENTITY) -src $(SRC_FILE) -sdc ../project.sdc -inc "$(RTL_INCLUDE)" + quartus_sh -t ../../project.tcl -project $(PROJECT) -family $(FAMILY) -device $(DEVICE) -top $(TOP_LEVEL_ENTITY) -src $(SRC_FILE) -sdc ../../project.sdc -inc "$(RTL_INCLUDE)" syn.chg: $(STAMP) syn.chg diff --git a/hw/syn/quartus/core/Makefile b/hw/syn/quartus/core/Makefile index 03d89e3f..37e42df0 100644 --- a/hw/syn/quartus/core/Makefile +++ b/hw/syn/quartus/core/Makefile @@ -1,13 +1,17 @@ -# Part, Family -FAMILY = "Arria 10" -DEVICE = 10AX115N3F40E2SG - PROJECT = Core TOP_LEVEL_ENTITY = VX_core SRC_FILE = VX_core.v +RTL_DIR = ../../../../rtl -RTL_DIR=../../../rtl -FPU_INCLUDE = $(RTL_DIR)/fp_cores;$(RTL_DIR)/fp_cores/altera/arria10;$(RTL_DIR)/fp_cores/fpnew/src;$(RTL_DIR)/fp_cores/fpnew/src/fpu_div_sqrt_mvp/hdl;$(RTL_DIR)/fp_cores/fpnew/src/common_cells/include;$(RTL_DIR)/fp_cores/fpnew/src/common_cells/src +FAMILY = "Arria 10" +DEVICE = 10AX115N3F40E2SG +FPU_CORE_PATH = $(RTL_DIR)/fp_cores/altera/arria10 + +#FAMILY = "Stratix 10" +#DEVICE = 1SX280HN2F43E2VG +#FPU_CORE_PATH = $(RTL_DIR)/fp_cores/altera/stratix10 + +FPU_INCLUDE = $(RTL_DIR)/fp_cores;$(FPU_CORE_PATH);$(RTL_DIR)/fp_cores/fpnew/src;$(RTL_DIR)/fp_cores/fpnew/src/fpu_div_sqrt_mvp/hdl;$(RTL_DIR)/fp_cores/fpnew/src/common_cells/include;$(RTL_DIR)/fp_cores/fpnew/src/common_cells/src RTL_INCLUDE = $(RTL_DIR);$(RTL_DIR)/libs;$(RTL_DIR)/interfaces;$(RTL_DIR)/cache;$(FPU_INCLUDE) PROJECT_FILES = $(PROJECT).qpf $(PROJECT).qsf @@ -54,7 +58,7 @@ smart.log: $(PROJECT_FILES) # Project initialization $(PROJECT_FILES): - quartus_sh -t ../project.tcl -project $(PROJECT) -family $(FAMILY) -device $(DEVICE) -top $(TOP_LEVEL_ENTITY) -src "$(SRC_FILE)" -sdc ../project.sdc -inc "$(RTL_INCLUDE)" + quartus_sh -t ../../project.tcl -project $(PROJECT) -family $(FAMILY) -device $(DEVICE) -top $(TOP_LEVEL_ENTITY) -src "$(SRC_FILE)" -sdc ../../project.sdc -inc "$(RTL_INCLUDE)" syn.chg: $(STAMP) syn.chg diff --git a/hw/syn/quartus/pipeline/Makefile b/hw/syn/quartus/pipeline/Makefile index 095e19ce..bd259697 100644 --- a/hw/syn/quartus/pipeline/Makefile +++ b/hw/syn/quartus/pipeline/Makefile @@ -1,8 +1,18 @@ PROJECT = VX_pipeline TOP_LEVEL_ENTITY = VX_pipeline SRC_FILE = VX_pipeline.v -FPU_INCLUDE = ../../../rtl/fp_cores;../../../rtl/fp_cores/altera/arria10;../../../rtl/fp_cores/fpnew/src;../../../rtl/fp_cores/fpnew/src/fpu_div_sqrt_mvp/hdl;../../../rtl/fp_cores/fpnew/src/common_cells/include;../../../rtl/fp_cores/fpnew/src/common_cells/src -RTL_INCLUDE = $(FPU_INCLUDE);../../../rtl;../../../rtl/libs;../../../rtl/interfaces +RTL_DIR = ../../../rtl + +FAMILY = "Arria 10" +DEVICE = 10AX115N3F40E2SG +FPU_CORE_PATH = $(RTL_DIR)/fp_cores/altera/arria10 + +#FAMILY = "Stratix 10" +#DEVICE = 1SX280HN2F43E2VG +#FPU_CORE_PATH = $(RTL_DIR)/fp_cores/altera/stratix10 + +FPU_INCLUDE = $(RTL_DIR)/fp_cores;$(FPU_CORE_PATH);$(RTL_DIR)/fp_cores/fpnew/src;$(RTL_DIR)/fp_cores/fpnew/src/fpu_div_sqrt_mvp/hdl;$(RTL_DIR)/fp_cores/fpnew/src/common_cells/include;$(RTL_DIR)/fp_cores/fpnew/src/common_cells/src +RTL_INCLUDE = $(FPU_INCLUDE);$(RTL_DIR);$(RTL_DIR)/libs;$(RTL_DIR)/interfaces PROJECT_FILES = $(PROJECT).qpf $(PROJECT).qsf # Part, Family @@ -51,7 +61,7 @@ smart.log: $(PROJECT_FILES) # Project initialization $(PROJECT_FILES): - quartus_sh -t ../project.tcl -project $(PROJECT) -family $(FAMILY) -device $(DEVICE) -top $(TOP_LEVEL_ENTITY) -src "$(SRC_FILE)" -sdc ../project.sdc -inc "$(RTL_INCLUDE)" + quartus_sh -t ../../project.tcl -project $(PROJECT) -family $(FAMILY) -device $(DEVICE) -top $(TOP_LEVEL_ENTITY) -src "$(SRC_FILE)" -sdc ../../project.sdc -inc "$(RTL_INCLUDE)" syn.chg: $(STAMP) syn.chg @@ -66,7 +76,7 @@ asm.chg: $(STAMP) asm.chg timing: $(PROJECT_FILES) - quartus_sh -t ../timing-html.tcl -project $(PROJECT) + quartus_sh -t ../../timing-html.tcl -project $(PROJECT) program: $(PROJECT).sof quartus_pgm --no_banner --mode=jtag -o "$(PROJECT).sof" diff --git a/hw/syn/quartus/top1/Makefile b/hw/syn/quartus/top1/Makefile index eec14202..465cb192 100644 --- a/hw/syn/quartus/top1/Makefile +++ b/hw/syn/quartus/top1/Makefile @@ -1,18 +1,18 @@ -FAMILY = "Arria 10" -DEVICE = 10AX115N3F40E2SG -FPU_CORE_PATH=../../../rtl/fp_cores/altera/arria10 - -#FAMILY = "Stratix 10" -#DEVICE = 1SX280HN2F43E2VG -#FPU_CORE_PATH=../../../rtl/fp_cores/altera/stratix10 - PROJECT = vortex_afu TOP_LEVEL_ENTITY = vortex_afu SRC_FILE = vortex_afu.sv +RTL_DIR = ../../../../rtl + +FAMILY = "Arria 10" +DEVICE = 10AX115N3F40E2SG +FPU_CORE_PATH = $(RTL_DIR)/fp_cores/altera/arria10 + +#FAMILY = "Stratix 10" +#DEVICE = 1SX280HN2F43E2VG +#FPU_CORE_PATH = $(RTL_DIR)/fp_cores/altera/stratix10 -RTL_DIR=../../../rtl FPU_INCLUDE = $(RTL_DIR)/fp_cores;$(FPU_CORE_PATH);$(RTL_DIR)/fp_cores/fpnew/src;$(RTL_DIR)/fp_cores/fpnew/src/fpu_div_sqrt_mvp/hdl;$(RTL_DIR)/fp_cores/fpnew/src/common_cells/include;$(RTL_DIR)/fp_cores/fpnew/src/common_cells/src -RTL_INCLUDE = $(RTL_DIR);$(RTL_DIR)/libs;$(RTL_DIR)/interfaces;$(RTL_DIR)/cache;../../../rtl/afu;../../../rtl/afu/ccip;$(FPU_INCLUDE) +RTL_INCLUDE = $(RTL_DIR);$(RTL_DIR)/libs;$(RTL_DIR)/interfaces;$(RTL_DIR)/cache;$(RTL_DIR)/afu;$(RTL_DIR)/afu/ccip;$(FPU_INCLUDE) PROJECT_FILES = $(PROJECT).qpf $(PROJECT).qsf @@ -58,7 +58,7 @@ smart.log: $(PROJECT_FILES) # Project initialization $(PROJECT_FILES): - quartus_sh -t ../project.tcl -project $(PROJECT) -family $(FAMILY) -device $(DEVICE) -top $(TOP_LEVEL_ENTITY) -src "$(SRC_FILE)" -sdc ../project.sdc -inc "$(RTL_INCLUDE)" -set "NOPAE" -set "NUM_CORES=1" + quartus_sh -t ../../project.tcl -project $(PROJECT) -family $(FAMILY) -device $(DEVICE) -top $(TOP_LEVEL_ENTITY) -src "$(SRC_FILE)" -sdc ../../project.sdc -inc "$(RTL_INCLUDE)" -set "NOPAE" -set "NUM_CORES=1" syn.chg: $(STAMP) syn.chg diff --git a/hw/syn/quartus/top16/Makefile b/hw/syn/quartus/top16/Makefile index 28e02490..bd31b20a 100644 --- a/hw/syn/quartus/top16/Makefile +++ b/hw/syn/quartus/top16/Makefile @@ -1,18 +1,18 @@ -FAMILY = "Arria 10" -DEVICE = 10AX115N3F40E2SG -FPU_CORE_PATH=../../../rtl/fp_cores/altera/arria10 - -#FAMILY = "Stratix 10" -#DEVICE = 1SX280HN2F43E2VG -#FPU_CORE_PATH=../../../rtl/fp_cores/altera/stratix10 - PROJECT = vortex_afu TOP_LEVEL_ENTITY = vortex_afu SRC_FILE = vortex_afu.sv +RTL_DIR = ../../../../rtl + +FAMILY = "Arria 10" +DEVICE = 10AX115N3F40E2SG +FPU_CORE_PATH = $(RTL_DIR)/fp_cores/altera/arria10 + +#FAMILY = "Stratix 10" +#DEVICE = 1SX280HN2F43E2VG +#FPU_CORE_PATH = $(RTL_DIR)/fp_cores/altera/stratix10 -RTL_DIR=../../../rtl FPU_INCLUDE = $(RTL_DIR)/fp_cores;$(FPU_CORE_PATH);$(RTL_DIR)/fp_cores/fpnew/src;$(RTL_DIR)/fp_cores/fpnew/src/fpu_div_sqrt_mvp/hdl;$(RTL_DIR)/fp_cores/fpnew/src/common_cells/include;$(RTL_DIR)/fp_cores/fpnew/src/common_cells/src -RTL_INCLUDE = $(RTL_DIR);$(RTL_DIR)/libs;$(RTL_DIR)/interfaces;$(RTL_DIR)/cache;../../../rtl/afu;../../../rtl/afu/ccip;$(FPU_INCLUDE) +RTL_INCLUDE = $(RTL_DIR);$(RTL_DIR)/libs;$(RTL_DIR)/interfaces;$(RTL_DIR)/cache;$(RTL_DIR)/afu;$(RTL_DIR)/afu/ccip;$(FPU_INCLUDE) PROJECT_FILES = $(PROJECT).qpf $(PROJECT).qsf @@ -58,7 +58,7 @@ smart.log: $(PROJECT_FILES) # Project initialization $(PROJECT_FILES): - quartus_sh -t ../project.tcl -project $(PROJECT) -family $(FAMILY) -device $(DEVICE) -top $(TOP_LEVEL_ENTITY) -src "$(SRC_FILE)" -sdc ../project.sdc -inc "$(RTL_INCLUDE)" -set "NOPAE" -set "NUM_CORES=4" -set "NUM_CLUSTERS=4" + quartus_sh -t ../../project.tcl -project $(PROJECT) -family $(FAMILY) -device $(DEVICE) -top $(TOP_LEVEL_ENTITY) -src "$(SRC_FILE)" -sdc ../../project.sdc -inc "$(RTL_INCLUDE)" -set "NOPAE" -set "NUM_CORES=4" -set "NUM_CLUSTERS=4" syn.chg: $(STAMP) syn.chg diff --git a/hw/syn/quartus/top2/Makefile b/hw/syn/quartus/top2/Makefile index 0de5492d..31234939 100644 --- a/hw/syn/quartus/top2/Makefile +++ b/hw/syn/quartus/top2/Makefile @@ -1,18 +1,18 @@ -FAMILY = "Arria 10" -DEVICE = 10AX115N3F40E2SG -FPU_CORE_PATH=../../../rtl/fp_cores/altera/arria10 - -#FAMILY = "Stratix 10" -#DEVICE = 1SX280HN2F43E2VG -#FPU_CORE_PATH=../../../rtl/fp_cores/altera/stratix10 - PROJECT = vortex_afu TOP_LEVEL_ENTITY = vortex_afu SRC_FILE = vortex_afu.sv +RTL_DIR = ../../../../rtl + +FAMILY = "Arria 10" +DEVICE = 10AX115N3F40E2SG +FPU_CORE_PATH=$(RTL_DIR)/fp_cores/altera/arria10 + +#FAMILY = "Stratix 10" +#DEVICE = 1SX280HN2F43E2VG +#FPU_CORE_PATH = $(RTL_DIR)/fp_cores/altera/stratix10 -RTL_DIR=../../../rtl FPU_INCLUDE = $(RTL_DIR)/fp_cores;$(FPU_CORE_PATH);$(RTL_DIR)/fp_cores/fpnew/src;$(RTL_DIR)/fp_cores/fpnew/src/fpu_div_sqrt_mvp/hdl;$(RTL_DIR)/fp_cores/fpnew/src/common_cells/include;$(RTL_DIR)/fp_cores/fpnew/src/common_cells/src -RTL_INCLUDE = $(RTL_DIR);$(RTL_DIR)/libs;$(RTL_DIR)/interfaces;$(RTL_DIR)/cache;../../../rtl/afu;../../../rtl/afu/ccip;$(FPU_INCLUDE) +RTL_INCLUDE = $(RTL_DIR);$(RTL_DIR)/libs;$(RTL_DIR)/interfaces;$(RTL_DIR)/cache;$(RTL_DIR)/afu;$(RTL_DIR)/afu/ccip;$(FPU_INCLUDE) PROJECT_FILES = $(PROJECT).qpf $(PROJECT).qsf @@ -58,7 +58,7 @@ smart.log: $(PROJECT_FILES) # Project initialization $(PROJECT_FILES): - quartus_sh -t ../project.tcl -project $(PROJECT) -family $(FAMILY) -device $(DEVICE) -top $(TOP_LEVEL_ENTITY) -src "$(SRC_FILE)" -sdc ../project.sdc -inc "$(RTL_INCLUDE)" -set "NOPAE" -set "NUM_CORES=2" + quartus_sh -t ../../project.tcl -project $(PROJECT) -family $(FAMILY) -device $(DEVICE) -top $(TOP_LEVEL_ENTITY) -src "$(SRC_FILE)" -sdc ../../project.sdc -inc "$(RTL_INCLUDE)" -set "NOPAE" -set "NUM_CORES=2" syn.chg: $(STAMP) syn.chg diff --git a/hw/syn/quartus/top32/Makefile b/hw/syn/quartus/top32/Makefile index 75bd55b3..558359e5 100644 --- a/hw/syn/quartus/top32/Makefile +++ b/hw/syn/quartus/top32/Makefile @@ -1,18 +1,18 @@ -#FAMILY = "Arria 10" -#DEVICE = 10AX115N3F40E2SG -#FPU_CORE_PATH=../../../rtl/fp_cores/altera/arria10 - -FAMILY = "Stratix 10" -DEVICE = 1SX280HN2F43E2VG -FPU_CORE_PATH=../../../rtl/fp_cores/altera/stratix10 - PROJECT = vortex_afu TOP_LEVEL_ENTITY = vortex_afu SRC_FILE = vortex_afu.sv +RTL_DIR = ../../../../rtl + +#FAMILY = "Arria 10" +#DEVICE = 10AX115N3F40E2SG +#FPU_CORE_PATH = $(RTL_DIR)/fp_cores/altera/arria10 + +FAMILY = "Stratix 10" +DEVICE = 1SX280HN2F43E2VG +FPU_CORE_PATH = $(RTL_DIR)/fp_cores/altera/stratix10 -RTL_DIR=../../../rtl FPU_INCLUDE = $(RTL_DIR)/fp_cores;$(FPU_CORE_PATH);$(RTL_DIR)/fp_cores/fpnew/src;$(RTL_DIR)/fp_cores/fpnew/src/fpu_div_sqrt_mvp/hdl;$(RTL_DIR)/fp_cores/fpnew/src/common_cells/include;$(RTL_DIR)/fp_cores/fpnew/src/common_cells/src -RTL_INCLUDE = $(RTL_DIR);$(RTL_DIR)/libs;$(RTL_DIR)/interfaces;$(RTL_DIR)/cache;../../../rtl/afu;../../../rtl/afu/ccip;$(FPU_INCLUDE) +RTL_INCLUDE = $(RTL_DIR);$(RTL_DIR)/libs;$(RTL_DIR)/interfaces;$(RTL_DIR)/cache;$(RTL_DIR)/afu;$(RTL_DIR)/afu/ccip;$(FPU_INCLUDE) PROJECT_FILES = $(PROJECT).qpf $(PROJECT).qsf @@ -58,7 +58,7 @@ smart.log: $(PROJECT_FILES) # Project initialization $(PROJECT_FILES): - quartus_sh -t ../project.tcl -project $(PROJECT) -family $(FAMILY) -device $(DEVICE) -top $(TOP_LEVEL_ENTITY) -src "$(SRC_FILE)" -sdc ../project.sdc -inc "$(RTL_INCLUDE)" -set "NOPAE" -set "NUM_CORES=4" -set "NUM_CLUSTERS=8" + quartus_sh -t ../../project.tcl -project $(PROJECT) -family $(FAMILY) -device $(DEVICE) -top $(TOP_LEVEL_ENTITY) -src "$(SRC_FILE)" -sdc ../../project.sdc -inc "$(RTL_INCLUDE)" -set "NOPAE" -set "NUM_CORES=4" -set "NUM_CLUSTERS=8" syn.chg: $(STAMP) syn.chg diff --git a/hw/syn/quartus/top4/Makefile b/hw/syn/quartus/top4/Makefile index 55e25c01..2bdd4f1d 100644 --- a/hw/syn/quartus/top4/Makefile +++ b/hw/syn/quartus/top4/Makefile @@ -1,18 +1,18 @@ -FAMILY = "Arria 10" -DEVICE = 10AX115N3F40E2SG -FPU_CORE_PATH=../../../rtl/fp_cores/altera/arria10 - -#FAMILY = "Stratix 10" -#DEVICE = 1SX280HN2F43E2VG -#FPU_CORE_PATH=../../../rtl/fp_cores/altera/stratix10 - PROJECT = vortex_afu TOP_LEVEL_ENTITY = vortex_afu SRC_FILE = vortex_afu.sv +RTL_DIR = ../../../../rtl + +FAMILY = "Arria 10" +DEVICE = 10AX115N3F40E2SG +FPU_CORE_PATH = $(RTL_DIR)/fp_cores/altera/arria10 + +#FAMILY = "Stratix 10" +#DEVICE = 1SX280HN2F43E2VG +#FPU_CORE_PATH = $(RTL_DIR)/fp_cores/altera/stratix10 -RTL_DIR=../../../rtl FPU_INCLUDE = $(RTL_DIR)/fp_cores;$(FPU_CORE_PATH);$(RTL_DIR)/fp_cores/fpnew/src;$(RTL_DIR)/fp_cores/fpnew/src/fpu_div_sqrt_mvp/hdl;$(RTL_DIR)/fp_cores/fpnew/src/common_cells/include;$(RTL_DIR)/fp_cores/fpnew/src/common_cells/src -RTL_INCLUDE = $(RTL_DIR);$(RTL_DIR)/libs;$(RTL_DIR)/interfaces;$(RTL_DIR)/cache;../../../rtl/afu;../../../rtl/afu/ccip;$(FPU_INCLUDE) +RTL_INCLUDE = $(RTL_DIR);$(RTL_DIR)/libs;$(RTL_DIR)/interfaces;$(RTL_DIR)/cache;$(RTL_DIR)/afu;$(RTL_DIR)/afu/ccip;$(FPU_INCLUDE) PROJECT_FILES = $(PROJECT).qpf $(PROJECT).qsf @@ -58,7 +58,7 @@ smart.log: $(PROJECT_FILES) # Project initialization $(PROJECT_FILES): - quartus_sh -t ../project.tcl -project $(PROJECT) -family $(FAMILY) -device $(DEVICE) -top $(TOP_LEVEL_ENTITY) -src "$(SRC_FILE)" -sdc ../project.sdc -inc "$(RTL_INCLUDE)" -set "NOPAE" -set "NUM_CORES=4" + quartus_sh -t ../../project.tcl -project $(PROJECT) -family $(FAMILY) -device $(DEVICE) -top $(TOP_LEVEL_ENTITY) -src "$(SRC_FILE)" -sdc ../../project.sdc -inc "$(RTL_INCLUDE)" -set "NOPAE" -set "NUM_CORES=4" syn.chg: $(STAMP) syn.chg diff --git a/hw/syn/quartus/top64/Makefile b/hw/syn/quartus/top64/Makefile index e3c44b2a..89e23aa4 100644 --- a/hw/syn/quartus/top64/Makefile +++ b/hw/syn/quartus/top64/Makefile @@ -1,18 +1,18 @@ -#FAMILY = "Arria 10" -#DEVICE = 10AX115N3F40E2SG -#FPU_CORE_PATH=../../../rtl/fp_cores/altera/arria10 - -FAMILY = "Stratix 10" -DEVICE = 1SX280HN2F43E2VG -FPU_CORE_PATH=../../../rtl/fp_cores/altera/stratix10 - PROJECT = vortex_afu TOP_LEVEL_ENTITY = vortex_afu SRC_FILE = vortex_afu.sv +RTL_DIR=../../../../rtl + +#FAMILY = "Arria 10" +#DEVICE = 10AX115N3F40E2SG +#FPU_CORE_PATH=$(RTL_DIR)/fp_cores/altera/arria10 + +FAMILY = "Stratix 10" +DEVICE = 1SX280HN2F43E2VG +FPU_CORE_PATH=$(RTL_DIR)/fp_cores/altera/stratix10 -RTL_DIR=../../../rtl FPU_INCLUDE = $(RTL_DIR)/fp_cores;$(FPU_CORE_PATH);$(RTL_DIR)/fp_cores/fpnew/src;$(RTL_DIR)/fp_cores/fpnew/src/fpu_div_sqrt_mvp/hdl;$(RTL_DIR)/fp_cores/fpnew/src/common_cells/include;$(RTL_DIR)/fp_cores/fpnew/src/common_cells/src -RTL_INCLUDE = $(RTL_DIR);$(RTL_DIR)/libs;$(RTL_DIR)/interfaces;$(RTL_DIR)/cache;../../../rtl/afu;../../../rtl/afu/ccip;$(FPU_INCLUDE) +RTL_INCLUDE = $(RTL_DIR);$(RTL_DIR)/libs;$(RTL_DIR)/interfaces;$(RTL_DIR)/cache;$(RTL_DIR)/afu;$(RTL_DIR)/afu/ccip;$(FPU_INCLUDE) PROJECT_FILES = $(PROJECT).qpf $(PROJECT).qsf @@ -58,7 +58,7 @@ smart.log: $(PROJECT_FILES) # Project initialization $(PROJECT_FILES): - quartus_sh -t ../project.tcl -project $(PROJECT) -family $(FAMILY) -device $(DEVICE) -top $(TOP_LEVEL_ENTITY) -src "$(SRC_FILE)" -sdc ../project.sdc -inc "$(RTL_INCLUDE)" -set "NOPAE" -set "NUM_CORES=8" -set "NUM_CLUSTERS=8" + quartus_sh -t ../../project.tcl -project $(PROJECT) -family $(FAMILY) -device $(DEVICE) -top $(TOP_LEVEL_ENTITY) -src "$(SRC_FILE)" -sdc ../../project.sdc -inc "$(RTL_INCLUDE)" -set "NOPAE" -set "NUM_CORES=8" -set "NUM_CLUSTERS=8" syn.chg: $(STAMP) syn.chg diff --git a/hw/syn/quartus/top8/Makefile b/hw/syn/quartus/top8/Makefile index 9caa490b..07605567 100644 --- a/hw/syn/quartus/top8/Makefile +++ b/hw/syn/quartus/top8/Makefile @@ -1,18 +1,18 @@ -FAMILY = "Arria 10" -DEVICE = 10AX115N3F40E2SG -FPU_CORE_PATH=../../../rtl/fp_cores/altera/arria10 - -#FAMILY = "Stratix 10" -#DEVICE = 1SX280HN2F43E2VG -#FPU_CORE_PATH=../../../rtl/fp_cores/altera/stratix10 - PROJECT = vortex_afu TOP_LEVEL_ENTITY = vortex_afu SRC_FILE = vortex_afu.sv +RTL_DIR = ../../../../rtl + +FAMILY = "Arria 10" +DEVICE = 10AX115N3F40E2SG +FPU_CORE_PATH = $(RTL_DIR)/fp_cores/altera/arria10 + +#FAMILY = "Stratix 10" +#DEVICE = 1SX280HN2F43E2VG +#FPU_CORE_PATH = $(RTL_DIR)/fp_cores/altera/stratix10 -RTL_DIR=../../../rtl FPU_INCLUDE = $(RTL_DIR)/fp_cores;$(FPU_CORE_PATH);$(RTL_DIR)/fp_cores/fpnew/src;$(RTL_DIR)/fp_cores/fpnew/src/fpu_div_sqrt_mvp/hdl;$(RTL_DIR)/fp_cores/fpnew/src/common_cells/include;$(RTL_DIR)/fp_cores/fpnew/src/common_cells/src -RTL_INCLUDE = $(RTL_DIR);$(RTL_DIR)/libs;$(RTL_DIR)/interfaces;$(RTL_DIR)/cache;../../../rtl/afu;../../../rtl/afu/ccip;$(FPU_INCLUDE) +RTL_INCLUDE = $(RTL_DIR);$(RTL_DIR)/libs;$(RTL_DIR)/interfaces;$(RTL_DIR)/cache;$(RTL_DIR)/afu;$(RTL_DIR)/afu/ccip;$(FPU_INCLUDE) PROJECT_FILES = $(PROJECT).qpf $(PROJECT).qsf @@ -58,7 +58,7 @@ smart.log: $(PROJECT_FILES) # Project initialization $(PROJECT_FILES): - quartus_sh -t ../project.tcl -project $(PROJECT) -family $(FAMILY) -device $(DEVICE) -top $(TOP_LEVEL_ENTITY) -src "$(SRC_FILE)" -sdc ../project.sdc -inc "$(RTL_INCLUDE)" -set "NOPAE" -set "NUM_CORES=4" -set "NUM_CLUSTERS=2" + quartus_sh -t ../../project.tcl -project $(PROJECT) -family $(FAMILY) -device $(DEVICE) -top $(TOP_LEVEL_ENTITY) -src "$(SRC_FILE)" -sdc ../../project.sdc -inc "$(RTL_INCLUDE)" -set "NOPAE" -set "NUM_CORES=4" -set "NUM_CLUSTERS=2" syn.chg: $(STAMP) syn.chg diff --git a/hw/syn/quartus/unittest/Makefile b/hw/syn/quartus/unittest/Makefile index 9644cf52..43d17d0f 100644 --- a/hw/syn/quartus/unittest/Makefile +++ b/hw/syn/quartus/unittest/Makefile @@ -1,13 +1,19 @@ PROJECT = Unittest TOP_LEVEL_ENTITY = VX_cache_core_req_bank_sel SRC_FILE = VX_cache_core_req_bank_sel.v -FPU_INCLUDE = ../../../rtl/fp_cores;../../../rtl/fp_cores/altera/arria10;../../../rtl/fp_cores/fpnew/src;../../../rtl/fp_cores/fpnew/src/fpu_div_sqrt_mvp/hdl;../../../rtl/fp_cores/fpnew/src/common_cells/include;../../../rtl/fp_cores/fpnew/src/common_cells/src -RTL_INCLUDE = $(FPU_INCLUDE);../../../rtl;../../../rtl/libs;../../../rtl/interfaces;../../../rtl/cache -PROJECT_FILES = $(PROJECT).qpf $(PROJECT).qsf +RTL_DIR = ../../../../rtl -# Part, Family FAMILY = "Arria 10" -DEVICE = 10AX115N3F40E2SG +DEVICE = 10AX115N3F40E2SG +FPU_CORE_PATH = $(RTL_DIR)/fp_cores/altera/arria10 + +#FAMILY = "Stratix 10" +#DEVICE = 1SX280HN2F43E2VG +#FPU_CORE_PATH = $(RTL_DIR)/fp_cores/altera/stratix10 + +FPU_INCLUDE = $(RTL_DIR)/fp_cores;$(FPU_CORE_PATH);$(RTL_DIR)/fp_cores/fpnew/src;$(RTL_DIR)/fp_cores/fpnew/src/fpu_div_sqrt_mvp/hdl;$(RTL_DIR)/fp_cores/fpnew/src/common_cells/include;$(RTL_DIR)/fp_cores/fpnew/src/common_cells/src +RTL_INCLUDE = $(FPU_INCLUDE);$(RTL_DIR);$(RTL_DIR)/libs;$(RTL_DIR)/interfaces;$(RTL_DIR)/cache +PROJECT_FILES = $(PROJECT).qpf $(PROJECT).qsf # Executable Configuration SYN_ARGS = --parallel --read_settings_files=on @@ -51,7 +57,7 @@ smart.log: $(PROJECT_FILES) # Project initialization $(PROJECT_FILES): - quartus_sh -t ../project.tcl -project $(PROJECT) -family $(FAMILY) -device $(DEVICE) -top $(TOP_LEVEL_ENTITY) -src "$(SRC_FILE)" -sdc ../project.sdc -inc "$(RTL_INCLUDE)" + quartus_sh -t ../../project.tcl -project $(PROJECT) -family $(FAMILY) -device $(DEVICE) -top $(TOP_LEVEL_ENTITY) -src "$(SRC_FILE)" -sdc ../../project.sdc -inc "$(RTL_INCLUDE)" syn.chg: $(STAMP) syn.chg diff --git a/hw/syn/quartus/vortex/Makefile b/hw/syn/quartus/vortex/Makefile index b2e90b31..48e40608 100644 --- a/hw/syn/quartus/vortex/Makefile +++ b/hw/syn/quartus/vortex/Makefile @@ -1,16 +1,16 @@ -FAMILY = "Arria 10" -DEVICE = 10AX115N3F40E2SG -FPU_CORE_PATH=../../../rtl/fp_cores/altera/arria10 - -#FAMILY = "Stratix 10" -#DEVICE = 1SX280HN2F43E2VG -#FPU_CORE_PATH=../../../rtl/fp_cores/altera/stratix10 - PROJECT = Vortex TOP_LEVEL_ENTITY = Vortex SRC_FILE = Vortex.sv +RTL_DIR = ../../../../rtl + +FAMILY = "Arria 10" +DEVICE = 10AX115N3F40E2SG +FPU_CORE_PATH = $(RTL_DIR)/fp_cores/altera/arria10 + +#FAMILY = "Stratix 10" +#DEVICE = 1SX280HN2F43E2VG +#FPU_CORE_PATH = $(RTL_DIR)/fp_cores/altera/stratix10 -RTL_DIR=../../../rtl FPU_INCLUDE = $(RTL_DIR)/fp_cores;$(FPU_CORE_PATH);$(RTL_DIR)/fp_cores/fpnew/src;$(RTL_DIR)/fp_cores/fpnew/src/fpu_div_sqrt_mvp/hdl;$(RTL_DIR)/fp_cores/fpnew/src/common_cells/include;$(RTL_DIR)/fp_cores/fpnew/src/common_cells/src RTL_INCLUDE = $(RTL_DIR);$(RTL_DIR)/libs;$(RTL_DIR)/interfaces;$(RTL_DIR)/cache;$(FPU_INCLUDE) @@ -58,7 +58,7 @@ smart.log: $(PROJECT_FILES) # Project initialization $(PROJECT_FILES): - quartus_sh -t ../project.tcl -project $(PROJECT) -family $(FAMILY) -device $(DEVICE) -top $(TOP_LEVEL_ENTITY) -src "$(SRC_FILE)" -sdc ../project.sdc -inc "$(RTL_INCLUDE)" + quartus_sh -t ../../project.tcl -project $(PROJECT) -family $(FAMILY) -device $(DEVICE) -top $(TOP_LEVEL_ENTITY) -src "$(SRC_FILE)" -sdc ../../project.sdc -inc "$(RTL_INCLUDE)" syn.chg: $(STAMP) syn.chg