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synthesis fixes

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This commit is contained in:
Blaise Tine
2020-03-05 07:03:23 -05:00
parent 369c2c625c 7222cdd199
commit 2ed98a4764
10 changed files with 256 additions and 32 deletions
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20
rtl/VX_cache/VX_cache_dram_req_arb.v
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@@ -15,6 +15,7 @@ module VX_cache_dram_req_arb (
input wire[`NUMBER_BANKS-1:0] per_bank_dram_wb_req,
input wire[`NUMBER_BANKS-1:0][31:0] per_bank_dram_wb_req_addr,
input wire[`NUMBER_BANKS-1:0][`BANK_LINE_SIZE_RNG][31:0] per_bank_dram_wb_req_data,
input wire[`NUMBER_BANKS-1:0] per_bank_dram_because_of_snp,
// real Dram request
output wire dram_req,
@@ -22,7 +23,8 @@ module VX_cache_dram_req_arb (
output wire dram_req_read,
output wire [31:0] dram_req_addr,
output wire [31:0] dram_req_size,
output wire [`BANK_LINE_SIZE_RNG][31:0] dram_req_data
output wire [`BANK_LINE_SIZE_RNG][31:0] dram_req_data,
output wire dram_req_because_of_wb
);
@@ -47,8 +49,9 @@ module VX_cache_dram_req_arb (
);
wire[`vx_clog2(`NUMBER_BANKS)-1:0] dwb_bank;
wire[`NUMBER_BANKS-1:0] use_wb_valid = per_bank_dram_wb_req | per_bank_dram_because_of_snp;
VX_generic_priority_encoder #(.N(`NUMBER_BANKS)) VX_sel_dwb(
.valids(per_bank_dram_wb_req),
.valids(use_wb_valid),
.index (dwb_bank),
.found (dwb_valid)
);
@@ -57,11 +60,12 @@ module VX_cache_dram_req_arb (
assign per_bank_dram_wb_queue_pop = per_bank_dram_wb_req & (~(1 << dwb_bank));
assign dram_req = dwb_valid || dfqq_req;
assign dram_req_write = dwb_valid;
assign dram_req_read = dfqq_req && !dwb_valid;
assign dram_req_addr = (dwb_valid ? per_bank_dram_wb_req_addr[dwb_bank] : dfqq_req_addr) & `BASE_ADDR_MASK;
assign dram_req_size = `BANK_LINE_SIZE_BYTES;
assign dram_req_data = dwb_valid ? per_bank_dram_wb_req_data[dwb_bank] : 0;
assign dram_req = dwb_valid || dfqq_req;
assign dram_req_write = dwb_valid;
assign dram_req_read = dfqq_req && !dwb_valid;
assign dram_req_addr = (dwb_valid ? per_bank_dram_wb_req_addr[dwb_bank] : dfqq_req_addr) & `BASE_ADDR_MASK;
assign dram_req_size = `BANK_LINE_SIZE_BYTES;
assign dram_req_data = dwb_valid ? per_bank_dram_wb_req_data[dwb_bank] : 0;
assign dram_req_because_of_wb = dwb_valid ? per_bank_dram_because_of_snp[dwb_bank] : 0;
endmodule