From 2eb19e23c2c85cd2a6b68ce9cc32e8bdeccca20b Mon Sep 17 00:00:00 2001 From: Blaise Tine Date: Mon, 30 Mar 2020 01:53:34 -0400 Subject: [PATCH] refactor RTL simulator --- driver/sw/rtlsim/Makefile | 2 +- driver/sw/rtlsim/vortex.cpp | 25 +- rtl/Makefile | 8 +- rtl/simulate/Vortex_SOC.cpp | 248 -------------- rtl/simulate/Vortex_SOC.h | 77 ----- rtl/simulate/multi_test_bench.cpp | 114 ------- rtl/simulate/ram.h | 364 ++++++++++----------- rtl/simulate/{Vortex.cpp => simulator.cpp} | 159 +++++++-- rtl/simulate/{Vortex.h => simulator.h} | 48 +-- rtl/simulate/test_bench.cpp | 9 +- 10 files changed, 340 insertions(+), 714 deletions(-) delete mode 100644 rtl/simulate/Vortex_SOC.cpp delete mode 100644 rtl/simulate/Vortex_SOC.h delete mode 100644 rtl/simulate/multi_test_bench.cpp rename rtl/simulate/{Vortex.cpp => simulator.cpp} (71%) rename rtl/simulate/{Vortex.h => simulator.h} (83%) diff --git a/driver/sw/rtlsim/Makefile b/driver/sw/rtlsim/Makefile index c64f1b12..1dc5e3f8 100644 --- a/driver/sw/rtlsim/Makefile +++ b/driver/sw/rtlsim/Makefile @@ -19,7 +19,7 @@ else RTL_TOP = Vortex endif -SRCS = vortex.cpp ../vx_utils.cpp ../../../rtl/simulate/$(RTL_TOP).cpp +SRCS = vortex.cpp ../vx_utils.cpp ../../../rtl/simulate/simulator.cpp RTL_INCLUDE = -I../../../rtl -I../../../rtl/interfaces -I../../../rtl/cache -I../../../rtl/VX_cache -I../../../rtl/shared_memory -I../../../rtl/pipe_regs -I../../../rtl/compat diff --git a/driver/sw/rtlsim/vortex.cpp b/driver/sw/rtlsim/vortex.cpp index 853fcebe..df816d87 100644 --- a/driver/sw/rtlsim/vortex.cpp +++ b/driver/sw/rtlsim/vortex.cpp @@ -9,12 +9,7 @@ #include #include - -#ifdef USE_MULTICORE -#include -#else -#include -#endif +#include #define PAGE_SIZE 4096 @@ -77,8 +72,8 @@ class vx_device { public: vx_device() : is_done_(false) - , vortex_(&ram_) { - vortex_.reset(); + , simulator_(&ram_) { + simulator_.reset(); thread_ = new std::thread(__thread_proc__, this); mem_allocation_ = vx_dev_caps(VX_CAPS_ALLOC_BASE_ADDR); } @@ -136,7 +131,7 @@ public: int flush_caches(size_t dev_maddr, size_t size) { mutex_.lock(); - vortex_.flush_caches(dev_maddr, size); + simulator_.flush_caches(dev_maddr, size); mutex_.unlock(); return 0; @@ -145,7 +140,7 @@ public: int start() { mutex_.lock(); - vortex_.reset(); + simulator_.reset(); mutex_.unlock(); return 0; @@ -155,7 +150,7 @@ public: auto timeout_sec = (timeout < 0) ? timeout : (timeout / 1000); for (;;) { mutex_.lock(); - bool is_busy = vortex_.is_busy(); + bool is_busy = simulator_.is_busy(); mutex_.unlock(); if (!is_busy || 0 == timeout_sec--) @@ -180,7 +175,7 @@ private: break; mutex_.lock(); - vortex_.step(); + simulator_.step(); mutex_.unlock(); } @@ -194,11 +189,7 @@ private: bool is_done_; size_t mem_allocation_; RAM ram_; -#ifdef USE_MULTICORE - Vortex_SOC vortex_; -#else - Vortex vortex_; -#endif + Simulator simulator_; std::thread* thread_; std::mutex mutex_; }; diff --git a/rtl/Makefile b/rtl/Makefile index d3ae30f5..99000f9b 100644 --- a/rtl/Makefile +++ b/rtl/Makefile @@ -6,9 +6,7 @@ SINGLE_CORE = Vortex.v MULTI_CORE = Vortex_SOC.v -EXE += --exe ./simulate/test_bench.cpp ./simulate/Vortex.cpp - -MULTI_EXE += --exe ./simulate/multi_test_bench.cpp ./simulate/Vortex_SOC.cpp +EXE += --exe ./simulate/test_bench.cpp ./simulate/simulator.cpp VF += -compiler gcc --language 1800-2009 @@ -48,13 +46,13 @@ VERILATORnoWarningsRel: build_config verilator $(VF) -cc $(SINGLE_CORE) $(INCLUDE) $(EXE) $(LIB) -CFLAGS '$(CF) -O3 -DVL_THREADED' $(WNO) --threads $(THREADS) VERILATORMULTInoWarnings: build_config - verilator $(VF) -cc $(MULTI_CORE) $(INCLUDE) $(MULTI_EXE) $(LIB) -CFLAGS '$(CF)' $(WNO) $(DEB) + verilator $(VF) -cc $(MULTI_CORE) $(INCLUDE) $(EXE) $(LIB) -CFLAGS '$(CF) -DUSE_MULTICORE' $(WNO) $(DEB) compdebug: build_config verilator_bin_dbg $(VF) -cc $(SINGLE_CORE) $(INCLUDE) $(EXE) $(LIB) -CFLAGS '$(CF) -DVCD_OUTPUT -DVL_DEBUG' $(WNO) $(DEB) compdebugmulti: build_config - verilator_bin_dbg $(VF) -cc $(MULTI_CORE) $(INCLUDE) $(MULTI_EXE) $(LIB) -CFLAGS '$(CF) -DVCD_OUTPUT -DVL_DEBUG' $(WNO) $(DEB) + verilator_bin_dbg $(VF) -cc $(MULTI_CORE) $(INCLUDE) $(EXE) $(LIB) -CFLAGS '$(CF) -DUSE_MULTICORE -DVCD_OUTPUT -DVL_DEBUG' $(WNO) $(DEB) RUNFILE: VERILATOR $(MAKECPP) diff --git a/rtl/simulate/Vortex_SOC.cpp b/rtl/simulate/Vortex_SOC.cpp deleted file mode 100644 index 8bfc94be..00000000 --- a/rtl/simulate/Vortex_SOC.cpp +++ /dev/null @@ -1,248 +0,0 @@ -#include "Vortex_SOC.h" - -unsigned long time_stamp = 0; - -double sc_time_stamp() { - return time_stamp / 1000.0; -} - -Vortex_SOC::Vortex_SOC(RAM *ram) - : start_pc(0), curr_cycle(0), stop(true), unit_test(true), stats_static_inst(0), stats_dynamic_inst(-1), - stats_total_cycles(0), stats_fwd_stalls(0), stats_branch_stalls(0), - debug_state(0), ibus_state(0), dbus_state(0), debug_return(0), - debug_wait_num(0), debug_inst_num(0), debug_end_wait(0), debug_debugAddr(0) { - this->ram = ram; - this->vortex = new VVortex_SOC; -#ifdef VCD_OUTPUT - Verilated::traceEverOn(true); - this->m_trace = new VerilatedVcdC; - this->vortex->trace(m_trace, 99); - this->m_trace->open("trace.vcd"); -#endif - this->results.open("../results.txt"); -} - -Vortex_SOC::~Vortex_SOC() { -#ifdef VCD_OUTPUT - m_trace->close(); -#endif - this->results.close(); - delete this->vortex; -} - -void Vortex_SOC::print_stats(bool cycle_test) { - - if (cycle_test) { - this->results << std::left; - // this->results << "# Static Instructions:\t" << std::dec << this->stats_static_inst << std::endl; - this->results << std::setw(24) << "# Dynamic Instructions:" << std::dec << this->stats_dynamic_inst << std::endl; - this->results << std::setw(24) << "# of total cycles:" << std::dec << this->stats_total_cycles << std::endl; - this->results << std::setw(24) << "# of forwarding stalls:" << std::dec << this->stats_fwd_stalls << std::endl; - this->results << std::setw(24) << "# of branch stalls:" << std::dec << this->stats_branch_stalls << std::endl; - this->results << std::setw(24) << "# CPI:" << std::dec << (double)this->stats_total_cycles / (double)this->stats_dynamic_inst << std::endl; - this->results << std::setw(24) << "# time to simulate: " << std::dec << this->stats_sim_time << " milliseconds" << std::endl; - } else { - this->results << std::left; - this->results << std::setw(24) << "# of total cycles:" << std::dec << this->stats_total_cycles << std::endl; - this->results << std::setw(24) << "# time to simulate: " << std::dec << this->stats_sim_time << " milliseconds" << std::endl; - } - - uint32_t status; - ram->getWord(0, &status); - - if (this->unit_test) { - if (status == 1) { - this->results << std::setw(24) << "# GRADE:" - << "PASSING\n"; - } else { - this->results << std::setw(24) << "# GRADE:" - << "Failed on test: " << status << "\n"; - } - } else { - this->results << std::setw(24) << "# GRADE:" - << "N/A [NOT A UNIT TEST]\n"; - } - - this->stats_static_inst = 0; - this->stats_dynamic_inst = -1; - this->stats_total_cycles = 0; - this->stats_fwd_stalls = 0; - this->stats_branch_stalls = 0; -} - -bool Vortex_SOC::ibus_driver() { - return false; -} - -void Vortex_SOC::io_handler() { - // std::cout << "Checking\n"; - for (int c = 0; c < vortex->number_cores; c++) { - if (vortex->io_valid[c]) { - uint32_t data_write = (uint32_t)vortex->io_data[c]; - // std::cout << "IO VALID!\n"; - char c = (char)data_write; - std::cerr << c; - // std::cout << c; - - std::cout << std::flush; - } - } -} - -bool Vortex_SOC::dbus_driver() { - // Iterate through each element, and get pop index - int dequeue_index = -1; - bool dequeue_valid = false; - for (int i = 0; i < this->dram_req_vec.size(); i++) { - if (this->dram_req_vec[i].cycles_left > 0) { - this->dram_req_vec[i].cycles_left -= 1; - } - - if ((this->dram_req_vec[i].cycles_left == 0) && (!dequeue_valid)) { - dequeue_index = i; - dequeue_valid = true; - } - } - - if (vortex->out_dram_req) { - if (vortex->out_dram_req_read) { - // Need to add an element - dram_req_t dram_req; - dram_req.cycles_left = vortex->out_dram_expected_lat; - dram_req.data_length = vortex->out_dram_req_size / 4; - dram_req.base_addr = vortex->out_dram_req_addr; - dram_req.data = (unsigned *)malloc(dram_req.data_length * sizeof(unsigned)); - - for (int i = 0; i < dram_req.data_length; i++) { - unsigned curr_addr = dram_req.base_addr + (i * 4); - unsigned data_rd; - ram->getWord(curr_addr, &data_rd); - dram_req.data[i] = data_rd; - } - // std::cout << "Fill Req -> Addr: " << std::hex << dram_req.base_addr << std::dec << "\n"; - this->dram_req_vec.push_back(dram_req); - } - - if (vortex->out_dram_req_write) { - unsigned base_addr = vortex->out_dram_req_addr; - unsigned data_length = vortex->out_dram_req_size / 4; - - for (int i = 0; i < data_length; i++) { - unsigned curr_addr = base_addr + (i * 4); - unsigned data_wr = vortex->out_dram_req_data[i]; - ram->writeWord(curr_addr, &data_wr); - } - } - } - - if (vortex->out_dram_fill_accept && dequeue_valid) { - vortex->out_dram_fill_rsp = 1; - vortex->out_dram_fill_rsp_addr = this->dram_req_vec[dequeue_index].base_addr; - // std::cout << "Fill Rsp -> Addr: " << std::hex << (this->dram_req_vec[dequeue_index].base_addr) << std::dec << "\n"; - - for (int i = 0; i < this->dram_req_vec[dequeue_index].data_length; i++) { - vortex->out_dram_fill_rsp_data[i] = this->dram_req_vec[dequeue_index].data[i]; - } - free(this->dram_req_vec[dequeue_index].data); - - this->dram_req_vec.erase(this->dram_req_vec.begin() + dequeue_index); - } else { - vortex->out_dram_fill_rsp = 0; - vortex->out_dram_fill_rsp_addr = 0; - } - - return false; -} - -void Vortex_SOC::reset() { - vortex->reset = 1; - this->step(); - vortex->reset = 0; -} - -void Vortex_SOC::step() { - vortex->clk = 0; - vortex->eval(); - -#ifdef VCD_OUTPUT - m_trace->dump(2 * this->stats_total_cycles + 0); -#endif - - vortex->clk = 1; - vortex->eval(); - - ibus_driver(); - dbus_driver(); - io_handler(); - -#ifdef VCD_OUTPUT - m_trace->dump(2 * this->stats_total_cycles + 1); -#endif - - ++time_stamp; - ++stats_total_cycles; -} - -void Vortex_SOC::wait(uint32_t cycles) { - for (int i = 0; i < cycles; ++i) { - this->step(); - } -} - -bool Vortex_SOC::is_busy() { - return (0 == vortex->out_ebreak); -} - -void Vortex_SOC::send_snoops(uint32_t mem_addr, uint32_t size) { - // align address to LLC block boundaries - auto aligned_addr_start = GLOBAL_BLOCK_SIZE_BYTES * (mem_addr / GLOBAL_BLOCK_SIZE_BYTES); - auto aligned_addr_end = GLOBAL_BLOCK_SIZE_BYTES * ((mem_addr + size + GLOBAL_BLOCK_SIZE_BYTES - 1) / GLOBAL_BLOCK_SIZE_BYTES); - - // submit snoop requests for the needed blocks - vortex->llc_snp_req_addr = aligned_addr_start; - vortex->llc_snp_req = false; - for (;;) { - this->step(); - if (vortex->llc_snp_req) { - vortex->llc_snp_req = false; - if (vortex->llc_snp_req_addr >= aligned_addr_end) - break; - vortex->llc_snp_req_addr += GLOBAL_BLOCK_SIZE_BYTES; - } - if (!vortex->llc_snp_req_delay) { - vortex->llc_snp_req = true; - } - } -} - -void Vortex_SOC::flush_caches(uint32_t mem_addr, uint32_t size) { - // send snoops for L1 flush - this->send_snoops(mem_addr, size); - -#if NUMBER_CORES != 1 - // send snoops for L2 flush - this->send_snoops(mem_addr, size); -#endif - - // wait 50 cycles to ensure that the request has committed - this->wait(50); -} - -bool Vortex_SOC::simulate() { - // reset the device - this->reset(); - - // execute program - while (!vortex->out_ebreak) { - this->step(); - } - - // wait 5 cycles to flush the pipeline - this->wait(5); - - std::cerr << "New Total Cycles: " << (this->stats_total_cycles) << "\n"; - - this->print_stats(); - - return false; -} \ No newline at end of file diff --git a/rtl/simulate/Vortex_SOC.h b/rtl/simulate/Vortex_SOC.h deleted file mode 100644 index 5ccbe044..00000000 --- a/rtl/simulate/Vortex_SOC.h +++ /dev/null @@ -1,77 +0,0 @@ -// C++ libraries -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "VX_define.h" -#include "ram.h" -#include "VVortex_SOC.h" -#include "verilated.h" - -#ifdef VCD_OUTPUT -#include -#endif - -typedef struct { - int cycles_left; - int data_length; - unsigned base_addr; - unsigned *data; -} dram_req_t; - -class Vortex_SOC { -public: - Vortex_SOC(RAM *ram); - ~Vortex_SOC(); - bool is_busy(); - void reset(); - void step(); - void flush_caches(uint32_t mem_addr, uint32_t size); - bool simulate(); -private: - void print_stats(bool cycle_test = true); - bool ibus_driver(); - bool dbus_driver(); - void io_handler(); - void send_snoops(uint32_t mem_addr, uint32_t size); - void wait(uint32_t cycles); - - RAM *ram; - - VVortex_SOC *vortex; - - unsigned start_pc; - bool refill_d; - unsigned refill_addr_d; - bool refill_i; - unsigned refill_addr_i; - long int curr_cycle; - bool stop; - bool unit_test; - std::ofstream results; - int stats_static_inst; - int stats_dynamic_inst; - int stats_total_cycles; - int stats_fwd_stalls; - int stats_branch_stalls; - int debug_state; - int ibus_state; - int dbus_state; - int debug_return; - int debug_wait_num; - int debug_inst_num; - int debug_end_wait; - int debug_debugAddr; - double stats_sim_time; - std::vector dram_req_vec; -#ifdef VCD_OUTPUT - VerilatedVcdC *m_trace; -#endif -}; diff --git a/rtl/simulate/multi_test_bench.cpp b/rtl/simulate/multi_test_bench.cpp deleted file mode 100644 index 7c213f42..00000000 --- a/rtl/simulate/multi_test_bench.cpp +++ /dev/null @@ -1,114 +0,0 @@ -#include "Vortex_SOC.h" - -#define NUM_TESTS 46 - -int main(int argc, char **argv) -{ - - Verilated::commandArgs(argc, argv); - -// #define ALL_TESTS -#ifdef ALL_TESTS - bool passed = true; - std::string tests[NUM_TESTS] = { - "../../emulator/riscv_tests/rv32ui-p-add.hex", - "../../emulator/riscv_tests/rv32ui-p-addi.hex", - "../../emulator/riscv_tests/rv32ui-p-and.hex", - "../../emulator/riscv_tests/rv32ui-p-andi.hex", - "../../emulator/riscv_tests/rv32ui-p-auipc.hex", - "../../emulator/riscv_tests/rv32ui-p-beq.hex", - "../../emulator/riscv_tests/rv32ui-p-bge.hex", - "../../emulator/riscv_tests/rv32ui-p-bgeu.hex", - "../../emulator/riscv_tests/rv32ui-p-blt.hex", - "../../emulator/riscv_tests/rv32ui-p-bltu.hex", - "../../emulator/riscv_tests/rv32ui-p-bne.hex", - "../../emulator/riscv_tests/rv32ui-p-jal.hex", - "../../emulator/riscv_tests/rv32ui-p-jalr.hex", - "../../emulator/riscv_tests/rv32ui-p-lw.hex", - "../../emulator/riscv_tests/rv32ui-p-lb.hex", - "../../emulator/riscv_tests/rv32ui-p-lbu.hex", - "../../emulator/riscv_tests/rv32ui-p-lh.hex", - "../../emulator/riscv_tests/rv32ui-p-lhu.hex", - "../../emulator/riscv_tests/rv32ui-p-lui.hex", - "../../emulator/riscv_tests/rv32ui-p-or.hex", - "../../emulator/riscv_tests/rv32ui-p-ori.hex", - "../../emulator/riscv_tests/rv32ui-p-sb.hex", - "../../emulator/riscv_tests/rv32ui-p-sh.hex", - "../../emulator/riscv_tests/rv32ui-p-simple.hex", - "../../emulator/riscv_tests/rv32ui-p-sll.hex", - "../../emulator/riscv_tests/rv32ui-p-slli.hex", - "../../emulator/riscv_tests/rv32ui-p-slt.hex", - "../../emulator/riscv_tests/rv32ui-p-slti.hex", - "../../emulator/riscv_tests/rv32ui-p-sltiu.hex", - "../../emulator/riscv_tests/rv32ui-p-sltu.hex", - "../../emulator/riscv_tests/rv32ui-p-sra.hex", - "../../emulator/riscv_tests/rv32ui-p-srai.hex", - "../../emulator/riscv_tests/rv32ui-p-srl.hex", - "../../emulator/riscv_tests/rv32ui-p-srli.hex", - "../../emulator/riscv_tests/rv32ui-p-sub.hex", - "../../emulator/riscv_tests/rv32ui-p-sw.hex", - "../../emulator/riscv_tests/rv32ui-p-xor.hex", - "../../emulator/riscv_tests/rv32ui-p-xori.hex", - "../../emulator/riscv_tests/rv32um-p-div.hex", - "../../emulator/riscv_tests/rv32um-p-divu.hex", - "../../emulator/riscv_tests/rv32um-p-mul.hex", - "../../emulator/riscv_tests/rv32um-p-mulh.hex", - "../../emulator/riscv_tests/rv32um-p-mulhsu.hex", - "../../emulator/riscv_tests/rv32um-p-mulhu.hex", - "../../emulator/riscv_tests/rv32um-p-rem.hex", - "../../emulator/riscv_tests/rv32um-p-remu.hex" - }; - - for (std::string s : tests) { - std::cerr << DEFAULT << "\n---------------------------------------\n"; - - std::cerr << s << std::endl; - - RAM ram; - loadHexImpl(s.c_str(), &ram); - - Vortex_SOC v(&ram); - bool curr = v.simulate(); - - if ( curr) std::cerr << GREEN << "Test Passed: " << s << std::endl; - if (!curr) std::cerr << RED << "Test Failed: " << s << std::endl; - std::cerr << DEFAULT; - passed = passed && curr; - } - - std::cerr << DEFAULT << "\n***************************************\n"; - - if( passed) std::cerr << DEFAULT << "PASSED ALL TESTS\n"; - if(!passed) std::cerr << DEFAULT << "Failed one or more tests\n"; - - return !passed; - - #else - - char testing[] = "../../runtime/mains/simple/vx_simple_main.hex"; - // char testing[] = "../../emulator/riscv_tests/rv32ui-p-lw.hex"; - // char testing[] = "../../emulator/riscv_tests/rv32ui-p-sw.hex"; - - // const char *testing; - - // if (argc >= 2) { - // testing = argv[1]; - // } else { - // testing = "../../kernel/vortex_test.hex"; - // } - - std::cerr << testing << std::endl; - - RAM ram; - loadHexImpl(testing, &ram); - - Vortex_SOC v(&ram); - bool curr = v.simulate(); - - if ( curr) std::cerr << GREEN << "Test Passed: " << testing << std::endl; - if (!curr) std::cerr << RED << "Test Failed: " << testing << std::endl; - - return !curr; - -#endif -} \ No newline at end of file diff --git a/rtl/simulate/ram.h b/rtl/simulate/ram.h index 39fb011e..ddeb0487 100644 --- a/rtl/simulate/ram.h +++ b/rtl/simulate/ram.h @@ -1,248 +1,212 @@ -#ifndef __RAM__ -#define __RAM__ +#pragma once -// #include "string.h" #include #include -// #include - -// #define NULL 0 class RAM; uint32_t hti(char); uint32_t hToI(const char *, uint32_t); -void loadHexImpl(const char *,RAM*); +void loadHexImpl(const char *, RAM *); -class RAM{ +class RAM { public: - uint8_t* mem[1 << 12]; + uint8_t *mem[1 << 12]; - RAM(){ - for(uint32_t i = 0;i < (1 << 12);i++) mem[i] = NULL; + RAM() { + for (uint32_t i = 0; i < (1 << 12); i++) + mem[i] = NULL; + } + ~RAM() { + for (uint32_t i = 0; i < (1 << 12); i++) + if (mem[i]) + delete[] mem[i]; + } + + size_t size() const { + return (1ull << 32); + } + + void clear() { + for (uint32_t i = 0; i < (1 << 12); i++) { + if (mem[i]) { + delete mem[i]; + mem[i] = NULL; + } } - ~RAM(){ - for(uint32_t i = 0;i < (1 << 12);i++) if(mem[i]) delete [] mem[i]; + } + + uint8_t *get(uint32_t address) { + + if (mem[address >> 20] == NULL) { + uint8_t *ptr = new uint8_t[1024 * 1024]; + for (uint32_t i = 0; i < 1024 * 1024; i += 4) { + ptr[i + 0] = 0x00; + ptr[i + 1] = 0x00; + ptr[i + 2] = 0x00; + ptr[i + 3] = 0x00; + } + mem[address >> 20] = ptr; } + return &mem[address >> 20][address & 0xFFFFF]; + } - size_t size() const { - return (1ull << 32); + void read(uint32_t address, uint32_t length, uint8_t *data) { + for (unsigned i = 0; i < length; i++) { + data[i] = (*this)[address + i]; } + } - void clear(){ - for(uint32_t i = 0;i < (1 << 12);i++) - { - if(mem[i]) - { - delete mem[i]; - mem[i] = NULL; - } - } + void write(uint32_t address, uint32_t length, uint8_t *data) { + for (unsigned i = 0; i < length; i++) { + (*this)[address + i] = data[i]; } + } - uint8_t* get(uint32_t address){ + void getBlock(uint32_t address, uint8_t *data) { + uint32_t block_number = address & 0xffffff00; // To zero out block offset + uint32_t bytes_num = 256; - if(mem[address >> 20] == NULL) { - uint8_t* ptr = new uint8_t[1024*1024]; - for(uint32_t i = 0;i < 1024*1024;i+=4) { - ptr[i + 0] = 0x00; - ptr[i + 1] = 0x00; - ptr[i + 2] = 0x00; - ptr[i + 3] = 0x00; - } - mem[address >> 20] = ptr; - } - return &mem[address >> 20][address & 0xFFFFF]; + this->read(block_number, bytes_num, data); + } + + void getWord(uint32_t address, uint32_t *data) { + data[0] = 0; + + uint8_t first = *get(address + 0); + uint8_t second = *get(address + 1); + uint8_t third = *get(address + 2); + uint8_t fourth = *get(address + 3); + + data[0] = (data[0] << 0) | fourth; + data[0] = (data[0] << 8) | third; + data[0] = (data[0] << 8) | second; + data[0] = (data[0] << 8) | first; + } + + void writeWord(uint32_t address, uint32_t *data) { + uint32_t data_to_write = *data; + + uint32_t byte_mask = 0xFF; + + for (int i = 0; i < 4; i++) { + (*this)[address + i] = data_to_write & byte_mask; + data_to_write = data_to_write >> 8; } + } - void read(uint32_t address,uint32_t length, uint8_t *data){ - for(unsigned i = 0;i < length;i++){ - data[i] = (*this)[address + i]; - } + void writeHalf(uint32_t address, uint32_t *data) { + uint32_t data_to_write = *data; + + uint32_t byte_mask = 0xFF; + + for (int i = 0; i < 2; i++) { + (*this)[address + i] = data_to_write & byte_mask; + data_to_write = data_to_write >> 8; } + } - void write(uint32_t address,uint32_t length, uint8_t *data){ - for(unsigned i = 0;i < length;i++){ - (*this)[address + i] = data[i]; - } - } + void writeByte(uint32_t address, uint32_t *data) { + uint32_t data_to_write = *data; - void getBlock(uint32_t address, uint8_t *data) - { - uint32_t block_number = address & 0xffffff00; // To zero out block offset - uint32_t bytes_num = 256; + uint32_t byte_mask = 0xFF; - this->read(block_number, bytes_num, data); - } - - void getWord(uint32_t address, uint32_t * data) - { - data[0] = 0; - - uint8_t first = *get(address + 0); - uint8_t second = *get(address + 1); - uint8_t third = *get(address + 2); - uint8_t fourth = *get(address + 3); - - // uint8_t hi = (uint8_t) *get(address + 0); - // std::cout << "RAM: READING ADDRESS " << address + 0 << " DATA: " << hi << "\n"; - // hi = (uint8_t) *get(address + 1); - // std::cout << "RAM: READING ADDRESS " << address + 1 << " DATA: " << hi << "\n"; - // hi = (uint8_t) *get(address + 2); - // std::cout << "RAM: READING ADDRESS " << address + 2 << " DATA: " << hi << "\n"; - // hi = (uint8_t) *get(address + 3); - // std::cout << "RAM: READING ADDRESS " << address + 3 << " DATA: " << hi << "\n"; - - data[0] = (data[0] << 0) | fourth; - data[0] = (data[0] << 8) | third; - data[0] = (data[0] << 8) | second; - data[0] = (data[0] << 8) | first; - - } - - void writeWord(uint32_t address, uint32_t * data) - { - uint32_t data_to_write = *data; - - uint32_t byte_mask = 0xFF; - - for (int i = 0; i < 4; i++) - { - // std::cout << "RAM: DATA TO WRITE " << data_to_write << "\n"; - // std::cout << "RAM: DATA TO MASK " << byte_mask << "\n"; - // std::cout << "RAM: WRITING ADDRESS " << address + i << " DATA: " << (data_to_write & byte_mask) << "\n"; - (*this)[address + i] = data_to_write & byte_mask; - data_to_write = data_to_write >> 8; - } - } - - void writeHalf(uint32_t address, uint32_t * data) - { - uint32_t data_to_write = *data; - - uint32_t byte_mask = 0xFF; - - for (int i = 0; i < 2; i++) - { - // std::cout << "RAM: DATA TO WRITE " << data_to_write << "\n"; - // std::cout << "RAM: DATA TO MASK " << byte_mask << "\n"; - // std::cout << "RAM: WRITING ADDRESS " << address + i << " DATA: " << (data_to_write & byte_mask) << "\n"; - (*this)[address + i] = data_to_write & byte_mask; - data_to_write = data_to_write >> 8; - } - } - - void writeByte(uint32_t address, uint32_t * data) - { - uint32_t data_to_write = *data; - - uint32_t byte_mask = 0xFF; - - (*this)[address] = data_to_write & byte_mask; - data_to_write = data_to_write >> 8; - - } - - uint8_t& operator [](uint32_t address) { - return *get(address); - } + (*this)[address] = data_to_write & byte_mask; + data_to_write = data_to_write >> 8; + } + uint8_t &operator[](uint32_t address) { + return *get(address); + } }; - // MEMORY UTILS inline uint32_t hti(char c) { - if (c >= 'A' && c <= 'F') - return c - 'A' + 10; - if (c >= 'a' && c <= 'f') - return c - 'a' + 10; - return c - '0'; + if (c >= 'A' && c <= 'F') + return c - 'A' + 10; + if (c >= 'a' && c <= 'f') + return c - 'a' + 10; + return c - '0'; } inline uint32_t hToI(const char *c, uint32_t size) { - uint32_t value = 0; - for (uint32_t i = 0; i < size; i++) { - value += hti(c[i]) << ((size - i - 1) * 4); - } - return value; + uint32_t value = 0; + for (uint32_t i = 0; i < size; i++) { + value += hti(c[i]) << ((size - i - 1) * 4); + } + return value; } +inline void loadHexImpl(const char *path, RAM *mem) { + mem->clear(); + FILE *fp = fopen(path, "r"); + if (fp == 0) { + printf("Path not found %s\n", path); + return; + // std::cout << path << " not found" << std::endl; + } + //Preload 0x0 <-> 0x80000000 jumps + ((uint32_t *)mem->get(0))[1] = 0xf1401073; + ((uint32_t *)mem->get(0))[2] = 0x30101073; -inline void loadHexImpl(const char *path, RAM* mem) { - mem->clear(); - FILE *fp = fopen(path, "r"); - if(fp == 0){ - printf("Path not found %s\n", path); - return; - // std::cout << path << " not found" << std::endl; - } - //Preload 0x0 <-> 0x80000000 jumps - ((uint32_t*)mem->get(0))[1] = 0xf1401073; + ((uint32_t *)mem->get(0))[3] = 0x800000b7; + ((uint32_t *)mem->get(0))[4] = 0x000080e7; - ((uint32_t*)mem->get(0))[2] = 0x30101073; + ((uint32_t *)mem->get(0x80000000))[0] = 0x00000097; - ((uint32_t*)mem->get(0))[3] = 0x800000b7; - ((uint32_t*)mem->get(0))[4] = 0x000080e7; - - ((uint32_t*)mem->get(0x80000000))[0] = 0x00000097; + ((uint32_t *)mem->get(0xb0000000))[0] = 0x01C02023; + // F00FFF10 + ((uint32_t *)mem->get(0xf00fff10))[0] = 0x12345678; - ((uint32_t*)mem->get(0xb0000000))[0] = 0x01C02023; - // F00FFF10 - ((uint32_t*)mem->get(0xf00fff10))[0] = 0x12345678; + fseek(fp, 0, SEEK_END); + uint32_t size = ftell(fp); + fseek(fp, 0, SEEK_SET); + char *content = new char[size]; + fread(content, 1, size, fp); + int offset = 0; + char *line = content; + // std::cout << "WHTA\n"; + while (1) { + if (line[0] == ':') { + uint32_t byteCount = hToI(line + 1, 2); + uint32_t nextAddr = hToI(line + 3, 4) + offset; + uint32_t key = hToI(line + 7, 2); + switch (key) { + case 0: + for (uint32_t i = 0; i < byteCount; i++) { - + unsigned add = nextAddr + i; - fseek(fp, 0, SEEK_END); - uint32_t size = ftell(fp); - fseek(fp, 0, SEEK_SET); - char* content = new char[size]; - fread(content, 1, size, fp); - - int offset = 0; - char* line = content; - // std::cout << "WHTA\n"; - while (1) { - if (line[0] == ':') { - uint32_t byteCount = hToI(line + 1, 2); - uint32_t nextAddr = hToI(line + 3, 4) + offset; - uint32_t key = hToI(line + 7, 2); - switch (key) { - case 0: - for (uint32_t i = 0; i < byteCount; i++) { - - unsigned add = nextAddr + i; - - *(mem->get(add)) = hToI(line + 9 + i * 2, 2); - } - break; - case 2: -// cout << offset << endl; - offset = hToI(line + 9, 4) << 4; - break; - case 4: -// cout << offset << endl; - offset = hToI(line + 9, 4) << 16; - break; - default: -// cout << "??? " << key << endl; - break; - } + *(mem->get(add)) = hToI(line + 9 + i * 2, 2); } - - while (*line != '\n' && size != 0) { - line++; - size--; - } - if (size <= 1) - break; - line++; - size--; + break; + case 2: + // cout << offset << endl; + offset = hToI(line + 9, 4) << 4; + break; + case 4: + // cout << offset << endl; + offset = hToI(line + 9, 4) << 16; + break; + default: + // cout << "??? " << key << endl; + break; + } } - if (content) delete[] content; -} + while (*line != '\n' && size != 0) { + line++; + size--; + } + if (size <= 1) + break; + line++; + size--; + } -#endif \ No newline at end of file + if (content) + delete[] content; +} \ No newline at end of file diff --git a/rtl/simulate/Vortex.cpp b/rtl/simulate/simulator.cpp similarity index 71% rename from rtl/simulate/Vortex.cpp rename to rtl/simulate/simulator.cpp index 7de2504e..fbf063af 100644 --- a/rtl/simulate/Vortex.cpp +++ b/rtl/simulate/simulator.cpp @@ -1,4 +1,6 @@ -#include "Vortex.h" +#include "simulator.h" +#include +#include unsigned long time_stamp = 0; @@ -6,23 +8,31 @@ double sc_time_stamp() { return time_stamp / 1000.0; } -Vortex::Vortex(RAM *ram) +Simulator::Simulator(RAM *ram) : start_pc(0), curr_cycle(0), stop(true), unit_test(true), stats_static_inst(0), stats_dynamic_inst(-1), stats_total_cycles(0), stats_fwd_stalls(0), stats_branch_stalls(0), debug_state(0), ibus_state(0), dbus_state(0), debug_return(0), debug_wait_num(0), debug_inst_num(0), debug_end_wait(0), debug_debugAddr(0) { + this->ram = ram; - this->vortex = new VVortex; + +#ifdef USE_MULTICORE + this->vortex = new VVortex_SOC(); +#else + this->vortex = new VVortex(); +#endif + #ifdef VCD_OUTPUT Verilated::traceEverOn(true); this->m_trace = new VerilatedVcdC; this->vortex->trace(m_trace, 99); this->m_trace->open("trace.vcd"); #endif + this->results.open("../results.txt"); } -Vortex::~Vortex() { +Simulator::~Simulator() { #ifdef VCD_OUTPUT m_trace->close(); #endif @@ -30,7 +40,7 @@ Vortex::~Vortex() { delete this->vortex; } -void Vortex::print_stats(bool cycle_test) { +void Simulator::print_stats(bool cycle_test) { if (cycle_test) { this->results << std::left; // this->results << "# Static Instructions:\t" << std::dec << this->stats_static_inst << std::endl; @@ -69,7 +79,9 @@ void Vortex::print_stats(bool cycle_test) { this->stats_branch_stalls = 0; } -bool Vortex::ibus_driver() { +#ifndef USE_MULTICORE + +bool Simulator::ibus_driver() { // Iterate through each element, and get pop index int dequeue_index = -1; bool dequeue_valid = false; @@ -138,20 +150,9 @@ bool Vortex::ibus_driver() { return false; } -void Vortex::io_handler() { - // std::cout << "Checking\n"; - if (vortex->io_valid) { - uint32_t data_write = (uint32_t)vortex->io_data; - // std::cout << "IO VALID!\n"; - char c = (char)data_write; - std::cerr << c; - // std::cout << c; +#endif - std::cout << std::flush; - } -} - -bool Vortex::dbus_driver() { +bool Simulator::dbus_driver() { // Iterate through each element, and get pop index int dequeue_index = -1; bool dequeue_valid = false; @@ -166,6 +167,57 @@ bool Vortex::dbus_driver() { } } +#ifdef USE_MULTICORE + + if (vortex->out_dram_req) { + if (vortex->out_dram_req_read) { + // Need to add an element + dram_req_t dram_req; + dram_req.cycles_left = vortex->out_dram_expected_lat; + dram_req.data_length = vortex->out_dram_req_size / 4; + dram_req.base_addr = vortex->out_dram_req_addr; + dram_req.data = (unsigned *)malloc(dram_req.data_length * sizeof(unsigned)); + + for (int i = 0; i < dram_req.data_length; i++) { + unsigned curr_addr = dram_req.base_addr + (i * 4); + unsigned data_rd; + ram->getWord(curr_addr, &data_rd); + dram_req.data[i] = data_rd; + } + // std::cout << "Fill Req -> Addr: " << std::hex << dram_req.base_addr << std::dec << "\n"; + this->dram_req_vec.push_back(dram_req); + } + + if (vortex->out_dram_req_write) { + unsigned base_addr = vortex->out_dram_req_addr; + unsigned data_length = vortex->out_dram_req_size / 4; + + for (int i = 0; i < data_length; i++) { + unsigned curr_addr = base_addr + (i * 4); + unsigned data_wr = vortex->out_dram_req_data[i]; + ram->writeWord(curr_addr, &data_wr); + } + } + } + + if (vortex->out_dram_fill_accept && dequeue_valid) { + vortex->out_dram_fill_rsp = 1; + vortex->out_dram_fill_rsp_addr = this->dram_req_vec[dequeue_index].base_addr; + // std::cout << "Fill Rsp -> Addr: " << std::hex << (this->dram_req_vec[dequeue_index].base_addr) << std::dec << "\n"; + + for (int i = 0; i < this->dram_req_vec[dequeue_index].data_length; i++) { + vortex->out_dram_fill_rsp_data[i] = this->dram_req_vec[dequeue_index].data[i]; + } + free(this->dram_req_vec[dequeue_index].data); + + this->dram_req_vec.erase(this->dram_req_vec.begin() + dequeue_index); + } else { + vortex->out_dram_fill_rsp = 0; + vortex->out_dram_fill_rsp_addr = 0; + } + +#else + if (vortex->dram_req) { if (vortex->dram_req_read) { // Need to add an element @@ -212,17 +264,43 @@ bool Vortex::dbus_driver() { vortex->dram_fill_rsp = 0; vortex->dram_fill_rsp_addr = 0; } + +#endif return false; } -void Vortex::reset() { +void Simulator::io_handler() { +#ifdef USE_MULTICORE + bool io_valid = false; + for (int c = 0; c < vortex->number_cores; c++) { + if (vortex->io_valid[c]) { + uint32_t data_write = (uint32_t)vortex->io_data[c]; + char c = (char)data_write; + std::cerr << c; + io_valid = true; + } + } + if (io_valid) { + std::cout << std::flush; + } +#else + if (vortex->io_valid) { + uint32_t data_write = (uint32_t)vortex->io_data; + char c = (char)data_write; + std::cerr << c; + std::cout << std::flush; + } +#endif +} + +void Simulator::reset() { vortex->reset = 1; this->step(); vortex->reset = 0; } -void Vortex::step() { +void Simulator::step() { vortex->clk = 0; vortex->eval(); @@ -233,7 +311,10 @@ void Vortex::step() { vortex->clk = 1; vortex->eval(); +#ifndef USE_MULTICORE ibus_driver(); +#endif + dbus_driver(); io_handler(); @@ -245,21 +326,38 @@ void Vortex::step() { ++stats_total_cycles; } -void Vortex::wait(uint32_t cycles) { +void Simulator::wait(uint32_t cycles) { for (int i = 0; i < cycles; ++i) { this->step(); } } -bool Vortex::is_busy() { +bool Simulator::is_busy() { return (0 == vortex->out_ebreak); } -void Vortex::send_snoops(uint32_t mem_addr, uint32_t size) { +void Simulator::send_snoops(uint32_t mem_addr, uint32_t size) { // align address to LLC block boundaries auto aligned_addr_start = GLOBAL_BLOCK_SIZE_BYTES * (mem_addr / GLOBAL_BLOCK_SIZE_BYTES); auto aligned_addr_end = GLOBAL_BLOCK_SIZE_BYTES * ((mem_addr + size + GLOBAL_BLOCK_SIZE_BYTES - 1) / GLOBAL_BLOCK_SIZE_BYTES); +#ifdef USE_MULTICORE + // submit snoop requests for the needed blocks + vortex->llc_snp_req_addr = aligned_addr_start; + vortex->llc_snp_req = false; + for (;;) { + this->step(); + if (vortex->llc_snp_req) { + vortex->llc_snp_req = false; + if (vortex->llc_snp_req_addr >= aligned_addr_end) + break; + vortex->llc_snp_req_addr += GLOBAL_BLOCK_SIZE_BYTES; + } + if (!vortex->llc_snp_req_delay) { + vortex->llc_snp_req = true; + } + } +#else // submit snoop requests for the needed blocks vortex->snp_req_addr = aligned_addr_start; vortex->snp_req = false; @@ -275,9 +373,10 @@ void Vortex::send_snoops(uint32_t mem_addr, uint32_t size) { vortex->snp_req = true; } } +#endif } -void Vortex::flush_caches(uint32_t mem_addr, uint32_t size) { +void Simulator::flush_caches(uint32_t mem_addr, uint32_t size) { // send snoops for L1 flush this->send_snoops(mem_addr, size); @@ -286,11 +385,11 @@ void Vortex::flush_caches(uint32_t mem_addr, uint32_t size) { this->send_snoops(mem_addr, size); #endif - // wait 50 cycles to ensure that the request has committed - this->wait(50); + // wait 300 cycles to ensure that the request has committed + this->wait(300); } -bool Vortex::simulate() { +bool Simulator::run() { // reset the device this->reset(); @@ -306,8 +405,12 @@ bool Vortex::simulate() { this->print_stats(); +#ifdef USE_MULTICORE + int status = 0; +#else // check riscv-tests PASSED/FAILED status int status = (unsigned int) vortex->Vortex->vx_back_end->VX_wb->last_data_wb & 0xf; +#endif return (status == 1); } \ No newline at end of file diff --git a/rtl/simulate/Vortex.h b/rtl/simulate/simulator.h similarity index 83% rename from rtl/simulate/Vortex.h rename to rtl/simulate/simulator.h index a8cd9b0a..fc734115 100644 --- a/rtl/simulate/Vortex.h +++ b/rtl/simulate/simulator.h @@ -1,18 +1,10 @@ -// C++ libraries -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include +#pragma once -#include "VX_define.h" -#include "ram.h" +#ifdef USE_MULTICORE +#include "VVortex_SOC.h" +#else #include "VVortex.h" +#endif #include "VVortex__Syms.h" #include "verilated.h" @@ -20,6 +12,12 @@ #include #endif +#include "VX_define.h" +#include "ram.h" + +#include +#include + typedef struct { int cycles_left; int data_length; @@ -27,19 +25,26 @@ typedef struct { unsigned *data; } dram_req_t; -class Vortex { +class Simulator { public: - Vortex(RAM *ram); - ~Vortex(); + + Simulator(RAM *ram); + virtual ~Simulator(); + bool is_busy(); void reset(); void step(); void flush_caches(uint32_t mem_addr, uint32_t size); - bool simulate(); + bool run(); + +protected: -private: void print_stats(bool cycle_test = true); + +#ifndef USE_MULTICORE bool ibus_driver(); +#endif + bool dbus_driver(); void io_handler(); void send_snoops(uint32_t mem_addr, uint32_t size); @@ -47,8 +52,6 @@ private: RAM *ram; - VVortex *vortex; - unsigned start_pc; bool refill_d; unsigned refill_addr_d; @@ -74,6 +77,11 @@ private: double stats_sim_time; std::vector dram_req_vec; std::vector I_dram_req_vec; +#ifdef USE_MULTICORE + VVortex_SOC *vortex; +#else + VVortex *vortex; +#endif #ifdef VCD_OUTPUT VerilatedVcdC *m_trace; #endif diff --git a/rtl/simulate/test_bench.cpp b/rtl/simulate/test_bench.cpp index b6792d4e..b5e57740 100644 --- a/rtl/simulate/test_bench.cpp +++ b/rtl/simulate/test_bench.cpp @@ -1,4 +1,5 @@ -#include "Vortex.h" +#include "simulator.h" +#include #define NUM_TESTS 46 @@ -70,7 +71,7 @@ int main(int argc, char **argv) RAM ram; loadHexImpl(s.c_str(), &ram); - Vortex v(&ram); + Simulator v(&ram); bool curr = v.simulate(); if ( curr) std::cerr << GREEN << "Test Passed: " << s << std::endl; @@ -105,8 +106,8 @@ int main(int argc, char **argv) RAM ram; loadHexImpl(testing, &ram); - Vortex v(&ram); - bool curr = v.simulate(); + Simulator simulator(&ram); + bool curr = simulator.run(); if ( curr) std::cerr << GREEN << "Test Passed: " << testing << std::endl; if (!curr) std::cerr << RED << "Test Failed: " << testing << std::endl;