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get device caps from CSRs

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This commit is contained in:
Blaise Tine
2020-06-30 00:08:23 -07:00
parent f66c251309
commit 2de61b5982
13 changed files with 534 additions and 275 deletions
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46
hw/rtl/VX_config.vh
View File

@@ -59,21 +59,33 @@
`define L3_ENABLE (`NUM_CLUSTERS > 1)
`endif
`define CSR_LTID 12'h020
`define CSR_LWID 12'h021
`define CSR_GTID 12'hF14 // reserved Hardware Thread ID (mhartid)
`define CSR_GWID 12'h023
`define CSR_GCID 12'h024
`define CSR_NT 12'h025
`define CSR_NW 12'h026
`define CSR_NC 12'h027
// Configuration Values =======================================================
`define CSR_CYCLL 12'hC00
`define CSR_CYCLH 12'hC80
`define CSR_INSTL 12'hC02
`define CSR_INSTH 12'hC82
`define VENDOR_ID 0
`define ARCHITECTURE_ID 0
`define IMPLEMENTATION_ID 0
// ========================= Dcache Configurable Knobs ========================
// CSR Addresses ==============================================================
`define CSR_VEND_ID 12'hF11
`define CSR_ARCH_ID 12'hF12
`define CSR_IMPL_ID 12'hF13
`define CSR_GTID 12'hF14
`define CSR_LTID 12'h020
`define CSR_LWID 12'h021
`define CSR_GWID 12'h023
`define CSR_GCID 12'h024
`define CSR_NT 12'h025
`define CSR_NW 12'h026
`define CSR_NC 12'h027
`define CSR_CYCLE_L 12'hC00
`define CSR_CYCLE_H 12'hC80
`define CSR_INSTR_L 12'hC02
`define CSR_INSTR_H 12'hC82
// Dcache Configurable Knobs ==================================================
// Size of cache in bytes
`ifndef DCACHE_SIZE
@@ -144,7 +156,7 @@
`define DPRFQ_STRIDE 0
`endif
// ========================== Icache Configurable Knobs =======================
// Icache Configurable Knobs ==================================================
// Size of cache in bytes
`ifndef ICACHE_SIZE
@@ -210,7 +222,7 @@
`define IPRFQ_STRIDE 0
`endif
// =========================== SM Configurable Knobs ==========================
// SM Configurable Knobs ======================================================
// Size of cache in bytes
`ifndef SCACHE_SIZE
@@ -247,7 +259,7 @@
`define SCWBQ_SIZE `SCREQ_SIZE
`endif
// ======================== L2cache Configurable Knobs ========================
// L2cache Configurable Knobs =================================================
// Size of cache in bytes
`ifndef L2CACHE_SIZE
@@ -318,7 +330,7 @@
`define L2PRFQ_STRIDE 0
`endif
// ======================== L3cache Configurable Knobs ========================
// L3cache Configurable Knobs =================================================
// Size of cache in bytes
`ifndef L3CACHE_SIZE

27
hw/rtl/VX_csr_data.v
View File

@@ -43,18 +43,21 @@ module VX_csr_data #(
always @(*) begin
case (read_addr)
`CSR_LWID : read_data = 32'(warp_num);
`CSR_GTID ,
`CSR_GWID : read_data = CORE_ID * `NUM_WARPS + 32'(warp_num);
`CSR_GCID : read_data = CORE_ID;
`CSR_NT : read_data = `NUM_THREADS;
`CSR_NW : read_data = `NUM_WARPS;
`CSR_NC : read_data = `NUM_CORES * `NUM_CLUSTERS;
`CSR_CYCLL : read_data = num_cycles[31:0];
`CSR_CYCLH : read_data = num_cycles[63:32];
`CSR_INSTL : read_data = num_instrs[31:0];
`CSR_INSTH : read_data = num_instrs[63:32];
default: read_data = 32'(csr_table[rd_addr]);
`CSR_LWID : read_data = 32'(warp_num);
`CSR_GTID ,
`CSR_GWID : read_data = CORE_ID * `NUM_WARPS + 32'(warp_num);
`CSR_GCID : read_data = CORE_ID;
`CSR_NT : read_data = `NUM_THREADS;
`CSR_NW : read_data = `NUM_WARPS;
`CSR_NC : read_data = `NUM_CORES * `NUM_CLUSTERS;
`CSR_CYCLE_L : read_data = num_cycles[31:0];
`CSR_CYCLE_H : read_data = num_cycles[63:32];
`CSR_INSTR_L : read_data = num_instrs[31:0];
`CSR_INSTR_H : read_data = num_instrs[63:32];
`CSR_VEND_ID : read_data = `VENDOR_ID;
`CSR_ARCH_ID : read_data = `ARCHITECTURE_ID;
`CSR_IMPL_ID : read_data = `IMPLEMENTATION_ID;
default : read_data = 32'(csr_table[rd_addr]);
endcase
end