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fixed fp_noncomp bug, ci toolchain script update, increased DRAM latency to 100 cycles

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This commit is contained in:
Blaise Tine
2020-11-23 11:59:40 -08:00
parent e281d32138
commit 2d4fef6dd6
6 changed files with 50 additions and 28 deletions
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12
hw/rtl/fp_cores/VX_fp_noncomp.v
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@@ -147,7 +147,7 @@ module VX_fp_noncomp #(
case (frm_r) // use LSB to distinguish MIN and MAX
3: fminmax_res[i] = a_smaller[i] ? dataa_r[i] : datab_r[i];
4: fminmax_res[i] = a_smaller[i] ? datab_r[i] : dataa_r[i];
default: fminmax_res[i] = 32'hdeadbeaf; // don't care value
default: fminmax_res[i] = 'x; // don't care value
endcase
end
end
@@ -160,7 +160,7 @@ module VX_fp_noncomp #(
0: fsgnj_res[i] = { b_sign[i], a_exponent[i], a_mantissa[i]};
1: fsgnj_res[i] = {~b_sign[i], a_exponent[i], a_mantissa[i]};
2: fsgnj_res[i] = { a_sign[i] ^ b_sign[i], a_exponent[i], a_mantissa[i]};
default: fsgnj_res[i] = 32'hdeadbeaf; // don't care value
default: fsgnj_res[i] = 'x; // don't care value
endcase
end
end
@@ -192,8 +192,8 @@ module VX_fp_noncomp #(
`FRM_RDN: begin
if (a_type[i].is_nan || b_type[i].is_nan) begin
fcmp_res[i] = 32'h0; // result is 0 when either operand is NaN
// ** FEQS only raise NV flag when either operand is signaling NaN
fcmp_excp[i] = {(a_type[i].is_signaling | b_type[i].is_signaling), 4'h0};
// FEQS only raise NV flag when either operand is signaling NaN
fcmp_excp[i] = {(a_type[i].is_signaling | b_type[i].is_signaling), 4'h0};
end
else begin
fcmp_res[i] = {31'h0, ab_equal[i]};
@@ -201,7 +201,7 @@ module VX_fp_noncomp #(
end
end
default: begin
fcmp_res[i] = 32'hdeadbeaf; // don't care value
fcmp_res[i] = 'x; // don't care value
fcmp_excp[i] = 5'h0;
end
endcase
@@ -226,7 +226,7 @@ module VX_fp_noncomp #(
end
//`FPU_MISC:
default: begin
case (frm)
case (frm_r)
0,1,2: begin
tmp_result[i] = fsgnj_res[i];
{tmp_fflags[i].NV, tmp_fflags[i].DZ, tmp_fflags[i].OF, tmp_fflags[i].UF, tmp_fflags[i].NX} = 5'h0;

16
hw/simulate/simulator.cpp
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@@ -4,7 +4,7 @@
#include <iomanip>
#define ENABLE_DRAM_STALLS
#define DRAM_LATENCY 4
#define DRAM_LATENCY 100
#define DRAM_RQ_SIZE 16
#define DRAM_STALLS_MODULO 16
@@ -180,9 +180,19 @@ void Simulator::eval_dram_bus() {
}
} else {
dram_req_t dram_req;
dram_req.cycles_left = DRAM_LATENCY;
dram_req.tag = vortex_->dram_req_tag;
dram_req.tag = vortex_->dram_req_tag;
dram_req.addr = vortex_->dram_req_addr;
ram_->read(vortex_->dram_req_addr * GLOBAL_BLOCK_SIZE, GLOBAL_BLOCK_SIZE, dram_req.block.data());
dram_req.cycles_left = DRAM_LATENCY;
for (auto& req : dram_rsp_vec_) {
if (req.addr == dram_req.addr) {
dram_req.cycles_left = req.cycles_left;
break;
}
}
dram_rsp_vec_.emplace_back(dram_req);
}
}

3
hw/simulate/simulator.h
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@@ -51,7 +51,8 @@ private:
typedef struct {
int cycles_left;
std::array<uint8_t, GLOBAL_BLOCK_SIZE> block;
unsigned tag;
uint32_t tag;
uint32_t addr;
} dram_req_t;
std::unordered_map<int, std::stringstream> print_bufs_;