From 2d39e0561ccda57cd5737e2b826f3facbaf502aa Mon Sep 17 00:00:00 2001
From: trmontgomery <tiffany.re.montgomery@gmail.com>
Date: Sat, 18 Jul 2020 23:58:56 -0400
Subject: [PATCH] Revert "successfully invalidate req after empty"

This reverts commit 9ed2012b12d99df33150c72ebcc880ae3feb3077.
---
 hw/unit_tests/cache/cachesim.cpp  | 56 +++++++++++++++++++++++++++++--
 hw/unit_tests/cache/testbench.cpp | 26 ++++++++++++--
 2 files changed, 77 insertions(+), 5 deletions(-)

diff --git a/hw/unit_tests/cache/cachesim.cpp b/hw/unit_tests/cache/cachesim.cpp
index 26463686..d247b3b9 100644
--- a/hw/unit_tests/cache/cachesim.cpp
+++ b/hw/unit_tests/cache/cachesim.cpp
@@ -77,11 +77,20 @@ void CacheSim::run(){
 #ifndef NDEBUG
   std::cout << timestamp << ": [sim] run()" << std::endl;
 #endif
+  // reset the device
+  this->reset();
   this->step();
 
   // execute program
-  for(int i = 0; i < 1000; ++i){ //should be while requests aren't responded to
+  while (!core_req_vec_.empty()) {
+
+    for(int i = 0; i < 10; ++i){
+      if(i == 1){
+        this->clear_req(); //invalidate reqs
+      }
       this->step();
+    }
+
   }
 }
 
@@ -102,11 +111,49 @@ bool CacheSim::get_core_rsp_ready(){
   return cache_->core_rsp_ready; 
 }
 
+void CacheSim::set_core_req(){
+  cache_->core_req_valid = 0xf; 
+  cache_->core_req_rw = 0xf; 
+  cache_->core_req_byteen = 0xffff;   
+  cache_->core_req_addr[0] = 0x00;
+  cache_->core_req_addr[1] = 0xab;
+  cache_->core_req_addr[2] = 0xcd;
+  cache_->core_req_addr[3] = 0xe1;  
+  cache_->core_req_data[0] = 0xffffffff;
+  cache_->core_req_data[1] = 0x11111111;
+  cache_->core_req_data[2] = 0x22222222;
+  cache_->core_req_data[3] = 0x33333333;  
+  cache_->core_req_tag = 0xff;
+}
+
+void CacheSim::set_core_req2(){
+  cache_->core_req_valid = 0xf; //b1000
+  cache_->core_req_rw = 0x0; //b0000
+  cache_->core_req_byteen = 0xffff;   
+  cache_->core_req_addr[0] = 0x00;
+  cache_->core_req_addr[1] = 0xab;
+  cache_->core_req_addr[2] = 0xcd;
+  cache_->core_req_addr[3] = 0xe1;  
+  cache_->core_req_data[0] = 0x1111111;
+  cache_->core_req_data[1] = 0x4444444;
+  cache_->core_req_data[2] = 0x5555555;
+  cache_->core_req_data[3] = 0x6666666;
+  cache_->core_req_tag = 0xff;
+}
+
+
 void CacheSim::eval_reqs(){
   //check to see if cache is accepting reqs
   if(!core_req_vec_.empty() && cache_->core_req_ready){
     core_req_t *req = core_req_vec_.front();
 
+    std::cout << "Display Req Data Contents " << std::endl; 
+
+    std::cout << std::hex << "Data[0]: " << req->data[0] << std::endl; 
+    std::cout << std::hex << "Data[1]: " << req->data[1] << std::endl; 
+    std::cout << std::hex << "Data[2]: " << req->data[2] << std::endl; 
+    std::cout << std::hex << "Data[3]: " << req->data[3] << std::endl; 
+
     cache_->core_req_valid = req->valid;
     cache_->core_req_rw = req->rw; 
     cache_->core_req_byteen = req->byteen;
@@ -123,9 +170,12 @@ void CacheSim::eval_reqs(){
 
     cache_->core_req_tag = req->tag; 
 
+
+    std::cout << "Display Cache Data inputs: " << std::endl;  
+    get_core_req();
+
     core_req_vec_.pop();
-  } else {
-    clear_req();
+    std::cout << "Req Popped" << std::endl; 
   }
 }
 
diff --git a/hw/unit_tests/cache/testbench.cpp b/hw/unit_tests/cache/testbench.cpp
index 6327659e..ba05a77e 100644
--- a/hw/unit_tests/cache/testbench.cpp
+++ b/hw/unit_tests/cache/testbench.cpp
@@ -11,7 +11,6 @@ int main(int argc, char **argv)
   RAM ram;
 	CacheSim cachesim;
   cachesim.attach_ram(&ram);
-  cachesim.reset();
 
   unsigned int addr[4] = {0x12222222, 0xabbbbbbb, 0xcddddddd, 0xe4444444};
   unsigned int data[4] = {0xffffffff, 0x11111111, 0x22222222, 0x33333333};
@@ -32,12 +31,35 @@ int main(int argc, char **argv)
   read->addr = addr;
   read->data = addr; 
   read->tag = 0xff;
+  
+	// reset the device
+  cachesim.reset();
 
   //queue reqs
   cachesim.send_req(write);
   cachesim.send_req(read);
+  cachesim.step();
+  //cachesim.get_core_req();
+  //write block to cache
+ // cachesim.set_core_req();
 
-  cachesim.run(); 
+  for (int i = 0; i < 100; ++i){
+    /*if(i == 1){
+      cachesim.clear_req();
+    }*/
+    cachesim.step();
+  }
+  cachesim.get_core_req();
+  // read block
+  //cachesim.set_core_req2();
+  for (int i = 0; i < 100; ++i){
+    if(i == 1){
+      //read block from cache
+      cachesim.clear_req();
 
+    }
+    cachesim.step();
+  } 
+  
 	return 0;
 }