Got queue_ll to work by modifying when to update bypass
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@@ -62,7 +62,7 @@ module VX_bank (
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reg snrq_hazard_st0;
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assign snrq_valid_st0 = !snrq_empty;
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VX_generic_queue #(.DATAW(32), .SIZE(`SNRQ_SIZE)) snr_queue(
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VX_generic_queue_ll #(.DATAW(32), .SIZE(`SNRQ_SIZE)) snr_queue(
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.clk (clk),
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.reset (reset),
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.push (snp_req),
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@@ -82,7 +82,7 @@ module VX_bank (
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assign dram_fill_accept = !dfpq_full;
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VX_generic_queue #(.DATAW(32+(`BANK_LINE_SIZE_WORDS*32)), .SIZE(`DFPQ_SIZE)) dfp_queue(
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VX_generic_queue_ll #(.DATAW(32+(`BANK_LINE_SIZE_WORDS*32)), .SIZE(`DFPQ_SIZE)) dfp_queue(
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.clk (clk),
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.reset (reset),
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.push (dram_fill_rsp),
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@@ -199,7 +199,7 @@ module VX_bank (
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assign dfpq_pop = !dfpq_empty && !stall_bank_pipe && !dfpq_hazard_st0;
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assign mrvq_pop = !dfpq_pop && mrvq_valid_st0 && !stall_bank_pipe && !mrvq_hazard_st0;
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assign reqq_pop = !mrvq_pop && reqq_req_st0 && !stall_bank_pipe && !is_fill_st1[0] && !reqq_hazard_st0;
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assign reqq_pop = !mrvq_pop && !reqq_empty && reqq_req_st0 && !stall_bank_pipe && !is_fill_st1[0] && !reqq_hazard_st0;
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assign snrq_pop = !reqq_pop && snrq_valid_st0 && !stall_bank_pipe && !snrq_hazard_st0;
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@@ -385,7 +385,7 @@ module VX_bank (
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wire cwbq_full;
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wire cwbq_empty;
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assign bank_wb_valid = !cwbq_empty;
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VX_generic_queue #(.DATAW( `vx_clog2(`NUMBER_REQUESTS) + 5 + 2 + (`NW_M1+1) + 32), .SIZE(`CWBQ_SIZE)) cwb_queue(
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VX_generic_queue_ll #(.DATAW( `vx_clog2(`NUMBER_REQUESTS) + 5 + 2 + (`NW_M1+1) + 32), .SIZE(`CWBQ_SIZE)) cwb_queue(
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.clk (clk),
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.reset (reset),
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@@ -425,7 +425,7 @@ module VX_bank (
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assign dram_fill_req_addr = addr_st2;
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assign dram_wb_req = !dwbq_empty;
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VX_generic_queue #(.DATAW( 1 + 32 + (`BANK_LINE_SIZE_WORDS * 32) + 1 + 1), .SIZE(`DWBQ_SIZE)) dwb_queue(
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VX_generic_queue_ll #(.DATAW( 1 + 32 + (`BANK_LINE_SIZE_WORDS * 32) + 1 + 1), .SIZE(`DWBQ_SIZE)) dwb_queue(
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.clk (clk),
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.reset (reset),
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