speeding up simulation using dedicated full dpi-based FPU core
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@@ -3,7 +3,7 @@
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#include <fstream>
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#include <iomanip>
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#define RESET_DELAY 2
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#define RESET_DELAY 4
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#define ENABLE_DRAM_STALLS
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#define DRAM_LATENCY 24
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@@ -75,13 +75,6 @@ void Simulator::reset() {
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vortex_->csr_rsp_ready = 0;
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vortex_->reset = 1;
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vortex_->clk = 0;
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this->eval();
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vortex_->clk = 1;
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this->eval();
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vortex_->reset = 0;
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for (int i = 0; i < RESET_DELAY; ++i) {
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vortex_->clk = 0;
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@@ -89,8 +82,11 @@ void Simulator::reset() {
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vortex_->clk = 1;
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this->eval();
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}
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vortex_->reset = 0;
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// Turn on assertion after reset
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printf("*** enabling assertion at tick: %ld", timestamp);
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Verilated::assertOn(true);
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}
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