fixed register file initialization to zero synthesis inference

2020-12-10 00:27:56 -08:00
parent 3e9abb978b
commit 29cd2f5dff
10 changed files with 171 additions and 130 deletions
--- a/hw/rtl/VX_csr_unit.v
+++ b/hw/rtl/VX_csr_unit.v
@@ -102,7 +102,7 @@ module VX_csr_unit #(
        endcase
    end

-    wire stall_in = fpu_pending[csr_pipe_req_if.wid];
+    wire stall_in = !csr_pipe_req_if.is_io && fpu_pending[csr_pipe_req_if.wid];

    wire pipe_req_valid_qual = csr_pipe_req_if.valid && !stall_in;