fixed register file initialization to zero synthesis inference

driver/opae/Makefile

@@ -85,7 +85,7 @@ vlsim-hw: $(SCOPE_H)
 fpga: $(SRCS) $(SCOPE_H)
 	$(CXX) $(CXXFLAGS) -DUSE_FPGA $^ $(LDFLAGS) $(FPGA_LIBS) -o $(PROJECT)
 
-asesim: $(SRCS) $(ASE_DIR)
+asesim: $(SRCS) $(ASE_DIR) $(SCOPE_H)
 	$(CXX) $(CXXFLAGS) -DUSE_ASE $(SRCS) $(LDFLAGS) $(ASE_LIBS) -o $(PROJECT_ASE)
 
 vlsim: $(SRCS) vlsim-hw

driver/opae/vx_scope.h

@@ -1,6 +1,10 @@
 #pragma once
 
+#if defined(USE_FPGA)
 #define HANG_TIMEOUT 60
+#else
+#define HANG_TIMEOUT (30*60)
+#endif
 
 int vx_scope_start(fpga_handle hfpga, uint64_t delay = -1);