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minor update

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This commit is contained in:
Blaise Tine
2021-09-30 06:14:05 -07:00
parent fe14a9933d
commit 29aba92bf1
5 changed files with 35 additions and 19 deletions
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8
hw/rtl/VX_gpu_types.vh
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@@ -10,7 +10,7 @@ typedef struct packed {
logic [`NUM_THREADS-1:0] tmask; logic [`NUM_THREADS-1:0] tmask;
} gpu_tmc_t; } gpu_tmc_t;
`define GPU_TMC_BITS $bits(gpu_tmc_t) `define GPU_TMC_BITS $bits(gpu_types::gpu_tmc_t)
typedef struct packed { typedef struct packed {
logic valid; logic valid;
@@ -18,7 +18,7 @@ typedef struct packed {
logic [31:0] pc; logic [31:0] pc;
} gpu_wspawn_t; } gpu_wspawn_t;
`define GPU_WSPAWN_BITS $bits(gpu_wspawn_t) `define GPU_WSPAWN_BITS $bits(gpu_types::gpu_wspawn_t)
typedef struct packed { typedef struct packed {
logic valid; logic valid;
@@ -28,7 +28,7 @@ typedef struct packed {
logic [31:0] pc; logic [31:0] pc;
} gpu_split_t; } gpu_split_t;
`define GPU_SPLIT_BITS $bits(gpu_split_t) `define GPU_SPLIT_BITS $bits(gpu_types::gpu_split_t)
typedef struct packed { typedef struct packed {
logic valid; logic valid;
@@ -36,7 +36,7 @@ typedef struct packed {
logic [`NW_BITS-1:0] size_m1; logic [`NW_BITS-1:0] size_m1;
} gpu_barrier_t; } gpu_barrier_t;
`define GPU_BARRIER_BITS $bits(gpu_barrier_t) `define GPU_BARRIER_BITS $bits(gpu_types::gpu_barrier_t)
endpackage endpackage

6
hw/rtl/VX_issue.sv
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@@ -131,8 +131,8 @@ module VX_issue #(
`SCOPE_ASSIGN (issue_imm, ibuffer_if.imm); `SCOPE_ASSIGN (issue_imm, ibuffer_if.imm);
`SCOPE_ASSIGN (issue_use_pc, ibuffer_if.use_PC); `SCOPE_ASSIGN (issue_use_pc, ibuffer_if.use_PC);
`SCOPE_ASSIGN (issue_use_imm, ibuffer_if.use_imm); `SCOPE_ASSIGN (issue_use_imm, ibuffer_if.use_imm);
`SCOPE_ASSIGN (scoreboard_delay, scoreboard_delay); `SCOPE_ASSIGN (scoreboard_delay, !sboard_wb_if.ready);
`SCOPE_ASSIGN (execute_delay, ~idmux_ib_if.ready); `SCOPE_ASSIGN (execute_delay, !idmux_ib_if.ready);
`SCOPE_ASSIGN (gpr_rsp_a, gpr_rsp_if.rs1_data); `SCOPE_ASSIGN (gpr_rsp_a, gpr_rsp_if.rs1_data);
`SCOPE_ASSIGN (gpr_rsp_b, gpr_rsp_if.rs2_data); `SCOPE_ASSIGN (gpr_rsp_b, gpr_rsp_if.rs2_data);
`SCOPE_ASSIGN (gpr_rsp_c, gpr_rsp_if.rs3_data); `SCOPE_ASSIGN (gpr_rsp_c, gpr_rsp_if.rs3_data);
@@ -170,7 +170,7 @@ module VX_issue #(
if (decode_if.valid & !decode_if.ready) begin if (decode_if.valid & !decode_if.ready) begin
perf_ibf_stalls <= perf_ibf_stalls + `PERF_CTR_BITS'd1; perf_ibf_stalls <= perf_ibf_stalls + `PERF_CTR_BITS'd1;
end end
if (ibuffer_if.valid & scoreboard_delay) begin if (ibuffer_if.valid & !sboard_wb_if.ready) begin
perf_scb_stalls <= perf_scb_stalls + `PERF_CTR_BITS'd1; perf_scb_stalls <= perf_scb_stalls + `PERF_CTR_BITS'd1;
end end
if (alu_req_if.valid & !alu_req_if.ready) begin if (alu_req_if.valid & !alu_req_if.ready) begin

4
hw/rtl/fp_cores/VX_fpu_types.vh
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@@ -15,7 +15,7 @@ typedef struct packed {
logic is_signaling; logic is_signaling;
} fp_class_t; } fp_class_t;
`define FP_CLASS_BITS $bits(fp_class_t) `define FP_CLASS_BITS $bits(fpu_types::fp_class_t)
typedef struct packed { typedef struct packed {
logic NV; // 4-Invalid logic NV; // 4-Invalid
@@ -25,7 +25,7 @@ typedef struct packed {
logic NX; // 0-Inexact logic NX; // 0-Inexact
} fflags_t; } fflags_t;
`define FFLAGS_BITS $bits(fflags_t) `define FFLAGS_BITS $bits(fpu_types::fflags_t)
endpackage endpackage

31
hw/scripts/scope.json
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@@ -1,10 +1,21 @@
{ {
"version": 1, "version": 1,
"include_paths":[
"../dpi",
"../rtl",
"../rtl/afu",
"../rtl/cache",
"../rtl/fp_cores",
"../rtl/interfaces",
"../rtl/libs"
],
"includes":[ "includes":[
"../dpi/util_dpi.vh", "../rtl/VX_config.vh",
"../rtl/VX_config.vh", "../rtl/VX_platform.vh",
"../rtl/VX_platform.vh", "../rtl/VX_define.vh",
"../rtl/VX_define.vh", "../rtl/VX_gpu_types.vh",
"../rtl/fp_cores/VX_fpu_types.vh",
"../rtl/fp_cores/VX_fpu_define.vh",
"../rtl/cache/VX_cache_define.vh" "../rtl/cache/VX_cache_define.vh"
], ],
"modules": { "modules": {
@@ -61,8 +72,8 @@
"VX_gpu_unit": {}, "VX_gpu_unit": {},
"VX_mem_unit": { "VX_mem_unit": {
"submodules": { "submodules": {
"dcache": {"type":"VX_cache", "params":{"NUM_BANKS":"`DNUM_BANKS"}}, "dcache": {"type":"VX_cache", "params":{"NUM_BANKS":"`DCACHE_NUM_BANKS"}},
"icache": {"type":"VX_cache", "params":{"NUM_BANKS":"`INUM_BANKS"}} "icache": {"type":"VX_cache", "params":{"NUM_BANKS":"1"}}
} }
}, },
"VX_cache": { "VX_cache": {
@@ -112,9 +123,9 @@
"!cci_pending_writes_full": 1, "!cci_pending_writes_full": 1,
"?afu_mem_req_fire": 1, "?afu_mem_req_fire": 1,
"afu_mem_req_addr": 26, "afu_mem_req_addr": 26,
"afu_mem_req_tag": 32, "afu_mem_req_tag": 27,
"?afu_mem_rsp_fire": 1, "?afu_mem_rsp_fire": 1,
"afu_mem_rsp_tag": 32 "afu_mem_rsp_tag": 27
}, },
"afu/vortex": { "afu/vortex": {
"!reset": 1, "!reset": 1,
@@ -133,10 +144,10 @@
"?icache_req_fire": 1, "?icache_req_fire": 1,
"icache_req_wid":"`NW_BITS", "icache_req_wid":"`NW_BITS",
"icache_req_addr": 32, "icache_req_addr": 32,
"icache_req_tag":"`ICORE_TAG_ID_BITS", "icache_req_tag":"`ICACHE_CORE_TAG_ID_BITS",
"?icache_rsp_fire": 1, "?icache_rsp_fire": 1,
"icache_rsp_data": 32, "icache_rsp_data": 32,
"icache_rsp_tag":"`ICORE_TAG_ID_BITS" "icache_rsp_tag":"`ICACHE_CORE_TAG_ID_BITS"
}, },
"afu/vortex/cluster/core/pipeline/fetch/warp_sched": { "afu/vortex/cluster/core/pipeline/fetch/warp_sched": {
"?wsched_scheduled": 1, "?wsched_scheduled": 1,

5
hw/scripts/scope.py
View File

@@ -278,6 +278,7 @@ def expand_text(text, params):
return None return None
def parse_include(filename, nesting): def parse_include(filename, nesting):
print("*** parsing: " + filename + "...")
if nesting > 99: if nesting > 99:
raise Exception("include recursion!") raise Exception("include recursion!")
#print("*** parsing '" + filename + "'...") #print("*** parsing '" + filename + "'...")
@@ -812,6 +813,10 @@ def main():
exclude_files.append(os.path.basename(args.vl)) exclude_files.append(os.path.basename(args.vl))
if "include_paths" in config:
for path in config["include_paths"]:
load_include_path(path)
if "includes" in config: if "includes" in config:
parse_includes(config["includes"]) parse_includes(config["includes"])