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constant integration updates

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This commit is contained in:
Blaise Tine
2020-11-15 21:30:31 -08:00
parent 60f5c15bc8
commit 2904f6441d
19 changed files with 58 additions and 61 deletions
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4
hw/rtl/cache/VX_bank.v vendored
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@@ -604,8 +604,8 @@ module VX_bank #(
// mark msrq entry that match DRAM fill as 'ready'
wire update_ready_st0 = dfpq_pop;
// push missed requests as 'ready' is this was a forced missed
// this request will be queued behind prior requests so will only pop when the fill arrives.
// push missed requests as 'ready' if it was a forced miss but actually had a hit
// or the fill request is comming for the missed block
wire msrq_init_ready_state_st3 = !miss_st3 || incoming_fill;
VX_cache_miss_resrv #(