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tensor: Improve commit efficiency by decoupling dpu with fifo

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This commit is contained in:
Hansung Kim
2024-05-26 21:59:25 -07:00
parent 864265bda5
commit 28f6cd59b5
3 changed files with 34 additions and 20 deletions
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10
hw/rtl/fpu/VX_tensor_dpu.sv
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@@ -15,11 +15,11 @@ module VX_tensor_dpu #(
input [3:0][1:0][31:0] A_tile,
input [1:0][3:0][31:0] B_tile,
input [3:0][3:0][31:0] C_tile,
input [`NW_WIDTH-1:0] warp_id,
input [`NW_WIDTH-1:0] wid,
output valid_out,
output [3:0][3:0][31:0] D_tile,
output [`NW_WIDTH-1:0] D_warp_id
output [`NW_WIDTH-1:0] D_wid
);
logic [3:0][3:0][31:0] result_hmma;
@@ -44,15 +44,15 @@ module VX_tensor_dpu #(
// fixed-latency model
VX_shift_register #(
.DATAW (1 + $bits(warp_id) + $bits(D_tile)),
.DATAW (1 + $bits(wid) + $bits(D_tile)),
.DEPTH (`LATENCY_HMMA),
.RESETW (1)
) shift_reg (
.clk (clk),
.reset (reset),
.enable (~stall),
.data_in ({valid_in, warp_id, result_hmma}),
.data_out ({valid_out, D_warp_id, D_tile})
.data_in ({valid_in, wid, result_hmma}),
.data_out ({valid_out, D_wid, D_tile})
);
endmodule
`endif