RTL code refactoring

2020-04-23 12:38:44 -04:00
parent f0e257bc8e
commit 28d054e295
39 changed files with 179 additions and 225 deletions
--- a/hw/rtl/VX_lsu_unit.v
+++ b/hw/rtl/VX_lsu_unit.v
@@ -9,8 +9,8 @@ module VX_lsu_unit (
    // Write back to GPR
    VX_inst_mem_wb_if       mem_wb_if,

-    VX_gpu_dcache_rsp_if    dcache_rsp_if,
-    VX_gpu_dcache_req_if    dcache_req_if,
+    VX_cache_core_rsp_if    dcache_rsp_if,
+    VX_cache_core_req_if    dcache_req_if,
    output wire             delay
 );
    // Generate Addresses