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RTL code refactoring

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This commit is contained in:
Blaise Tine
2020-04-23 14:12:08 -04:00
parent f79067fb52
commit 2846809823
3 changed files with 68 additions and 68 deletions
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24
hw/simulate/simulator.cpp
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@@ -60,11 +60,11 @@ void Simulator::dbus_driver() {
#endif
if (!dram_stalled_) {
if (vortex_->dram_req_read) {
if (vortex_->D_dram_req_read) {
// Need to add an element
dram_req_t dram_req;
dram_req.cycles_left = DRAM_LATENCY;
dram_req.base_addr = vortex_->dram_req_addr;
dram_req.base_addr = vortex_->D_dram_req_addr;
dram_req.data = (unsigned *)malloc(GLOBAL_BLOCK_SIZE_BYTES);
for (int i = 0; i < (GLOBAL_BLOCK_SIZE_BYTES / 4); i++) {
@@ -76,33 +76,33 @@ void Simulator::dbus_driver() {
dram_req_vec_.push_back(dram_req);
}
if (vortex_->dram_req_write) {
unsigned base_addr = vortex_->dram_req_addr;
if (vortex_->D_dram_req_write) {
unsigned base_addr = vortex_->D_dram_req_addr;
for (int i = 0; i < (GLOBAL_BLOCK_SIZE_BYTES / 4); i++) {
unsigned curr_addr = base_addr + (i * 4);
unsigned data_wr = vortex_->dram_req_data[i];
unsigned data_wr = vortex_->D_dram_req_data[i];
ram_->writeWord(curr_addr, &data_wr);
}
}
}
if (vortex_->dram_rsp_ready && dequeue_valid) {
vortex_->dram_rsp_valid = 1;
vortex_->dram_rsp_addr = dram_req_vec_[dequeue_index].base_addr;
if (vortex_->D_dram_rsp_ready && dequeue_valid) {
vortex_->D_dram_rsp_valid = 1;
vortex_->D_dram_rsp_addr = dram_req_vec_[dequeue_index].base_addr;
for (int i = 0; i < (GLOBAL_BLOCK_SIZE_BYTES / 4); i++) {
vortex_->dram_rsp_data[i] = dram_req_vec_[dequeue_index].data[i];
vortex_->D_dram_rsp_data[i] = dram_req_vec_[dequeue_index].data[i];
}
free(dram_req_vec_[dequeue_index].data);
dram_req_vec_.erase(dram_req_vec_.begin() + dequeue_index);
} else {
vortex_->dram_rsp_valid = 0;
vortex_->dram_rsp_addr = 0;
vortex_->D_dram_rsp_valid = 0;
vortex_->D_dram_rsp_addr = 0;
}
vortex_->dram_req_ready = ~dram_stalled_;
vortex_->D_dram_req_ready = ~dram_stalled_;
}
#ifndef USE_MULTICORE