multiplier fixes
This commit is contained in:
Blaise Tine
@@ -3,12 +3,12 @@
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module VX_divide #(
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parameter WIDTHN = 1,
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parameter WIDTHD = 1,
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parameter REP = "UNSIGNED",
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parameter NSIGNED = 0,
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parameter DSIGNED = 0,
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parameter PIPELINE = 0
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) (
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input wire clk,
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input wire reset,
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input wire clken,
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input [WIDTHN-1:0] numer,
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input [WIDTHD-1:0] denom,
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@@ -19,84 +19,90 @@ module VX_divide #(
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`ifdef QUARTUS
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lpm_divide #(
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.LPM_WIDTHN(WIDTHN),
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.LPM_WIDTHD(WIDTHD),
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.LPM_NREPRESENTATION(REP),
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.LPM_DREPRESENTATION(REP),
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.LPM_PIPELINE(PIPELINE),
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.DSP_BLOCK_BALANCING("LOGIC ELEMENTS"),
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.MAXIMIZE_SPEED(9)
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) quartus_divider (
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.clock(clk),
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.aclr(reset),
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.clken(clken),
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.numer(numer),
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.denom(denom),
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.quotient(quotient),
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.remain(remainder)
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lpm_divide quartus_div (
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.clock (clk),
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.numer (numer),
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.denom (denom),
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.quotient (quotient),
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.remain (remainder),
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.aclr (1'b0),
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.clken (1'b1)
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);
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defparam
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quartus_div.lpm_type = "LPM_DIVIDE",
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quartus_div.lpm_widthn = WIDTHN,
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quartus_div.lpm_widthd = WIDTHD,
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quartus_div.lpm_nrepresentation = NSIGNED ? "SIGNED" : "UNSIGNED",
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quartus_div.lpm_drepresentation = DSIGNED ? "SIGNED" : "UNSIGNED",
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quartus_div.lpm_hint = "LPM_REMAINDERPOSITIVE=FALSE,MAXIMIZE_SPEED=9",
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quartus_div.lpm_pipeline = PIPELINE;
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`else
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wire [WIDTHN-1:0] numer_pipe_end;
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wire [WIDTHD-1:0] denom_pipe_end;
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reg [WIDTHN-1:0] quotient_unqual;
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reg [WIDTHD-1:0] remainder_unqual;
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always @(*) begin
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`ifndef SYNTHESIS
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// this edge case kills verilator in some cases by causing a division
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// overflow exception. INT_MIN / -1 (on x86)
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if (numer == {1'b1, (WIDTHN-1)'(0)}
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&& denom == {WIDTHD{1'b1}}) begin
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quotient_unqual = 0;
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remainder_unqual = 0;
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end else
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`endif
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begin
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if (NSIGNED && DSIGNED) begin
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quotient_unqual = $signed(numer) / $signed(denom);
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remainder_unqual = $signed(numer) % $signed(denom);
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end
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else if (NSIGNED && !DSIGNED) begin
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quotient_unqual = $signed(numer) / denom;
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remainder_unqual = $signed(numer) % denom;
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end
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else if (!NSIGNED && DSIGNED) begin
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quotient_unqual = numer / $signed(denom);
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remainder_unqual = numer % $signed(denom);
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end
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else begin
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quotient_unqual = numer / denom;
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remainder_unqual = numer % denom;
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end
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end
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end
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if (PIPELINE == 0) begin
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assign numer_pipe_end = numer;
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assign denom_pipe_end = denom;
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assign quotient = quotient_unqual;
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assign remainder = remainder_unqual;
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end else begin
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reg [WIDTHN-1:0] numer_pipe [0:PIPELINE-1];
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reg [WIDTHD-1:0] denom_pipe [0:PIPELINE-1];
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reg [WIDTHN-1:0] quotient_pipe [0:PIPELINE-1];
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reg [WIDTHD-1:0] remainder_pipe [0:PIPELINE-1];
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genvar i;
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for (i = 0; i < PIPELINE; i++) begin
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always @(posedge clk) begin
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if (reset) begin
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numer_pipe[i] <= 0;
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denom_pipe[i] <= 0;
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quotient_pipe[i] <= 0;
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remainder_pipe[i] <= 0;
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end
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else if (clken) begin
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else begin
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if (i == 0) begin
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numer_pipe[0] <= numer;
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denom_pipe[0] <= denom;
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quotient_pipe[0] <= quotient_unqual;
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remainder_pipe[0] <= remainder_unqual;
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end else begin
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numer_pipe[i] <= numer_pipe[i-1];
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denom_pipe[i] <= denom_pipe[i-1];
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quotient_pipe[i] <= quotient_pipe[i-1];
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remainder_pipe[i] <= remainder_pipe[i-1];
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end
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end
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end
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end
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assign numer_pipe_end = numer_pipe[PIPELINE-1];
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assign denom_pipe_end = denom_pipe[PIPELINE-1];
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end
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always @(*) begin
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if (denom_pipe_end == 0) begin
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quotient = {WIDTHN{1'b1}};
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remainder = numer_pipe_end;
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end
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`ifndef SYNTHESIS
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// this edge case kills verilator in some cases by causing a division
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// overflow exception. INT_MIN / -1 (on x86)
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else if (numer_pipe_end == {1'b1, (WIDTHN-1)'(0)}
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&& denom_pipe_end == {WIDTHD{1'b1}}) begin
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quotient = 0;
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remainder = 0;
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end
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`endif
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else begin
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if (REP == "SIGNED") begin
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quotient = $signed(numer_pipe_end) / $signed(denom_pipe_end);
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remainder = $signed(numer_pipe_end) % $signed(denom_pipe_end);
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end else begin
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quotient = numer_pipe_end / denom_pipe_end;
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remainder = numer_pipe_end % denom_pipe_end;
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end
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end
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end
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assign quotient = quotient_pipe[PIPELINE-1];
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assign remainder = remainder_pipe[PIPELINE-1];
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end
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`endif
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endmodule : VX_divide
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endmodule
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@@ -4,12 +4,11 @@ module VX_mult #(
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parameter WIDTHA = 1,
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parameter WIDTHB = 1,
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parameter WIDTHP = 1,
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parameter REP = "UNSIGNED",
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parameter SIGNED = 0,
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parameter PIPELINE = 0
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) (
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input clk,
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input reset,
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input clken,
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input [WIDTHA-1:0] dataa,
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input [WIDTHB-1:0] datab,
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@@ -19,65 +18,59 @@ module VX_mult #(
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`ifdef QUARTUS
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lpm_mult #(
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.LPM_WIDTHA(WIDTHA),
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.LPM_WIDTHB(WIDTHB),
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.LPM_WIDTHP(WIDTHP),
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.LPM_REPRESENTATION(REP),
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.LPM_PIPELINE(PIPELINE),
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.DSP_BLOCK_BALANCING("LOGIC ELEMENTS"),
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.MAXIMIZE_SPEED(9)
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) quartus_mult (
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.clock(clk),
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.aclr(reset),
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.clken(clken),
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.dataa(dataa),
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.datab(datab),
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.result(result)
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lpm_mult quartus_mult (
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.clock (clk),
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.dataa (dataa),
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.datab (datab),
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.result (result),
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.aclr (1'b0),
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.clken (1'b1),
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.sclr (1'b0),
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.sum (1'b0)
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);
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defparam quartus_mult.lpm_type = "LPM_MULT",
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quartus_mult.lpm_widtha = WIDTHA,
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quartus_mult.lpm_widthb = WIDTHB,
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quartus_mult.lpm_widthp = WIDTHP,
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quartus_mult.lpm_representation = SIGNED ? "SIGNED" : "UNSIGNED",
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quartus_mult.lpm_pipeline = PIPELINE,
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quartus_mult.lpm_hint = "MAXIMIZE_SPEED=9";
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`else
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wire [WIDTHA-1:0] dataa_pipe_end;
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wire [WIDTHB-1:0] datab_pipe_end;
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if (PIPELINE == 0) begin
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assign dataa_pipe_end = dataa;
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assign datab_pipe_end = datab;
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wire [WIDTHP-1:0] result_unqual;
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if (SIGNED) begin
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assign result_unqual = $signed(dataa) * $signed(datab);
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end else begin
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reg [WIDTHA-1:0] dataa_pipe [0:PIPELINE-1];
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reg [WIDTHB-1:0] datab_pipe [0:PIPELINE-1];
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assign result_unqual = dataa * datab;
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end
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if (PIPELINE == 0) begin
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assign result = result_unqual;
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end else begin
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reg [WIDTHP-1:0] result_pipe [0:PIPELINE-1];
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genvar i;
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for (i = 0; i < PIPELINE; i++) begin
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always @(posedge clk) begin
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if (reset) begin
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dataa_pipe[i] <= 0;
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datab_pipe[i] <= 0;
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result_pipe[i] <= 0;
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end
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else if (clken) begin
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else begin
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if (i == 0) begin
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dataa_pipe[0] <= dataa;
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datab_pipe[0] <= datab;
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result_pipe[0] <= result_unqual;
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end else begin
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dataa_pipe[i] <= dataa_pipe[i-1];
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datab_pipe[i] <= datab_pipe[i-1];
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result_pipe[i] <= result_pipe[i-1];
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end
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end
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end
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end
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assign dataa_pipe_end = dataa_pipe[PIPELINE-1];
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assign datab_pipe_end = datab_pipe[PIPELINE-1];
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end
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if (REP == "SIGNED") begin
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assign result = $signed(dataa_pipe_end) * $signed(datab_pipe_end);
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end
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else begin
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assign result = dataa_pipe_end * datab_pipe_end;
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assign result = result_pipe[PIPELINE-1];
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end
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`endif
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endmodule: VX_mult
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endmodule
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