pipeline optimization
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@@ -15,7 +15,7 @@ module VX_index_queue #(
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input wire [`LOG2UP(SIZE)-1:0] read_addr,
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output wire [DATAW-1:0] read_data
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);
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reg [DATAW-1:0] data [SIZE-1:0];
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`USE_FAST_BRAM reg [DATAW-1:0] data [SIZE-1:0];
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reg [SIZE-1:0] valid;
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reg [`LOG2UP(SIZE):0] rd_ptr, wr_ptr;
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