diff --git a/hw/rtl/VX_config.vh b/hw/rtl/VX_config.vh index f78ca3b9..5df9d501 100644 --- a/hw/rtl/VX_config.vh +++ b/hw/rtl/VX_config.vh @@ -105,11 +105,19 @@ `endif `ifndef LATENCY_FDIV -`define LATENCY_FDIV 15 +`ifdef ALTERA_S10 +`define LATENCY_FDIV 34 +`else +`define LATENCY_FDIV 20 +`endif `endif `ifndef LATENCY_FSQRT -`define LATENCY_FSQRT 10 +`ifdef ALTERA_S10 +`define LATENCY_FSQRT 25 +`else +`define LATENCY_FSQRT 15 +`endif `endif `ifndef LATENCY_ITOF diff --git a/hw/rtl/fp_cores/VX_fp_addmul.v b/hw/rtl/fp_cores/VX_fp_addmul.v index 3a1404b0..8a34c9bb 100644 --- a/hw/rtl/fp_cores/VX_fp_addmul.v +++ b/hw/rtl/fp_cores/VX_fp_addmul.v @@ -41,125 +41,32 @@ module VX_fp_addmul #( wire [31:0] result_mul; `ifdef QUARTUS - twentynm_fp_mac mac_fp_add ( - // inputs - .accumulate(), - .chainin_overflow(), - .chainin_invalid(), - .chainin_underflow(), - .chainin_inexact(), - .ax(dataa[i]), - .ay(datab[i]), - .az(), - .clk({2'b00, clk}), - .ena({2'b00, enable}), - .aclr({reset, reset}), - .chainin(), - // outputs - .overflow(), - .invalid(), - .underflow(), - .inexact(), - .chainout_overflow(), - .chainout_invalid(), - .chainout_underflow(), - .chainout_inexact(), - .resulta(result_add), - .chainout() + acl_fadd fadd ( + .clk (clk), + .areset (reset), + .en (enable), + .a (dataa[i]), + .b (datab[i]), + .q (result_add) ); - defparam mac_fp_add.operation_mode = "sp_add"; - defparam mac_fp_add.use_chainin = "false"; - defparam mac_fp_add.adder_subtract = "false"; - defparam mac_fp_add.ax_clock = "0"; - defparam mac_fp_add.ay_clock = "0"; - defparam mac_fp_add.az_clock = "none"; - defparam mac_fp_add.output_clock = "0"; - defparam mac_fp_add.accumulate_clock = "none"; - defparam mac_fp_add.ax_chainin_pl_clock = "none"; - defparam mac_fp_add.accum_pipeline_clock = "none"; - defparam mac_fp_add.mult_pipeline_clock = "none"; - defparam mac_fp_add.adder_input_clock = "0"; - defparam mac_fp_add.accum_adder_clock = "none"; - twentynm_fp_mac mac_fp_sub ( - // inputs - .accumulate(), - .chainin_overflow(), - .chainin_invalid(), - .chainin_underflow(), - .chainin_inexact(), - .ax(dataa[i]), - .ay(datab[i]), - .az(), - .clk({2'b00, clk}), - .ena({2'b00, enable}), - .aclr({reset, reset}), - .chainin(), - // outputs - .overflow(), - .invalid(), - .underflow(), - .inexact(), - .chainout_overflow(), - .chainout_invalid(), - .chainout_underflow(), - .chainout_inexact(), - .resulta(result_sub), - .chainout() + acl_fsub fsub ( + .clk (clk), + .areset (reset), + .en (enable), + .a (dataa[i]), + .b (datab[i]), + .q (result_sub) ); - defparam mac_fp_sub.operation_mode = "sp_add"; - defparam mac_fp_sub.use_chainin = "false"; - defparam mac_fp_sub.adder_subtract = "true"; - defparam mac_fp_sub.ax_clock = "0"; - defparam mac_fp_sub.ay_clock = "0"; - defparam mac_fp_sub.az_clock = "none"; - defparam mac_fp_sub.output_clock = "0"; - defparam mac_fp_sub.accumulate_clock = "none"; - defparam mac_fp_sub.ax_chainin_pl_clock = "none"; - defparam mac_fp_sub.accum_pipeline_clock = "none"; - defparam mac_fp_sub.mult_pipeline_clock = "none"; - defparam mac_fp_sub.adder_input_clock = "0"; - defparam mac_fp_sub.accum_adder_clock = "none"; - twentynm_fp_mac mac_fp_mul ( - // inputs - .accumulate(), - .chainin_overflow(), - .chainin_invalid(), - .chainin_underflow(), - .chainin_inexact(), - .ax(), - .ay(datab[i]), - .az(dataa[i]), - .clk({2'b00, clk}), - .ena({2'b00, enable}), - .aclr({reset, reset}), - .chainin(), - // outputs - .overflow(), - .invalid(), - .underflow(), - .inexact(), - .chainout_overflow(), - .chainout_invalid(), - .chainout_underflow(), - .chainout_inexact(), - .resulta(result_mul), - .chainout() + acl_fmul fmul ( + .clk (clk), + .areset (reset), + .en (enable), + .a (dataa[i]), + .b (datab[i]), + .q (result_mul) ); - defparam mac_fp_mul.operation_mode = "sp_mult"; - defparam mac_fp_mul.use_chainin = "false"; - defparam mac_fp_mul.adder_subtract = "false"; - defparam mac_fp_mul.ax_clock = "none"; - defparam mac_fp_mul.ay_clock = "0"; - defparam mac_fp_mul.az_clock = "0"; - defparam mac_fp_mul.output_clock = "0"; - defparam mac_fp_mul.accumulate_clock = "none"; - defparam mac_fp_mul.ax_chainin_pl_clock = "none"; - defparam mac_fp_mul.accum_pipeline_clock = "none"; - defparam mac_fp_mul.mult_pipeline_clock = "0"; - defparam mac_fp_mul.adder_input_clock = "none"; - defparam mac_fp_mul.accum_adder_clock = "none"; `else integer fadd_h, fsub_h, fmul_h; initial begin @@ -185,7 +92,7 @@ module VX_fp_addmul #( .clk(clk), .reset (reset), .enable (enable), - .data_in ({valid_in, tag_in, do_sub, do_mul}), + .data_in ({valid_in, tag_in, do_sub, do_mul}), .data_out ({valid_out, tag_out, do_sub_r, do_mul_r}) ); diff --git a/hw/rtl/fp_cores/VX_fp_madd.v b/hw/rtl/fp_cores/VX_fp_madd.v index d65aeb6e..e5a1f8fd 100644 --- a/hw/rtl/fp_cores/VX_fp_madd.v +++ b/hw/rtl/fp_cores/VX_fp_madd.v @@ -41,85 +41,25 @@ module VX_fp_madd #( wire [31:0] result_msub; `ifdef QUARTUS - twentynm_fp_mac mac_fp_madd ( - // inputs - .accumulate(), - .chainin_overflow(), - .chainin_invalid(), - .chainin_underflow(), - .chainin_inexact(), - .ax(datac[i]), - .ay(datab[i]), - .az(dataa[i]), - .clk({2'b00, clk}), - .ena({2'b00, enable}), - .aclr({reset, reset}), - .chainin(), - // outputs - .overflow(), - .invalid(), - .underflow(), - .inexact(), - .chainout_overflow(), - .chainout_invalid(), - .chainout_underflow(), - .chainout_inexact(), - .resulta(result_madd), - .chainout() + acl_fmadd fmadd ( + .clk (clk), + .areset (reset), + .en (enable), + .a (dataa[i]), + .b (datab[i]), + .c (datac[i]), + .q (result_madd) ); - defparam mac_fp_madd.operation_mode = "sp_mult_add"; - defparam mac_fp_madd.use_chainin = "false"; - defparam mac_fp_madd.adder_subtract = "false"; - defparam mac_fp_madd.ax_clock = "0"; - defparam mac_fp_madd.ay_clock = "0"; - defparam mac_fp_madd.az_clock = "0"; - defparam mac_fp_madd.output_clock = "0"; - defparam mac_fp_madd.accumulate_clock = "none"; - defparam mac_fp_madd.ax_chainin_pl_clock = "0"; - defparam mac_fp_madd.accum_pipeline_clock = "none"; - defparam mac_fp_madd.mult_pipeline_clock = "0"; - defparam mac_fp_madd.adder_input_clock = "0"; - defparam mac_fp_madd.accum_adder_clock = "none"; - twentynm_fp_mac mac_fp_msub ( - // inputs - .accumulate(), - .chainin_overflow(), - .chainin_invalid(), - .chainin_underflow(), - .chainin_inexact(), - .ax(datac[i]), - .ay(datab[i]), - .az(dataa[i]), - .clk({2'b00, clk}), - .ena({2'b00, enable}), - .aclr({reset, reset}), - .chainin(), - // outputs - .overflow(), - .invalid(), - .underflow(), - .inexact(), - .chainout_overflow(), - .chainout_invalid(), - .chainout_underflow(), - .chainout_inexact(), - .resulta(result_msub), - .chainout() + acl_fmsub fmsub ( + .clk (clk), + .areset (reset), + .en (enable), + .a (dataa[i]), + .b (datab[i]), + .c (datac[i]), + .q (result_msub) ); - defparam mac_fp_msub.operation_mode = "sp_mult_add"; - defparam mac_fp_msub.use_chainin = "false"; - defparam mac_fp_msub.adder_subtract = "true"; - defparam mac_fp_msub.ax_clock = "0"; - defparam mac_fp_msub.ay_clock = "0"; - defparam mac_fp_msub.az_clock = "0"; - defparam mac_fp_msub.output_clock = "0"; - defparam mac_fp_msub.accumulate_clock = "none"; - defparam mac_fp_msub.ax_chainin_pl_clock = "0"; - defparam mac_fp_msub.accum_pipeline_clock = "none"; - defparam mac_fp_msub.mult_pipeline_clock = "0"; - defparam mac_fp_msub.adder_input_clock = "0"; - defparam mac_fp_msub.accum_adder_clock = "none"; `else integer fmadd_h, fmsub_h; initial begin @@ -145,7 +85,7 @@ module VX_fp_madd #( .clk(clk), .reset (reset), .enable (enable), - .data_in ({valid_in, tag_in, do_sub, do_neg}), + .data_in ({valid_in, tag_in, do_sub, do_neg}), .data_out ({valid_out, tag_out, do_sub_r, do_neg_r}) ); diff --git a/hw/rtl/fp_cores/altera/acl_fdiv.sv b/hw/rtl/fp_cores/altera/acl_fdiv.sv deleted file mode 100644 index acba3a52..00000000 --- a/hw/rtl/fp_cores/altera/acl_fdiv.sv +++ /dev/null @@ -1,1592 +0,0 @@ -// ------------------------------------------------------------------------- -// High Level Design Compiler for Intel(R) FPGAs Version 17.1 (Release Build #273) -// Quartus Prime development tool and MATLAB/Simulink Interface -// -// Legal Notice: Copyright 2017 Intel Corporation. All rights reserved. -// Your use of Intel Corporation's design tools, logic functions and other -// software and tools, and its AMPP partner logic functions, and any output -// files any of the foregoing (including device programming or simulation -// files), and any associated documentation or information are expressly -// subject to the terms and conditions of the Intel FPGA Software License -// Agreement, Intel MegaCore Function License Agreement, or other applicable -// license agreement, including, without limitation, that your use is for -// the sole purpose of programming logic devices manufactured by Intel -// and sold by Intel or its authorized distributors. Please refer to the -// applicable agreement for further details. -// --------------------------------------------------------------------------- - -// SystemVerilog created from acl_fdiv -// SystemVerilog created on Wed Dec 9 01:17:51 2020 - - -(* altera_attribute = "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410; -name MESSAGE_DISABLE 113007; -name MESSAGE_DISABLE 10958" *) -module acl_fdiv ( - input wire [31:0] a, - input wire [31:0] b, - input wire [0:0] en, - output wire [31:0] q, - input wire clk, - input wire areset - ); - - wire [0:0] GND_q; - wire [0:0] VCC_q; - wire [7:0] cstBiasM1_uid6_fpDivTest_q; - wire [7:0] expX_uid9_fpDivTest_b; - wire [22:0] fracX_uid10_fpDivTest_b; - wire [0:0] signX_uid11_fpDivTest_b; - wire [7:0] expY_uid12_fpDivTest_b; - wire [22:0] fracY_uid13_fpDivTest_b; - wire [0:0] signY_uid14_fpDivTest_b; - wire [22:0] paddingY_uid15_fpDivTest_q; - wire [23:0] updatedY_uid16_fpDivTest_q; - wire [23:0] fracYZero_uid15_fpDivTest_a; - wire [0:0] fracYZero_uid15_fpDivTest_qi; - reg [0:0] fracYZero_uid15_fpDivTest_q; - wire [7:0] cstAllOWE_uid18_fpDivTest_q; - wire [7:0] cstAllZWE_uid20_fpDivTest_q; - wire [0:0] excZ_x_uid23_fpDivTest_qi; - reg [0:0] excZ_x_uid23_fpDivTest_q; - wire [0:0] expXIsMax_uid24_fpDivTest_qi; - reg [0:0] expXIsMax_uid24_fpDivTest_q; - wire [0:0] fracXIsZero_uid25_fpDivTest_qi; - reg [0:0] fracXIsZero_uid25_fpDivTest_q; - wire [0:0] fracXIsNotZero_uid26_fpDivTest_q; - wire [0:0] excI_x_uid27_fpDivTest_q; - wire [0:0] excN_x_uid28_fpDivTest_q; - wire [0:0] invExpXIsMax_uid29_fpDivTest_q; - wire [0:0] InvExpXIsZero_uid30_fpDivTest_q; - wire [0:0] excR_x_uid31_fpDivTest_q; - wire [0:0] excZ_y_uid37_fpDivTest_qi; - reg [0:0] excZ_y_uid37_fpDivTest_q; - wire [0:0] expXIsMax_uid38_fpDivTest_qi; - reg [0:0] expXIsMax_uid38_fpDivTest_q; - wire [0:0] fracXIsZero_uid39_fpDivTest_qi; - reg [0:0] fracXIsZero_uid39_fpDivTest_q; - wire [0:0] fracXIsNotZero_uid40_fpDivTest_q; - wire [0:0] excI_y_uid41_fpDivTest_q; - wire [0:0] excN_y_uid42_fpDivTest_q; - wire [0:0] invExpXIsMax_uid43_fpDivTest_q; - wire [0:0] InvExpXIsZero_uid44_fpDivTest_q; - wire [0:0] excR_y_uid45_fpDivTest_q; - wire [0:0] signR_uid46_fpDivTest_qi; - reg [0:0] signR_uid46_fpDivTest_q; - wire [8:0] expXmY_uid47_fpDivTest_a; - wire [8:0] expXmY_uid47_fpDivTest_b; - logic [8:0] expXmY_uid47_fpDivTest_o; - wire [8:0] expXmY_uid47_fpDivTest_q; - wire [10:0] expR_uid48_fpDivTest_a; - wire [10:0] expR_uid48_fpDivTest_b; - logic [10:0] expR_uid48_fpDivTest_o; - wire [9:0] expR_uid48_fpDivTest_q; - wire [8:0] yAddr_uid51_fpDivTest_b; - wire [13:0] yPE_uid52_fpDivTest_b; - wire [0:0] fracYPostZ_uid56_fpDivTest_qi; - reg [0:0] fracYPostZ_uid56_fpDivTest_q; - wire [23:0] lOAdded_uid58_fpDivTest_q; - wire [1:0] oFracXSE_bottomExtension_uid61_fpDivTest_q; - wire [25:0] oFracXSE_mergedSignalTM_uid63_fpDivTest_q; - wire [0:0] divValPreNormTrunc_uid66_fpDivTest_s; - reg [25:0] divValPreNormTrunc_uid66_fpDivTest_q; - wire [0:0] norm_uid67_fpDivTest_b; - wire [24:0] divValPreNormHigh_uid68_fpDivTest_in; - wire [23:0] divValPreNormHigh_uid68_fpDivTest_b; - wire [23:0] divValPreNormLow_uid69_fpDivTest_in; - wire [23:0] divValPreNormLow_uid69_fpDivTest_b; - wire [0:0] normFracRnd_uid70_fpDivTest_s; - reg [23:0] normFracRnd_uid70_fpDivTest_q; - wire [33:0] expFracRnd_uid71_fpDivTest_q; - wire [24:0] rndOp_uid75_fpDivTest_q; - wire [35:0] expFracPostRnd_uid76_fpDivTest_a; - wire [35:0] expFracPostRnd_uid76_fpDivTest_b; - logic [35:0] expFracPostRnd_uid76_fpDivTest_o; - wire [34:0] expFracPostRnd_uid76_fpDivTest_q; - wire [23:0] fracRPreExc_uid78_fpDivTest_in; - wire [22:0] fracRPreExc_uid78_fpDivTest_b; - wire [31:0] excRPreExc_uid79_fpDivTest_in; - wire [7:0] excRPreExc_uid79_fpDivTest_b; - wire [10:0] expRExt_uid80_fpDivTest_b; - wire [12:0] expUdf_uid81_fpDivTest_a; - wire [12:0] expUdf_uid81_fpDivTest_b; - logic [12:0] expUdf_uid81_fpDivTest_o; - wire [0:0] expUdf_uid81_fpDivTest_n; - wire [12:0] expOvf_uid84_fpDivTest_a; - wire [12:0] expOvf_uid84_fpDivTest_b; - logic [12:0] expOvf_uid84_fpDivTest_o; - wire [0:0] expOvf_uid84_fpDivTest_n; - wire [0:0] zeroOverReg_uid85_fpDivTest_q; - wire [0:0] regOverRegWithUf_uid86_fpDivTest_q; - wire [0:0] xRegOrZero_uid87_fpDivTest_q; - wire [0:0] regOrZeroOverInf_uid88_fpDivTest_q; - wire [0:0] excRZero_uid89_fpDivTest_q; - wire [0:0] excXRYZ_uid90_fpDivTest_q; - wire [0:0] excXRYROvf_uid91_fpDivTest_q; - wire [0:0] excXIYZ_uid92_fpDivTest_q; - wire [0:0] excXIYR_uid93_fpDivTest_q; - wire [0:0] excRInf_uid94_fpDivTest_q; - wire [0:0] excXZYZ_uid95_fpDivTest_q; - wire [0:0] excXIYI_uid96_fpDivTest_q; - wire [0:0] excRNaN_uid97_fpDivTest_q; - wire [2:0] concExc_uid98_fpDivTest_q; - reg [1:0] excREnc_uid99_fpDivTest_q; - wire [22:0] oneFracRPostExc2_uid100_fpDivTest_q; - wire [1:0] fracRPostExc_uid103_fpDivTest_s; - reg [22:0] fracRPostExc_uid103_fpDivTest_q; - wire [1:0] expRPostExc_uid107_fpDivTest_s; - reg [7:0] expRPostExc_uid107_fpDivTest_q; - wire [0:0] invExcRNaN_uid108_fpDivTest_q; - wire [0:0] sRPostExc_uid109_fpDivTest_qi; - reg [0:0] sRPostExc_uid109_fpDivTest_q; - wire [31:0] divR_uid110_fpDivTest_q; - wire [11:0] yT1_uid124_invPolyEval_b; - wire [0:0] lowRangeB_uid126_invPolyEval_in; - wire [0:0] lowRangeB_uid126_invPolyEval_b; - wire [11:0] highBBits_uid127_invPolyEval_b; - wire [21:0] s1sumAHighB_uid128_invPolyEval_a; - wire [21:0] s1sumAHighB_uid128_invPolyEval_b; - logic [21:0] s1sumAHighB_uid128_invPolyEval_o; - wire [21:0] s1sumAHighB_uid128_invPolyEval_q; - wire [22:0] s1_uid129_invPolyEval_q; - wire [1:0] lowRangeB_uid132_invPolyEval_in; - wire [1:0] lowRangeB_uid132_invPolyEval_b; - wire [21:0] highBBits_uid133_invPolyEval_b; - wire [31:0] s2sumAHighB_uid134_invPolyEval_a; - wire [31:0] s2sumAHighB_uid134_invPolyEval_b; - logic [31:0] s2sumAHighB_uid134_invPolyEval_o; - wire [31:0] s2sumAHighB_uid134_invPolyEval_q; - wire [33:0] s2_uid135_invPolyEval_q; - wire [25:0] osig_uid138_prodDivPreNormProd_uid60_fpDivTest_b; - wire [12:0] osig_uid141_pT1_uid125_invPolyEval_b; - wire [23:0] osig_uid144_pT2_uid131_invPolyEval_b; - wire memoryC0_uid112_invTables_lutmem_reset0; - wire [30:0] memoryC0_uid112_invTables_lutmem_ia; - wire [8:0] memoryC0_uid112_invTables_lutmem_aa; - wire [8:0] memoryC0_uid112_invTables_lutmem_ab; - wire [30:0] memoryC0_uid112_invTables_lutmem_ir; - wire [30:0] memoryC0_uid112_invTables_lutmem_r; - wire memoryC1_uid115_invTables_lutmem_reset0; - wire [20:0] memoryC1_uid115_invTables_lutmem_ia; - wire [8:0] memoryC1_uid115_invTables_lutmem_aa; - wire [8:0] memoryC1_uid115_invTables_lutmem_ab; - wire [20:0] memoryC1_uid115_invTables_lutmem_ir; - wire [20:0] memoryC1_uid115_invTables_lutmem_r; - wire memoryC2_uid118_invTables_lutmem_reset0; - wire [11:0] memoryC2_uid118_invTables_lutmem_ia; - wire [8:0] memoryC2_uid118_invTables_lutmem_aa; - wire [8:0] memoryC2_uid118_invTables_lutmem_ab; - wire [11:0] memoryC2_uid118_invTables_lutmem_ir; - wire [11:0] memoryC2_uid118_invTables_lutmem_r; - wire prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_reset; - (* preserve, altera_attribute = "-name allow_synch_ctrl_usage off" *) reg [25:0] prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_a0 [0:0]; - (* preserve, altera_attribute = "-name allow_synch_ctrl_usage off" *) reg [25:0] prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_a1 [0:0]; - (* preserve, altera_attribute = "-name allow_synch_ctrl_usage off" *) reg [23:0] prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_c0 [0:0]; - (* preserve, altera_attribute = "-name allow_synch_ctrl_usage off" *) reg [23:0] prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_c1 [0:0]; - wire [49:0] prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_p [0:0]; - wire [49:0] prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_u [0:0]; - wire [49:0] prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_w [0:0]; - wire [49:0] prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_x [0:0]; - wire [49:0] prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_y [0:0]; - reg [49:0] prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_s [0:0]; - wire [49:0] prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_qq; - wire [49:0] prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_q; - wire prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_ena0; - wire prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_ena1; - wire prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_ena2; - wire prodXY_uid140_pT1_uid125_invPolyEval_cma_reset; - (* preserve, altera_attribute = "-name allow_synch_ctrl_usage off" *) reg [11:0] prodXY_uid140_pT1_uid125_invPolyEval_cma_a0 [0:0]; - (* preserve, altera_attribute = "-name allow_synch_ctrl_usage off" *) reg [11:0] prodXY_uid140_pT1_uid125_invPolyEval_cma_a1 [0:0]; - (* preserve, altera_attribute = "-name allow_synch_ctrl_usage off" *) reg signed [11:0] prodXY_uid140_pT1_uid125_invPolyEval_cma_c0 [0:0]; - (* preserve, altera_attribute = "-name allow_synch_ctrl_usage off" *) reg signed [11:0] prodXY_uid140_pT1_uid125_invPolyEval_cma_c1 [0:0]; - wire signed [12:0] prodXY_uid140_pT1_uid125_invPolyEval_cma_l [0:0]; - wire signed [24:0] prodXY_uid140_pT1_uid125_invPolyEval_cma_p [0:0]; - wire signed [24:0] prodXY_uid140_pT1_uid125_invPolyEval_cma_u [0:0]; - wire signed [24:0] prodXY_uid140_pT1_uid125_invPolyEval_cma_w [0:0]; - wire signed [24:0] prodXY_uid140_pT1_uid125_invPolyEval_cma_x [0:0]; - wire signed [24:0] prodXY_uid140_pT1_uid125_invPolyEval_cma_y [0:0]; - reg signed [24:0] prodXY_uid140_pT1_uid125_invPolyEval_cma_s [0:0]; - wire [23:0] prodXY_uid140_pT1_uid125_invPolyEval_cma_qq; - wire [23:0] prodXY_uid140_pT1_uid125_invPolyEval_cma_q; - wire prodXY_uid140_pT1_uid125_invPolyEval_cma_ena0; - wire prodXY_uid140_pT1_uid125_invPolyEval_cma_ena1; - wire prodXY_uid140_pT1_uid125_invPolyEval_cma_ena2; - wire prodXY_uid143_pT2_uid131_invPolyEval_cma_reset; - (* preserve, altera_attribute = "-name allow_synch_ctrl_usage off" *) reg [13:0] prodXY_uid143_pT2_uid131_invPolyEval_cma_a0 [0:0]; - (* preserve, altera_attribute = "-name allow_synch_ctrl_usage off" *) reg [13:0] prodXY_uid143_pT2_uid131_invPolyEval_cma_a1 [0:0]; - (* preserve, altera_attribute = "-name allow_synch_ctrl_usage off" *) reg signed [22:0] prodXY_uid143_pT2_uid131_invPolyEval_cma_c0 [0:0]; - (* preserve, altera_attribute = "-name allow_synch_ctrl_usage off" *) reg signed [22:0] prodXY_uid143_pT2_uid131_invPolyEval_cma_c1 [0:0]; - wire signed [14:0] prodXY_uid143_pT2_uid131_invPolyEval_cma_l [0:0]; - wire signed [37:0] prodXY_uid143_pT2_uid131_invPolyEval_cma_p [0:0]; - wire signed [37:0] prodXY_uid143_pT2_uid131_invPolyEval_cma_u [0:0]; - wire signed [37:0] prodXY_uid143_pT2_uid131_invPolyEval_cma_w [0:0]; - wire signed [37:0] prodXY_uid143_pT2_uid131_invPolyEval_cma_x [0:0]; - wire signed [37:0] prodXY_uid143_pT2_uid131_invPolyEval_cma_y [0:0]; - reg signed [37:0] prodXY_uid143_pT2_uid131_invPolyEval_cma_s [0:0]; - wire [36:0] prodXY_uid143_pT2_uid131_invPolyEval_cma_qq; - wire [36:0] prodXY_uid143_pT2_uid131_invPolyEval_cma_q; - wire prodXY_uid143_pT2_uid131_invPolyEval_cma_ena0; - wire prodXY_uid143_pT2_uid131_invPolyEval_cma_ena1; - wire prodXY_uid143_pT2_uid131_invPolyEval_cma_ena2; - wire [31:0] invY_uid54_fpDivTest_merged_bit_select_in; - wire [25:0] invY_uid54_fpDivTest_merged_bit_select_b; - wire [0:0] invY_uid54_fpDivTest_merged_bit_select_c; - reg [25:0] redist0_invY_uid54_fpDivTest_merged_bit_select_b_1_q; - reg [0:0] redist1_lowRangeB_uid126_invPolyEval_b_1_q; - reg [7:0] redist2_excRPreExc_uid79_fpDivTest_b_1_q; - reg [22:0] redist3_fracRPreExc_uid78_fpDivTest_b_1_q; - reg [23:0] redist4_lOAdded_uid58_fpDivTest_q_3_q; - reg [0:0] redist5_fracYPostZ_uid56_fpDivTest_q_4_q; - reg [13:0] redist6_yPE_uid52_fpDivTest_b_2_q; - reg [8:0] redist8_yAddr_uid51_fpDivTest_b_3_q; - reg [8:0] redist9_yAddr_uid51_fpDivTest_b_7_q; - reg [0:0] redist11_signR_uid46_fpDivTest_q_14_q; - reg [0:0] redist12_fracXIsZero_uid39_fpDivTest_q_14_q; - reg [0:0] redist13_expXIsMax_uid38_fpDivTest_q_14_q; - reg [0:0] redist14_excZ_y_uid37_fpDivTest_q_14_q; - reg [0:0] redist15_fracXIsZero_uid25_fpDivTest_q_4_q; - reg [0:0] redist16_expXIsMax_uid24_fpDivTest_q_14_q; - reg [0:0] redist17_excZ_x_uid23_fpDivTest_q_14_q; - reg [0:0] redist18_fracYZero_uid15_fpDivTest_q_9_q; - wire redist7_yPE_uid52_fpDivTest_b_6_mem_reset0; - wire [13:0] redist7_yPE_uid52_fpDivTest_b_6_mem_ia; - wire [1:0] redist7_yPE_uid52_fpDivTest_b_6_mem_aa; - wire [1:0] redist7_yPE_uid52_fpDivTest_b_6_mem_ab; - wire [13:0] redist7_yPE_uid52_fpDivTest_b_6_mem_iq; - wire [13:0] redist7_yPE_uid52_fpDivTest_b_6_mem_q; - wire [1:0] redist7_yPE_uid52_fpDivTest_b_6_rdcnt_q; - (* preserve *) reg [1:0] redist7_yPE_uid52_fpDivTest_b_6_rdcnt_i; - (* preserve *) reg redist7_yPE_uid52_fpDivTest_b_6_rdcnt_eq; - wire [0:0] redist7_yPE_uid52_fpDivTest_b_6_rdmux_s; - reg [1:0] redist7_yPE_uid52_fpDivTest_b_6_rdmux_q; - reg [1:0] redist7_yPE_uid52_fpDivTest_b_6_wraddr_q; - wire [1:0] redist7_yPE_uid52_fpDivTest_b_6_mem_last_q; - wire [0:0] redist7_yPE_uid52_fpDivTest_b_6_cmp_q; - reg [0:0] redist7_yPE_uid52_fpDivTest_b_6_cmpReg_q; - wire [0:0] redist7_yPE_uid52_fpDivTest_b_6_notEnable_q; - wire [0:0] redist7_yPE_uid52_fpDivTest_b_6_nor_q; - (* preserve_syn_only *) reg [0:0] redist7_yPE_uid52_fpDivTest_b_6_sticky_ena_q; - wire [0:0] redist7_yPE_uid52_fpDivTest_b_6_enaAnd_q; - reg [8:0] redist10_expXmY_uid47_fpDivTest_q_13_outputreg_q; - wire redist10_expXmY_uid47_fpDivTest_q_13_mem_reset0; - wire [8:0] redist10_expXmY_uid47_fpDivTest_q_13_mem_ia; - wire [3:0] redist10_expXmY_uid47_fpDivTest_q_13_mem_aa; - wire [3:0] redist10_expXmY_uid47_fpDivTest_q_13_mem_ab; - wire [8:0] redist10_expXmY_uid47_fpDivTest_q_13_mem_iq; - wire [8:0] redist10_expXmY_uid47_fpDivTest_q_13_mem_q; - wire [3:0] redist10_expXmY_uid47_fpDivTest_q_13_rdcnt_q; - (* preserve *) reg [3:0] redist10_expXmY_uid47_fpDivTest_q_13_rdcnt_i; - (* preserve *) reg redist10_expXmY_uid47_fpDivTest_q_13_rdcnt_eq; - wire [0:0] redist10_expXmY_uid47_fpDivTest_q_13_rdmux_s; - reg [3:0] redist10_expXmY_uid47_fpDivTest_q_13_rdmux_q; - reg [3:0] redist10_expXmY_uid47_fpDivTest_q_13_wraddr_q; - wire [4:0] redist10_expXmY_uid47_fpDivTest_q_13_mem_last_q; - wire [4:0] redist10_expXmY_uid47_fpDivTest_q_13_cmp_b; - wire [0:0] redist10_expXmY_uid47_fpDivTest_q_13_cmp_q; - reg [0:0] redist10_expXmY_uid47_fpDivTest_q_13_cmpReg_q; - wire [0:0] redist10_expXmY_uid47_fpDivTest_q_13_notEnable_q; - wire [0:0] redist10_expXmY_uid47_fpDivTest_q_13_nor_q; - (* preserve_syn_only *) reg [0:0] redist10_expXmY_uid47_fpDivTest_q_13_sticky_ena_q; - wire [0:0] redist10_expXmY_uid47_fpDivTest_q_13_enaAnd_q; - wire redist19_fracX_uid10_fpDivTest_b_10_mem_reset0; - wire [22:0] redist19_fracX_uid10_fpDivTest_b_10_mem_ia; - wire [3:0] redist19_fracX_uid10_fpDivTest_b_10_mem_aa; - wire [3:0] redist19_fracX_uid10_fpDivTest_b_10_mem_ab; - wire [22:0] redist19_fracX_uid10_fpDivTest_b_10_mem_iq; - wire [22:0] redist19_fracX_uid10_fpDivTest_b_10_mem_q; - wire [3:0] redist19_fracX_uid10_fpDivTest_b_10_rdcnt_q; - (* preserve *) reg [3:0] redist19_fracX_uid10_fpDivTest_b_10_rdcnt_i; - (* preserve *) reg redist19_fracX_uid10_fpDivTest_b_10_rdcnt_eq; - wire [0:0] redist19_fracX_uid10_fpDivTest_b_10_rdmux_s; - reg [3:0] redist19_fracX_uid10_fpDivTest_b_10_rdmux_q; - reg [3:0] redist19_fracX_uid10_fpDivTest_b_10_wraddr_q; - wire [3:0] redist19_fracX_uid10_fpDivTest_b_10_mem_last_q; - wire [0:0] redist19_fracX_uid10_fpDivTest_b_10_cmp_q; - reg [0:0] redist19_fracX_uid10_fpDivTest_b_10_cmpReg_q; - wire [0:0] redist19_fracX_uid10_fpDivTest_b_10_notEnable_q; - wire [0:0] redist19_fracX_uid10_fpDivTest_b_10_nor_q; - (* preserve_syn_only *) reg [0:0] redist19_fracX_uid10_fpDivTest_b_10_sticky_ena_q; - wire [0:0] redist19_fracX_uid10_fpDivTest_b_10_enaAnd_q; - - - // fracY_uid13_fpDivTest(BITSELECT,12)@0 - assign fracY_uid13_fpDivTest_b = b[22:0]; - - // paddingY_uid15_fpDivTest(CONSTANT,14) - assign paddingY_uid15_fpDivTest_q = 23'b00000000000000000000000; - - // fracXIsZero_uid39_fpDivTest(LOGICAL,38)@0 + 1 - assign fracXIsZero_uid39_fpDivTest_qi = paddingY_uid15_fpDivTest_q == fracY_uid13_fpDivTest_b ? 1'b1 : 1'b0; - dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") ) - fracXIsZero_uid39_fpDivTest_delay ( .xin(fracXIsZero_uid39_fpDivTest_qi), .xout(fracXIsZero_uid39_fpDivTest_q), .ena(en[0]), .clk(clk), .aclr(areset) ); - - // redist12_fracXIsZero_uid39_fpDivTest_q_14(DELAY,164) - dspba_delay_ver #( .width(1), .depth(13), .reset_kind("ASYNC") ) - redist12_fracXIsZero_uid39_fpDivTest_q_14 ( .xin(fracXIsZero_uid39_fpDivTest_q), .xout(redist12_fracXIsZero_uid39_fpDivTest_q_14_q), .ena(en[0]), .clk(clk), .aclr(areset) ); - - // cstAllOWE_uid18_fpDivTest(CONSTANT,17) - assign cstAllOWE_uid18_fpDivTest_q = 8'b11111111; - - // expY_uid12_fpDivTest(BITSELECT,11)@0 - assign expY_uid12_fpDivTest_b = b[30:23]; - - // expXIsMax_uid38_fpDivTest(LOGICAL,37)@0 + 1 - assign expXIsMax_uid38_fpDivTest_qi = expY_uid12_fpDivTest_b == cstAllOWE_uid18_fpDivTest_q ? 1'b1 : 1'b0; - dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") ) - expXIsMax_uid38_fpDivTest_delay ( .xin(expXIsMax_uid38_fpDivTest_qi), .xout(expXIsMax_uid38_fpDivTest_q), .ena(en[0]), .clk(clk), .aclr(areset) ); - - // redist13_expXIsMax_uid38_fpDivTest_q_14(DELAY,165) - dspba_delay_ver #( .width(1), .depth(13), .reset_kind("ASYNC") ) - redist13_expXIsMax_uid38_fpDivTest_q_14 ( .xin(expXIsMax_uid38_fpDivTest_q), .xout(redist13_expXIsMax_uid38_fpDivTest_q_14_q), .ena(en[0]), .clk(clk), .aclr(areset) ); - - // excI_y_uid41_fpDivTest(LOGICAL,40)@14 - assign excI_y_uid41_fpDivTest_q = redist13_expXIsMax_uid38_fpDivTest_q_14_q & redist12_fracXIsZero_uid39_fpDivTest_q_14_q; - - // redist19_fracX_uid10_fpDivTest_b_10_notEnable(LOGICAL,202) - assign redist19_fracX_uid10_fpDivTest_b_10_notEnable_q = ~ (en); - - // redist19_fracX_uid10_fpDivTest_b_10_nor(LOGICAL,203) - assign redist19_fracX_uid10_fpDivTest_b_10_nor_q = ~ (redist19_fracX_uid10_fpDivTest_b_10_notEnable_q | redist19_fracX_uid10_fpDivTest_b_10_sticky_ena_q); - - // redist19_fracX_uid10_fpDivTest_b_10_mem_last(CONSTANT,199) - assign redist19_fracX_uid10_fpDivTest_b_10_mem_last_q = 4'b0111; - - // redist19_fracX_uid10_fpDivTest_b_10_cmp(LOGICAL,200) - assign redist19_fracX_uid10_fpDivTest_b_10_cmp_q = redist19_fracX_uid10_fpDivTest_b_10_mem_last_q == redist19_fracX_uid10_fpDivTest_b_10_rdmux_q ? 1'b1 : 1'b0; - - // redist19_fracX_uid10_fpDivTest_b_10_cmpReg(REG,201) - always @ (posedge clk or posedge areset) - begin - if (areset) - begin - redist19_fracX_uid10_fpDivTest_b_10_cmpReg_q <= 1'b0; - end - else if (en == 1'b1) - begin - redist19_fracX_uid10_fpDivTest_b_10_cmpReg_q <= redist19_fracX_uid10_fpDivTest_b_10_cmp_q; - end - end - - // redist19_fracX_uid10_fpDivTest_b_10_sticky_ena(REG,204) - always @ (posedge clk or posedge areset) - begin - if (areset) - begin - redist19_fracX_uid10_fpDivTest_b_10_sticky_ena_q <= 1'b0; - end - else if (redist19_fracX_uid10_fpDivTest_b_10_nor_q == 1'b1) - begin - redist19_fracX_uid10_fpDivTest_b_10_sticky_ena_q <= redist19_fracX_uid10_fpDivTest_b_10_cmpReg_q; - end - end - - // redist19_fracX_uid10_fpDivTest_b_10_enaAnd(LOGICAL,205) - assign redist19_fracX_uid10_fpDivTest_b_10_enaAnd_q = redist19_fracX_uid10_fpDivTest_b_10_sticky_ena_q & en; - - // redist19_fracX_uid10_fpDivTest_b_10_rdcnt(COUNTER,196) - // low=0, high=8, step=1, init=0 - always @ (posedge clk or posedge areset) - begin - if (areset) - begin - redist19_fracX_uid10_fpDivTest_b_10_rdcnt_i <= 4'd0; - redist19_fracX_uid10_fpDivTest_b_10_rdcnt_eq <= 1'b0; - end - else if (en == 1'b1) - begin - if (redist19_fracX_uid10_fpDivTest_b_10_rdcnt_i == 4'd7) - begin - redist19_fracX_uid10_fpDivTest_b_10_rdcnt_eq <= 1'b1; - end - else - begin - redist19_fracX_uid10_fpDivTest_b_10_rdcnt_eq <= 1'b0; - end - if (redist19_fracX_uid10_fpDivTest_b_10_rdcnt_eq == 1'b1) - begin - redist19_fracX_uid10_fpDivTest_b_10_rdcnt_i <= $unsigned(redist19_fracX_uid10_fpDivTest_b_10_rdcnt_i) + $unsigned(4'd8); - end - else - begin - redist19_fracX_uid10_fpDivTest_b_10_rdcnt_i <= $unsigned(redist19_fracX_uid10_fpDivTest_b_10_rdcnt_i) + $unsigned(4'd1); - end - end - end - assign redist19_fracX_uid10_fpDivTest_b_10_rdcnt_q = redist19_fracX_uid10_fpDivTest_b_10_rdcnt_i[3:0]; - - // redist19_fracX_uid10_fpDivTest_b_10_rdmux(MUX,197) - assign redist19_fracX_uid10_fpDivTest_b_10_rdmux_s = en; - always @(redist19_fracX_uid10_fpDivTest_b_10_rdmux_s or redist19_fracX_uid10_fpDivTest_b_10_wraddr_q or redist19_fracX_uid10_fpDivTest_b_10_rdcnt_q) - begin - unique case (redist19_fracX_uid10_fpDivTest_b_10_rdmux_s) - 1'b0 : redist19_fracX_uid10_fpDivTest_b_10_rdmux_q = redist19_fracX_uid10_fpDivTest_b_10_wraddr_q; - 1'b1 : redist19_fracX_uid10_fpDivTest_b_10_rdmux_q = redist19_fracX_uid10_fpDivTest_b_10_rdcnt_q; - default : redist19_fracX_uid10_fpDivTest_b_10_rdmux_q = 4'b0; - endcase - end - - // VCC(CONSTANT,1) - assign VCC_q = 1'b1; - - // fracX_uid10_fpDivTest(BITSELECT,9)@0 - assign fracX_uid10_fpDivTest_b = a[22:0]; - - // redist19_fracX_uid10_fpDivTest_b_10_wraddr(REG,198) - always @ (posedge clk or posedge areset) - begin - if (areset) - begin - redist19_fracX_uid10_fpDivTest_b_10_wraddr_q <= 4'b1000; - end - else - begin - redist19_fracX_uid10_fpDivTest_b_10_wraddr_q <= redist19_fracX_uid10_fpDivTest_b_10_rdmux_q; - end - end - - // redist19_fracX_uid10_fpDivTest_b_10_mem(DUALMEM,195) - assign redist19_fracX_uid10_fpDivTest_b_10_mem_ia = fracX_uid10_fpDivTest_b; - assign redist19_fracX_uid10_fpDivTest_b_10_mem_aa = redist19_fracX_uid10_fpDivTest_b_10_wraddr_q; - assign redist19_fracX_uid10_fpDivTest_b_10_mem_ab = redist19_fracX_uid10_fpDivTest_b_10_rdmux_q; - assign redist19_fracX_uid10_fpDivTest_b_10_mem_reset0 = areset; - altera_syncram #( - .ram_block_type("MLAB"), - .operation_mode("DUAL_PORT"), - .width_a(23), - .widthad_a(4), - .numwords_a(9), - .width_b(23), - .widthad_b(4), - .numwords_b(9), - .lpm_type("altera_syncram"), - .width_byteena_a(1), - .address_reg_b("CLOCK0"), - .indata_reg_b("CLOCK0"), - .rdcontrol_reg_b("CLOCK0"), - .byteena_reg_b("CLOCK0"), - .outdata_reg_b("CLOCK1"), - .outdata_aclr_b("CLEAR1"), - .clock_enable_input_a("NORMAL"), - .clock_enable_input_b("NORMAL"), - .clock_enable_output_b("NORMAL"), - .read_during_write_mode_mixed_ports("DONT_CARE"), - .power_up_uninitialized("TRUE"), - .intended_device_family("Arria 10") - ) redist19_fracX_uid10_fpDivTest_b_10_mem_dmem ( - .clocken1(redist19_fracX_uid10_fpDivTest_b_10_enaAnd_q[0]), - .clocken0(VCC_q[0]), - .clock0(clk), - .aclr1(redist19_fracX_uid10_fpDivTest_b_10_mem_reset0), - .clock1(clk), - .address_a(redist19_fracX_uid10_fpDivTest_b_10_mem_aa), - .data_a(redist19_fracX_uid10_fpDivTest_b_10_mem_ia), - .wren_a(en[0]), - .address_b(redist19_fracX_uid10_fpDivTest_b_10_mem_ab), - .q_b(redist19_fracX_uid10_fpDivTest_b_10_mem_iq), - .wren_b(), - .rden_a(), - .rden_b(), - .data_b(), - .clocken2(), - .clocken3(), - .aclr0(), - .addressstall_a(), - .addressstall_b(), - .byteena_a(), - .byteena_b(), - .eccencbypass(), - .eccencparity(), - .sclr(), - .address2_a(), - .address2_b(), - .q_a(), - .eccstatus() - ); - assign redist19_fracX_uid10_fpDivTest_b_10_mem_q = redist19_fracX_uid10_fpDivTest_b_10_mem_iq[22:0]; - - // fracXIsZero_uid25_fpDivTest(LOGICAL,24)@10 + 1 - assign fracXIsZero_uid25_fpDivTest_qi = paddingY_uid15_fpDivTest_q == redist19_fracX_uid10_fpDivTest_b_10_mem_q ? 1'b1 : 1'b0; - dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") ) - fracXIsZero_uid25_fpDivTest_delay ( .xin(fracXIsZero_uid25_fpDivTest_qi), .xout(fracXIsZero_uid25_fpDivTest_q), .ena(en[0]), .clk(clk), .aclr(areset) ); - - // redist15_fracXIsZero_uid25_fpDivTest_q_4(DELAY,167) - dspba_delay_ver #( .width(1), .depth(3), .reset_kind("ASYNC") ) - redist15_fracXIsZero_uid25_fpDivTest_q_4 ( .xin(fracXIsZero_uid25_fpDivTest_q), .xout(redist15_fracXIsZero_uid25_fpDivTest_q_4_q), .ena(en[0]), .clk(clk), .aclr(areset) ); - - // expX_uid9_fpDivTest(BITSELECT,8)@0 - assign expX_uid9_fpDivTest_b = a[30:23]; - - // expXIsMax_uid24_fpDivTest(LOGICAL,23)@0 + 1 - assign expXIsMax_uid24_fpDivTest_qi = expX_uid9_fpDivTest_b == cstAllOWE_uid18_fpDivTest_q ? 1'b1 : 1'b0; - dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") ) - expXIsMax_uid24_fpDivTest_delay ( .xin(expXIsMax_uid24_fpDivTest_qi), .xout(expXIsMax_uid24_fpDivTest_q), .ena(en[0]), .clk(clk), .aclr(areset) ); - - // redist16_expXIsMax_uid24_fpDivTest_q_14(DELAY,168) - dspba_delay_ver #( .width(1), .depth(13), .reset_kind("ASYNC") ) - redist16_expXIsMax_uid24_fpDivTest_q_14 ( .xin(expXIsMax_uid24_fpDivTest_q), .xout(redist16_expXIsMax_uid24_fpDivTest_q_14_q), .ena(en[0]), .clk(clk), .aclr(areset) ); - - // excI_x_uid27_fpDivTest(LOGICAL,26)@14 - assign excI_x_uid27_fpDivTest_q = redist16_expXIsMax_uid24_fpDivTest_q_14_q & redist15_fracXIsZero_uid25_fpDivTest_q_4_q; - - // excXIYI_uid96_fpDivTest(LOGICAL,95)@14 - assign excXIYI_uid96_fpDivTest_q = excI_x_uid27_fpDivTest_q & excI_y_uid41_fpDivTest_q; - - // fracXIsNotZero_uid40_fpDivTest(LOGICAL,39)@14 - assign fracXIsNotZero_uid40_fpDivTest_q = ~ (redist12_fracXIsZero_uid39_fpDivTest_q_14_q); - - // excN_y_uid42_fpDivTest(LOGICAL,41)@14 - assign excN_y_uid42_fpDivTest_q = redist13_expXIsMax_uid38_fpDivTest_q_14_q & fracXIsNotZero_uid40_fpDivTest_q; - - // fracXIsNotZero_uid26_fpDivTest(LOGICAL,25)@14 - assign fracXIsNotZero_uid26_fpDivTest_q = ~ (redist15_fracXIsZero_uid25_fpDivTest_q_4_q); - - // excN_x_uid28_fpDivTest(LOGICAL,27)@14 - assign excN_x_uid28_fpDivTest_q = redist16_expXIsMax_uid24_fpDivTest_q_14_q & fracXIsNotZero_uid26_fpDivTest_q; - - // cstAllZWE_uid20_fpDivTest(CONSTANT,19) - assign cstAllZWE_uid20_fpDivTest_q = 8'b00000000; - - // excZ_y_uid37_fpDivTest(LOGICAL,36)@0 + 1 - assign excZ_y_uid37_fpDivTest_qi = expY_uid12_fpDivTest_b == cstAllZWE_uid20_fpDivTest_q ? 1'b1 : 1'b0; - dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") ) - excZ_y_uid37_fpDivTest_delay ( .xin(excZ_y_uid37_fpDivTest_qi), .xout(excZ_y_uid37_fpDivTest_q), .ena(en[0]), .clk(clk), .aclr(areset) ); - - // redist14_excZ_y_uid37_fpDivTest_q_14(DELAY,166) - dspba_delay_ver #( .width(1), .depth(13), .reset_kind("ASYNC") ) - redist14_excZ_y_uid37_fpDivTest_q_14 ( .xin(excZ_y_uid37_fpDivTest_q), .xout(redist14_excZ_y_uid37_fpDivTest_q_14_q), .ena(en[0]), .clk(clk), .aclr(areset) ); - - // excZ_x_uid23_fpDivTest(LOGICAL,22)@0 + 1 - assign excZ_x_uid23_fpDivTest_qi = expX_uid9_fpDivTest_b == cstAllZWE_uid20_fpDivTest_q ? 1'b1 : 1'b0; - dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") ) - excZ_x_uid23_fpDivTest_delay ( .xin(excZ_x_uid23_fpDivTest_qi), .xout(excZ_x_uid23_fpDivTest_q), .ena(en[0]), .clk(clk), .aclr(areset) ); - - // redist17_excZ_x_uid23_fpDivTest_q_14(DELAY,169) - dspba_delay_ver #( .width(1), .depth(13), .reset_kind("ASYNC") ) - redist17_excZ_x_uid23_fpDivTest_q_14 ( .xin(excZ_x_uid23_fpDivTest_q), .xout(redist17_excZ_x_uid23_fpDivTest_q_14_q), .ena(en[0]), .clk(clk), .aclr(areset) ); - - // excXZYZ_uid95_fpDivTest(LOGICAL,94)@14 - assign excXZYZ_uid95_fpDivTest_q = redist17_excZ_x_uid23_fpDivTest_q_14_q & redist14_excZ_y_uid37_fpDivTest_q_14_q; - - // excRNaN_uid97_fpDivTest(LOGICAL,96)@14 - assign excRNaN_uid97_fpDivTest_q = excXZYZ_uid95_fpDivTest_q | excN_x_uid28_fpDivTest_q | excN_y_uid42_fpDivTest_q | excXIYI_uid96_fpDivTest_q; - - // invExcRNaN_uid108_fpDivTest(LOGICAL,107)@14 - assign invExcRNaN_uid108_fpDivTest_q = ~ (excRNaN_uid97_fpDivTest_q); - - // signY_uid14_fpDivTest(BITSELECT,13)@0 - assign signY_uid14_fpDivTest_b = b[31:31]; - - // signX_uid11_fpDivTest(BITSELECT,10)@0 - assign signX_uid11_fpDivTest_b = a[31:31]; - - // signR_uid46_fpDivTest(LOGICAL,45)@0 + 1 - assign signR_uid46_fpDivTest_qi = signX_uid11_fpDivTest_b ^ signY_uid14_fpDivTest_b; - dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") ) - signR_uid46_fpDivTest_delay ( .xin(signR_uid46_fpDivTest_qi), .xout(signR_uid46_fpDivTest_q), .ena(en[0]), .clk(clk), .aclr(areset) ); - - // redist11_signR_uid46_fpDivTest_q_14(DELAY,163) - dspba_delay_ver #( .width(1), .depth(13), .reset_kind("ASYNC") ) - redist11_signR_uid46_fpDivTest_q_14 ( .xin(signR_uid46_fpDivTest_q), .xout(redist11_signR_uid46_fpDivTest_q_14_q), .ena(en[0]), .clk(clk), .aclr(areset) ); - - // sRPostExc_uid109_fpDivTest(LOGICAL,108)@14 + 1 - assign sRPostExc_uid109_fpDivTest_qi = redist11_signR_uid46_fpDivTest_q_14_q & invExcRNaN_uid108_fpDivTest_q; - dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") ) - sRPostExc_uid109_fpDivTest_delay ( .xin(sRPostExc_uid109_fpDivTest_qi), .xout(sRPostExc_uid109_fpDivTest_q), .ena(en[0]), .clk(clk), .aclr(areset) ); - - // lOAdded_uid58_fpDivTest(BITJOIN,57)@10 - assign lOAdded_uid58_fpDivTest_q = {VCC_q, redist19_fracX_uid10_fpDivTest_b_10_mem_q}; - - // redist4_lOAdded_uid58_fpDivTest_q_3(DELAY,156) - dspba_delay_ver #( .width(24), .depth(3), .reset_kind("ASYNC") ) - redist4_lOAdded_uid58_fpDivTest_q_3 ( .xin(lOAdded_uid58_fpDivTest_q), .xout(redist4_lOAdded_uid58_fpDivTest_q_3_q), .ena(en[0]), .clk(clk), .aclr(areset) ); - - // oFracXSE_bottomExtension_uid61_fpDivTest(CONSTANT,60) - assign oFracXSE_bottomExtension_uid61_fpDivTest_q = 2'b00; - - // oFracXSE_mergedSignalTM_uid63_fpDivTest(BITJOIN,62)@13 - assign oFracXSE_mergedSignalTM_uid63_fpDivTest_q = {redist4_lOAdded_uid58_fpDivTest_q_3_q, oFracXSE_bottomExtension_uid61_fpDivTest_q}; - - // yAddr_uid51_fpDivTest(BITSELECT,50)@0 - assign yAddr_uid51_fpDivTest_b = fracY_uid13_fpDivTest_b[22:14]; - - // memoryC2_uid118_invTables_lutmem(DUALMEM,147)@0 + 2 - // in j@20000000 - assign memoryC2_uid118_invTables_lutmem_aa = yAddr_uid51_fpDivTest_b; - assign memoryC2_uid118_invTables_lutmem_reset0 = areset; - altera_syncram #( - .ram_block_type("M20K"), - .operation_mode("ROM"), - .width_a(12), - .widthad_a(9), - .numwords_a(512), - .lpm_type("altera_syncram"), - .width_byteena_a(1), - .outdata_reg_a("CLOCK0"), - .outdata_aclr_a("CLEAR0"), - .clock_enable_input_a("NORMAL"), - .power_up_uninitialized("FALSE"), - .init_file("acl_fdiv_memoryC2_uid118_invTables_lutmem.hex"), - .init_file_layout("PORT_A"), - .intended_device_family("Arria 10") - ) memoryC2_uid118_invTables_lutmem_dmem ( - .clocken0(en[0]), - .aclr0(memoryC2_uid118_invTables_lutmem_reset0), - .clock0(clk), - .address_a(memoryC2_uid118_invTables_lutmem_aa), - .q_a(memoryC2_uid118_invTables_lutmem_ir), - .wren_a(), - .wren_b(), - .rden_a(), - .rden_b(), - .data_a(), - .data_b(), - .address_b(), - .clock1(), - .clocken1(), - .clocken2(), - .clocken3(), - .aclr1(), - .addressstall_a(), - .addressstall_b(), - .byteena_a(), - .byteena_b(), - .eccencbypass(), - .eccencparity(), - .sclr(), - .address2_a(), - .address2_b(), - .q_b(), - .eccstatus() - ); - assign memoryC2_uid118_invTables_lutmem_r = memoryC2_uid118_invTables_lutmem_ir[11:0]; - - // yPE_uid52_fpDivTest(BITSELECT,51)@0 - assign yPE_uid52_fpDivTest_b = b[13:0]; - - // redist6_yPE_uid52_fpDivTest_b_2(DELAY,158) - dspba_delay_ver #( .width(14), .depth(2), .reset_kind("ASYNC") ) - redist6_yPE_uid52_fpDivTest_b_2 ( .xin(yPE_uid52_fpDivTest_b), .xout(redist6_yPE_uid52_fpDivTest_b_2_q), .ena(en[0]), .clk(clk), .aclr(areset) ); - - // yT1_uid124_invPolyEval(BITSELECT,123)@2 - assign yT1_uid124_invPolyEval_b = redist6_yPE_uid52_fpDivTest_b_2_q[13:2]; - - // prodXY_uid140_pT1_uid125_invPolyEval_cma(CHAINMULTADD,149)@2 + 3 - assign prodXY_uid140_pT1_uid125_invPolyEval_cma_reset = areset; - assign prodXY_uid140_pT1_uid125_invPolyEval_cma_ena0 = en[0]; - assign prodXY_uid140_pT1_uid125_invPolyEval_cma_ena1 = prodXY_uid140_pT1_uid125_invPolyEval_cma_ena0; - assign prodXY_uid140_pT1_uid125_invPolyEval_cma_ena2 = prodXY_uid140_pT1_uid125_invPolyEval_cma_ena0; - assign prodXY_uid140_pT1_uid125_invPolyEval_cma_l[0] = $signed({1'b0, prodXY_uid140_pT1_uid125_invPolyEval_cma_a1[0][11:0]}); - assign prodXY_uid140_pT1_uid125_invPolyEval_cma_p[0] = prodXY_uid140_pT1_uid125_invPolyEval_cma_l[0] * prodXY_uid140_pT1_uid125_invPolyEval_cma_c1[0]; - assign prodXY_uid140_pT1_uid125_invPolyEval_cma_u[0] = prodXY_uid140_pT1_uid125_invPolyEval_cma_p[0][24:0]; - assign prodXY_uid140_pT1_uid125_invPolyEval_cma_w[0] = prodXY_uid140_pT1_uid125_invPolyEval_cma_u[0]; - assign prodXY_uid140_pT1_uid125_invPolyEval_cma_x[0] = prodXY_uid140_pT1_uid125_invPolyEval_cma_w[0]; - assign prodXY_uid140_pT1_uid125_invPolyEval_cma_y[0] = prodXY_uid140_pT1_uid125_invPolyEval_cma_x[0]; - always @ (posedge clk or posedge areset) - begin - if (areset) - begin - prodXY_uid140_pT1_uid125_invPolyEval_cma_a0 <= '{default: '0}; - prodXY_uid140_pT1_uid125_invPolyEval_cma_c0 <= '{default: '0}; - end - else - begin - if (prodXY_uid140_pT1_uid125_invPolyEval_cma_ena0 == 1'b1) - begin - prodXY_uid140_pT1_uid125_invPolyEval_cma_a0[0] <= yT1_uid124_invPolyEval_b; - prodXY_uid140_pT1_uid125_invPolyEval_cma_c0[0] <= memoryC2_uid118_invTables_lutmem_r; - end - end - end - always @ (posedge clk or posedge areset) - begin - if (areset) - begin - prodXY_uid140_pT1_uid125_invPolyEval_cma_a1 <= '{default: '0}; - prodXY_uid140_pT1_uid125_invPolyEval_cma_c1 <= '{default: '0}; - end - else - begin - if (prodXY_uid140_pT1_uid125_invPolyEval_cma_ena2 == 1'b1) - begin - prodXY_uid140_pT1_uid125_invPolyEval_cma_a1 <= prodXY_uid140_pT1_uid125_invPolyEval_cma_a0; - prodXY_uid140_pT1_uid125_invPolyEval_cma_c1 <= prodXY_uid140_pT1_uid125_invPolyEval_cma_c0; - end - end - end - always @ (posedge clk or posedge areset) - begin - if (areset) - begin - prodXY_uid140_pT1_uid125_invPolyEval_cma_s <= '{default: '0}; - end - else - begin - if (prodXY_uid140_pT1_uid125_invPolyEval_cma_ena1 == 1'b1) - begin - prodXY_uid140_pT1_uid125_invPolyEval_cma_s[0] <= prodXY_uid140_pT1_uid125_invPolyEval_cma_y[0]; - end - end - end - dspba_delay_ver #( .width(24), .depth(0), .reset_kind("ASYNC") ) - prodXY_uid140_pT1_uid125_invPolyEval_cma_delay ( .xin(prodXY_uid140_pT1_uid125_invPolyEval_cma_s[0][23:0]), .xout(prodXY_uid140_pT1_uid125_invPolyEval_cma_qq), .ena(en[0]), .clk(clk), .aclr(areset) ); - assign prodXY_uid140_pT1_uid125_invPolyEval_cma_q = prodXY_uid140_pT1_uid125_invPolyEval_cma_qq[23:0]; - - // osig_uid141_pT1_uid125_invPolyEval(BITSELECT,140)@5 - assign osig_uid141_pT1_uid125_invPolyEval_b = prodXY_uid140_pT1_uid125_invPolyEval_cma_q[23:11]; - - // highBBits_uid127_invPolyEval(BITSELECT,126)@5 - assign highBBits_uid127_invPolyEval_b = osig_uid141_pT1_uid125_invPolyEval_b[12:1]; - - // redist8_yAddr_uid51_fpDivTest_b_3(DELAY,160) - dspba_delay_ver #( .width(9), .depth(3), .reset_kind("ASYNC") ) - redist8_yAddr_uid51_fpDivTest_b_3 ( .xin(yAddr_uid51_fpDivTest_b), .xout(redist8_yAddr_uid51_fpDivTest_b_3_q), .ena(en[0]), .clk(clk), .aclr(areset) ); - - // memoryC1_uid115_invTables_lutmem(DUALMEM,146)@3 + 2 - // in j@20000000 - assign memoryC1_uid115_invTables_lutmem_aa = redist8_yAddr_uid51_fpDivTest_b_3_q; - assign memoryC1_uid115_invTables_lutmem_reset0 = areset; - altera_syncram #( - .ram_block_type("M20K"), - .operation_mode("ROM"), - .width_a(21), - .widthad_a(9), - .numwords_a(512), - .lpm_type("altera_syncram"), - .width_byteena_a(1), - .outdata_reg_a("CLOCK0"), - .outdata_aclr_a("CLEAR0"), - .clock_enable_input_a("NORMAL"), - .power_up_uninitialized("FALSE"), - .init_file("acl_fdiv_memoryC1_uid115_invTables_lutmem.hex"), - .init_file_layout("PORT_A"), - .intended_device_family("Arria 10") - ) memoryC1_uid115_invTables_lutmem_dmem ( - .clocken0(en[0]), - .aclr0(memoryC1_uid115_invTables_lutmem_reset0), - .clock0(clk), - .address_a(memoryC1_uid115_invTables_lutmem_aa), - .q_a(memoryC1_uid115_invTables_lutmem_ir), - .wren_a(), - .wren_b(), - .rden_a(), - .rden_b(), - .data_a(), - .data_b(), - .address_b(), - .clock1(), - .clocken1(), - .clocken2(), - .clocken3(), - .aclr1(), - .addressstall_a(), - .addressstall_b(), - .byteena_a(), - .byteena_b(), - .eccencbypass(), - .eccencparity(), - .sclr(), - .address2_a(), - .address2_b(), - .q_b(), - .eccstatus() - ); - assign memoryC1_uid115_invTables_lutmem_r = memoryC1_uid115_invTables_lutmem_ir[20:0]; - - // s1sumAHighB_uid128_invPolyEval(ADD,127)@5 + 1 - assign s1sumAHighB_uid128_invPolyEval_a = {{1{memoryC1_uid115_invTables_lutmem_r[20]}}, memoryC1_uid115_invTables_lutmem_r}; - assign s1sumAHighB_uid128_invPolyEval_b = {{10{highBBits_uid127_invPolyEval_b[11]}}, highBBits_uid127_invPolyEval_b}; - always @ (posedge clk or posedge areset) - begin - if (areset) - begin - s1sumAHighB_uid128_invPolyEval_o <= 22'b0; - end - else if (en == 1'b1) - begin - s1sumAHighB_uid128_invPolyEval_o <= $signed(s1sumAHighB_uid128_invPolyEval_a) + $signed(s1sumAHighB_uid128_invPolyEval_b); - end - end - assign s1sumAHighB_uid128_invPolyEval_q = s1sumAHighB_uid128_invPolyEval_o[21:0]; - - // lowRangeB_uid126_invPolyEval(BITSELECT,125)@5 - assign lowRangeB_uid126_invPolyEval_in = osig_uid141_pT1_uid125_invPolyEval_b[0:0]; - assign lowRangeB_uid126_invPolyEval_b = lowRangeB_uid126_invPolyEval_in[0:0]; - - // redist1_lowRangeB_uid126_invPolyEval_b_1(DELAY,153) - dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") ) - redist1_lowRangeB_uid126_invPolyEval_b_1 ( .xin(lowRangeB_uid126_invPolyEval_b), .xout(redist1_lowRangeB_uid126_invPolyEval_b_1_q), .ena(en[0]), .clk(clk), .aclr(areset) ); - - // s1_uid129_invPolyEval(BITJOIN,128)@6 - assign s1_uid129_invPolyEval_q = {s1sumAHighB_uid128_invPolyEval_q, redist1_lowRangeB_uid126_invPolyEval_b_1_q}; - - // redist7_yPE_uid52_fpDivTest_b_6_notEnable(LOGICAL,179) - assign redist7_yPE_uid52_fpDivTest_b_6_notEnable_q = ~ (en); - - // redist7_yPE_uid52_fpDivTest_b_6_nor(LOGICAL,180) - assign redist7_yPE_uid52_fpDivTest_b_6_nor_q = ~ (redist7_yPE_uid52_fpDivTest_b_6_notEnable_q | redist7_yPE_uid52_fpDivTest_b_6_sticky_ena_q); - - // redist7_yPE_uid52_fpDivTest_b_6_mem_last(CONSTANT,176) - assign redist7_yPE_uid52_fpDivTest_b_6_mem_last_q = 2'b01; - - // redist7_yPE_uid52_fpDivTest_b_6_cmp(LOGICAL,177) - assign redist7_yPE_uid52_fpDivTest_b_6_cmp_q = redist7_yPE_uid52_fpDivTest_b_6_mem_last_q == redist7_yPE_uid52_fpDivTest_b_6_rdmux_q ? 1'b1 : 1'b0; - - // redist7_yPE_uid52_fpDivTest_b_6_cmpReg(REG,178) - always @ (posedge clk or posedge areset) - begin - if (areset) - begin - redist7_yPE_uid52_fpDivTest_b_6_cmpReg_q <= 1'b0; - end - else if (en == 1'b1) - begin - redist7_yPE_uid52_fpDivTest_b_6_cmpReg_q <= redist7_yPE_uid52_fpDivTest_b_6_cmp_q; - end - end - - // redist7_yPE_uid52_fpDivTest_b_6_sticky_ena(REG,181) - always @ (posedge clk or posedge areset) - begin - if (areset) - begin - redist7_yPE_uid52_fpDivTest_b_6_sticky_ena_q <= 1'b0; - end - else if (redist7_yPE_uid52_fpDivTest_b_6_nor_q == 1'b1) - begin - redist7_yPE_uid52_fpDivTest_b_6_sticky_ena_q <= redist7_yPE_uid52_fpDivTest_b_6_cmpReg_q; - end - end - - // redist7_yPE_uid52_fpDivTest_b_6_enaAnd(LOGICAL,182) - assign redist7_yPE_uid52_fpDivTest_b_6_enaAnd_q = redist7_yPE_uid52_fpDivTest_b_6_sticky_ena_q & en; - - // redist7_yPE_uid52_fpDivTest_b_6_rdcnt(COUNTER,173) - // low=0, high=2, step=1, init=0 - always @ (posedge clk or posedge areset) - begin - if (areset) - begin - redist7_yPE_uid52_fpDivTest_b_6_rdcnt_i <= 2'd0; - redist7_yPE_uid52_fpDivTest_b_6_rdcnt_eq <= 1'b0; - end - else if (en == 1'b1) - begin - if (redist7_yPE_uid52_fpDivTest_b_6_rdcnt_i == 2'd1) - begin - redist7_yPE_uid52_fpDivTest_b_6_rdcnt_eq <= 1'b1; - end - else - begin - redist7_yPE_uid52_fpDivTest_b_6_rdcnt_eq <= 1'b0; - end - if (redist7_yPE_uid52_fpDivTest_b_6_rdcnt_eq == 1'b1) - begin - redist7_yPE_uid52_fpDivTest_b_6_rdcnt_i <= $unsigned(redist7_yPE_uid52_fpDivTest_b_6_rdcnt_i) + $unsigned(2'd2); - end - else - begin - redist7_yPE_uid52_fpDivTest_b_6_rdcnt_i <= $unsigned(redist7_yPE_uid52_fpDivTest_b_6_rdcnt_i) + $unsigned(2'd1); - end - end - end - assign redist7_yPE_uid52_fpDivTest_b_6_rdcnt_q = redist7_yPE_uid52_fpDivTest_b_6_rdcnt_i[1:0]; - - // redist7_yPE_uid52_fpDivTest_b_6_rdmux(MUX,174) - assign redist7_yPE_uid52_fpDivTest_b_6_rdmux_s = en; - always @(redist7_yPE_uid52_fpDivTest_b_6_rdmux_s or redist7_yPE_uid52_fpDivTest_b_6_wraddr_q or redist7_yPE_uid52_fpDivTest_b_6_rdcnt_q) - begin - unique case (redist7_yPE_uid52_fpDivTest_b_6_rdmux_s) - 1'b0 : redist7_yPE_uid52_fpDivTest_b_6_rdmux_q = redist7_yPE_uid52_fpDivTest_b_6_wraddr_q; - 1'b1 : redist7_yPE_uid52_fpDivTest_b_6_rdmux_q = redist7_yPE_uid52_fpDivTest_b_6_rdcnt_q; - default : redist7_yPE_uid52_fpDivTest_b_6_rdmux_q = 2'b0; - endcase - end - - // redist7_yPE_uid52_fpDivTest_b_6_wraddr(REG,175) - always @ (posedge clk or posedge areset) - begin - if (areset) - begin - redist7_yPE_uid52_fpDivTest_b_6_wraddr_q <= 2'b10; - end - else - begin - redist7_yPE_uid52_fpDivTest_b_6_wraddr_q <= redist7_yPE_uid52_fpDivTest_b_6_rdmux_q; - end - end - - // redist7_yPE_uid52_fpDivTest_b_6_mem(DUALMEM,172) - assign redist7_yPE_uid52_fpDivTest_b_6_mem_ia = redist6_yPE_uid52_fpDivTest_b_2_q; - assign redist7_yPE_uid52_fpDivTest_b_6_mem_aa = redist7_yPE_uid52_fpDivTest_b_6_wraddr_q; - assign redist7_yPE_uid52_fpDivTest_b_6_mem_ab = redist7_yPE_uid52_fpDivTest_b_6_rdmux_q; - assign redist7_yPE_uid52_fpDivTest_b_6_mem_reset0 = areset; - altera_syncram #( - .ram_block_type("MLAB"), - .operation_mode("DUAL_PORT"), - .width_a(14), - .widthad_a(2), - .numwords_a(3), - .width_b(14), - .widthad_b(2), - .numwords_b(3), - .lpm_type("altera_syncram"), - .width_byteena_a(1), - .address_reg_b("CLOCK0"), - .indata_reg_b("CLOCK0"), - .rdcontrol_reg_b("CLOCK0"), - .byteena_reg_b("CLOCK0"), - .outdata_reg_b("CLOCK1"), - .outdata_aclr_b("CLEAR1"), - .clock_enable_input_a("NORMAL"), - .clock_enable_input_b("NORMAL"), - .clock_enable_output_b("NORMAL"), - .read_during_write_mode_mixed_ports("DONT_CARE"), - .power_up_uninitialized("TRUE"), - .intended_device_family("Arria 10") - ) redist7_yPE_uid52_fpDivTest_b_6_mem_dmem ( - .clocken1(redist7_yPE_uid52_fpDivTest_b_6_enaAnd_q[0]), - .clocken0(VCC_q[0]), - .clock0(clk), - .aclr1(redist7_yPE_uid52_fpDivTest_b_6_mem_reset0), - .clock1(clk), - .address_a(redist7_yPE_uid52_fpDivTest_b_6_mem_aa), - .data_a(redist7_yPE_uid52_fpDivTest_b_6_mem_ia), - .wren_a(en[0]), - .address_b(redist7_yPE_uid52_fpDivTest_b_6_mem_ab), - .q_b(redist7_yPE_uid52_fpDivTest_b_6_mem_iq), - .wren_b(), - .rden_a(), - .rden_b(), - .data_b(), - .clocken2(), - .clocken3(), - .aclr0(), - .addressstall_a(), - .addressstall_b(), - .byteena_a(), - .byteena_b(), - .eccencbypass(), - .eccencparity(), - .sclr(), - .address2_a(), - .address2_b(), - .q_a(), - .eccstatus() - ); - assign redist7_yPE_uid52_fpDivTest_b_6_mem_q = redist7_yPE_uid52_fpDivTest_b_6_mem_iq[13:0]; - - // prodXY_uid143_pT2_uid131_invPolyEval_cma(CHAINMULTADD,150)@6 + 3 - assign prodXY_uid143_pT2_uid131_invPolyEval_cma_reset = areset; - assign prodXY_uid143_pT2_uid131_invPolyEval_cma_ena0 = en[0]; - assign prodXY_uid143_pT2_uid131_invPolyEval_cma_ena1 = prodXY_uid143_pT2_uid131_invPolyEval_cma_ena0; - assign prodXY_uid143_pT2_uid131_invPolyEval_cma_ena2 = prodXY_uid143_pT2_uid131_invPolyEval_cma_ena0; - assign prodXY_uid143_pT2_uid131_invPolyEval_cma_l[0] = $signed({1'b0, prodXY_uid143_pT2_uid131_invPolyEval_cma_a1[0][13:0]}); - assign prodXY_uid143_pT2_uid131_invPolyEval_cma_p[0] = prodXY_uid143_pT2_uid131_invPolyEval_cma_l[0] * prodXY_uid143_pT2_uid131_invPolyEval_cma_c1[0]; - assign prodXY_uid143_pT2_uid131_invPolyEval_cma_u[0] = prodXY_uid143_pT2_uid131_invPolyEval_cma_p[0][37:0]; - assign prodXY_uid143_pT2_uid131_invPolyEval_cma_w[0] = prodXY_uid143_pT2_uid131_invPolyEval_cma_u[0]; - assign prodXY_uid143_pT2_uid131_invPolyEval_cma_x[0] = prodXY_uid143_pT2_uid131_invPolyEval_cma_w[0]; - assign prodXY_uid143_pT2_uid131_invPolyEval_cma_y[0] = prodXY_uid143_pT2_uid131_invPolyEval_cma_x[0]; - always @ (posedge clk or posedge areset) - begin - if (areset) - begin - prodXY_uid143_pT2_uid131_invPolyEval_cma_a0 <= '{default: '0}; - prodXY_uid143_pT2_uid131_invPolyEval_cma_c0 <= '{default: '0}; - end - else - begin - if (prodXY_uid143_pT2_uid131_invPolyEval_cma_ena0 == 1'b1) - begin - prodXY_uid143_pT2_uid131_invPolyEval_cma_a0[0] <= redist7_yPE_uid52_fpDivTest_b_6_mem_q; - prodXY_uid143_pT2_uid131_invPolyEval_cma_c0[0] <= s1_uid129_invPolyEval_q; - end - end - end - always @ (posedge clk or posedge areset) - begin - if (areset) - begin - prodXY_uid143_pT2_uid131_invPolyEval_cma_a1 <= '{default: '0}; - prodXY_uid143_pT2_uid131_invPolyEval_cma_c1 <= '{default: '0}; - end - else - begin - if (prodXY_uid143_pT2_uid131_invPolyEval_cma_ena2 == 1'b1) - begin - prodXY_uid143_pT2_uid131_invPolyEval_cma_a1 <= prodXY_uid143_pT2_uid131_invPolyEval_cma_a0; - prodXY_uid143_pT2_uid131_invPolyEval_cma_c1 <= prodXY_uid143_pT2_uid131_invPolyEval_cma_c0; - end - end - end - always @ (posedge clk or posedge areset) - begin - if (areset) - begin - prodXY_uid143_pT2_uid131_invPolyEval_cma_s <= '{default: '0}; - end - else - begin - if (prodXY_uid143_pT2_uid131_invPolyEval_cma_ena1 == 1'b1) - begin - prodXY_uid143_pT2_uid131_invPolyEval_cma_s[0] <= prodXY_uid143_pT2_uid131_invPolyEval_cma_y[0]; - end - end - end - dspba_delay_ver #( .width(37), .depth(0), .reset_kind("ASYNC") ) - prodXY_uid143_pT2_uid131_invPolyEval_cma_delay ( .xin(prodXY_uid143_pT2_uid131_invPolyEval_cma_s[0][36:0]), .xout(prodXY_uid143_pT2_uid131_invPolyEval_cma_qq), .ena(en[0]), .clk(clk), .aclr(areset) ); - assign prodXY_uid143_pT2_uid131_invPolyEval_cma_q = prodXY_uid143_pT2_uid131_invPolyEval_cma_qq[36:0]; - - // osig_uid144_pT2_uid131_invPolyEval(BITSELECT,143)@9 - assign osig_uid144_pT2_uid131_invPolyEval_b = prodXY_uid143_pT2_uid131_invPolyEval_cma_q[36:13]; - - // highBBits_uid133_invPolyEval(BITSELECT,132)@9 - assign highBBits_uid133_invPolyEval_b = osig_uid144_pT2_uid131_invPolyEval_b[23:2]; - - // redist9_yAddr_uid51_fpDivTest_b_7(DELAY,161) - dspba_delay_ver #( .width(9), .depth(4), .reset_kind("ASYNC") ) - redist9_yAddr_uid51_fpDivTest_b_7 ( .xin(redist8_yAddr_uid51_fpDivTest_b_3_q), .xout(redist9_yAddr_uid51_fpDivTest_b_7_q), .ena(en[0]), .clk(clk), .aclr(areset) ); - - // memoryC0_uid112_invTables_lutmem(DUALMEM,145)@7 + 2 - // in j@20000000 - assign memoryC0_uid112_invTables_lutmem_aa = redist9_yAddr_uid51_fpDivTest_b_7_q; - assign memoryC0_uid112_invTables_lutmem_reset0 = areset; - altera_syncram #( - .ram_block_type("M20K"), - .operation_mode("ROM"), - .width_a(31), - .widthad_a(9), - .numwords_a(512), - .lpm_type("altera_syncram"), - .width_byteena_a(1), - .outdata_reg_a("CLOCK0"), - .outdata_aclr_a("CLEAR0"), - .clock_enable_input_a("NORMAL"), - .power_up_uninitialized("FALSE"), - .init_file("acl_fdiv_memoryC0_uid112_invTables_lutmem.hex"), - .init_file_layout("PORT_A"), - .intended_device_family("Arria 10") - ) memoryC0_uid112_invTables_lutmem_dmem ( - .clocken0(en[0]), - .aclr0(memoryC0_uid112_invTables_lutmem_reset0), - .clock0(clk), - .address_a(memoryC0_uid112_invTables_lutmem_aa), - .q_a(memoryC0_uid112_invTables_lutmem_ir), - .wren_a(), - .wren_b(), - .rden_a(), - .rden_b(), - .data_a(), - .data_b(), - .address_b(), - .clock1(), - .clocken1(), - .clocken2(), - .clocken3(), - .aclr1(), - .addressstall_a(), - .addressstall_b(), - .byteena_a(), - .byteena_b(), - .eccencbypass(), - .eccencparity(), - .sclr(), - .address2_a(), - .address2_b(), - .q_b(), - .eccstatus() - ); - assign memoryC0_uid112_invTables_lutmem_r = memoryC0_uid112_invTables_lutmem_ir[30:0]; - - // s2sumAHighB_uid134_invPolyEval(ADD,133)@9 - assign s2sumAHighB_uid134_invPolyEval_a = {{1{memoryC0_uid112_invTables_lutmem_r[30]}}, memoryC0_uid112_invTables_lutmem_r}; - assign s2sumAHighB_uid134_invPolyEval_b = {{10{highBBits_uid133_invPolyEval_b[21]}}, highBBits_uid133_invPolyEval_b}; - assign s2sumAHighB_uid134_invPolyEval_o = $signed(s2sumAHighB_uid134_invPolyEval_a) + $signed(s2sumAHighB_uid134_invPolyEval_b); - assign s2sumAHighB_uid134_invPolyEval_q = s2sumAHighB_uid134_invPolyEval_o[31:0]; - - // lowRangeB_uid132_invPolyEval(BITSELECT,131)@9 - assign lowRangeB_uid132_invPolyEval_in = osig_uid144_pT2_uid131_invPolyEval_b[1:0]; - assign lowRangeB_uid132_invPolyEval_b = lowRangeB_uid132_invPolyEval_in[1:0]; - - // s2_uid135_invPolyEval(BITJOIN,134)@9 - assign s2_uid135_invPolyEval_q = {s2sumAHighB_uid134_invPolyEval_q, lowRangeB_uid132_invPolyEval_b}; - - // invY_uid54_fpDivTest_merged_bit_select(BITSELECT,151)@9 - assign invY_uid54_fpDivTest_merged_bit_select_in = s2_uid135_invPolyEval_q[31:0]; - assign invY_uid54_fpDivTest_merged_bit_select_b = invY_uid54_fpDivTest_merged_bit_select_in[30:5]; - assign invY_uid54_fpDivTest_merged_bit_select_c = invY_uid54_fpDivTest_merged_bit_select_in[31:31]; - - // redist0_invY_uid54_fpDivTest_merged_bit_select_b_1(DELAY,152) - dspba_delay_ver #( .width(26), .depth(1), .reset_kind("ASYNC") ) - redist0_invY_uid54_fpDivTest_merged_bit_select_b_1 ( .xin(invY_uid54_fpDivTest_merged_bit_select_b), .xout(redist0_invY_uid54_fpDivTest_merged_bit_select_b_1_q), .ena(en[0]), .clk(clk), .aclr(areset) ); - - // GND(CONSTANT,0) - assign GND_q = 1'b0; - - // prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma(CHAINMULTADD,148)@10 + 3 - assign prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_reset = areset; - assign prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_ena0 = en[0]; - assign prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_ena1 = prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_ena0; - assign prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_ena2 = prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_ena0; - assign prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_p[0] = prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_a1[0] * prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_c1[0]; - assign prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_u[0] = prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_p[0][49:0]; - assign prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_w[0] = prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_u[0]; - assign prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_x[0] = prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_w[0]; - assign prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_y[0] = prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_x[0]; - always @ (posedge clk or posedge areset) - begin - if (areset) - begin - prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_a0 <= '{default: '0}; - prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_c0 <= '{default: '0}; - end - else - begin - if (prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_ena0 == 1'b1) - begin - prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_a0[0] <= redist0_invY_uid54_fpDivTest_merged_bit_select_b_1_q; - prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_c0[0] <= lOAdded_uid58_fpDivTest_q; - end - end - end - always @ (posedge clk or posedge areset) - begin - if (areset) - begin - prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_a1 <= '{default: '0}; - prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_c1 <= '{default: '0}; - end - else - begin - if (prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_ena2 == 1'b1) - begin - prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_a1 <= prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_a0; - prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_c1 <= prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_c0; - end - end - end - always @ (posedge clk or posedge areset) - begin - if (areset) - begin - prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_s <= '{default: '0}; - end - else - begin - if (prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_ena1 == 1'b1) - begin - prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_s[0] <= prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_y[0]; - end - end - end - dspba_delay_ver #( .width(50), .depth(0), .reset_kind("ASYNC") ) - prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_delay ( .xin(prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_s[0][49:0]), .xout(prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_qq), .ena(en[0]), .clk(clk), .aclr(areset) ); - assign prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_q = prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_qq[49:0]; - - // osig_uid138_prodDivPreNormProd_uid60_fpDivTest(BITSELECT,137)@13 - assign osig_uid138_prodDivPreNormProd_uid60_fpDivTest_b = prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_q[49:24]; - - // updatedY_uid16_fpDivTest(BITJOIN,15)@0 - assign updatedY_uid16_fpDivTest_q = {GND_q, paddingY_uid15_fpDivTest_q}; - - // fracYZero_uid15_fpDivTest(LOGICAL,16)@0 + 1 - assign fracYZero_uid15_fpDivTest_a = {1'b0, fracY_uid13_fpDivTest_b}; - assign fracYZero_uid15_fpDivTest_qi = fracYZero_uid15_fpDivTest_a == updatedY_uid16_fpDivTest_q ? 1'b1 : 1'b0; - dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") ) - fracYZero_uid15_fpDivTest_delay ( .xin(fracYZero_uid15_fpDivTest_qi), .xout(fracYZero_uid15_fpDivTest_q), .ena(en[0]), .clk(clk), .aclr(areset) ); - - // redist18_fracYZero_uid15_fpDivTest_q_9(DELAY,170) - dspba_delay_ver #( .width(1), .depth(8), .reset_kind("ASYNC") ) - redist18_fracYZero_uid15_fpDivTest_q_9 ( .xin(fracYZero_uid15_fpDivTest_q), .xout(redist18_fracYZero_uid15_fpDivTest_q_9_q), .ena(en[0]), .clk(clk), .aclr(areset) ); - - // fracYPostZ_uid56_fpDivTest(LOGICAL,55)@9 + 1 - assign fracYPostZ_uid56_fpDivTest_qi = redist18_fracYZero_uid15_fpDivTest_q_9_q | invY_uid54_fpDivTest_merged_bit_select_c; - dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") ) - fracYPostZ_uid56_fpDivTest_delay ( .xin(fracYPostZ_uid56_fpDivTest_qi), .xout(fracYPostZ_uid56_fpDivTest_q), .ena(en[0]), .clk(clk), .aclr(areset) ); - - // redist5_fracYPostZ_uid56_fpDivTest_q_4(DELAY,157) - dspba_delay_ver #( .width(1), .depth(3), .reset_kind("ASYNC") ) - redist5_fracYPostZ_uid56_fpDivTest_q_4 ( .xin(fracYPostZ_uid56_fpDivTest_q), .xout(redist5_fracYPostZ_uid56_fpDivTest_q_4_q), .ena(en[0]), .clk(clk), .aclr(areset) ); - - // divValPreNormTrunc_uid66_fpDivTest(MUX,65)@13 - assign divValPreNormTrunc_uid66_fpDivTest_s = redist5_fracYPostZ_uid56_fpDivTest_q_4_q; - always @(divValPreNormTrunc_uid66_fpDivTest_s or en or osig_uid138_prodDivPreNormProd_uid60_fpDivTest_b or oFracXSE_mergedSignalTM_uid63_fpDivTest_q) - begin - unique case (divValPreNormTrunc_uid66_fpDivTest_s) - 1'b0 : divValPreNormTrunc_uid66_fpDivTest_q = osig_uid138_prodDivPreNormProd_uid60_fpDivTest_b; - 1'b1 : divValPreNormTrunc_uid66_fpDivTest_q = oFracXSE_mergedSignalTM_uid63_fpDivTest_q; - default : divValPreNormTrunc_uid66_fpDivTest_q = 26'b0; - endcase - end - - // norm_uid67_fpDivTest(BITSELECT,66)@13 - assign norm_uid67_fpDivTest_b = divValPreNormTrunc_uid66_fpDivTest_q[25:25]; - - // rndOp_uid75_fpDivTest(BITJOIN,74)@13 - assign rndOp_uid75_fpDivTest_q = {norm_uid67_fpDivTest_b, paddingY_uid15_fpDivTest_q, VCC_q}; - - // cstBiasM1_uid6_fpDivTest(CONSTANT,5) - assign cstBiasM1_uid6_fpDivTest_q = 8'b01111110; - - // redist10_expXmY_uid47_fpDivTest_q_13_notEnable(LOGICAL,191) - assign redist10_expXmY_uid47_fpDivTest_q_13_notEnable_q = ~ (en); - - // redist10_expXmY_uid47_fpDivTest_q_13_nor(LOGICAL,192) - assign redist10_expXmY_uid47_fpDivTest_q_13_nor_q = ~ (redist10_expXmY_uid47_fpDivTest_q_13_notEnable_q | redist10_expXmY_uid47_fpDivTest_q_13_sticky_ena_q); - - // redist10_expXmY_uid47_fpDivTest_q_13_mem_last(CONSTANT,188) - assign redist10_expXmY_uid47_fpDivTest_q_13_mem_last_q = 5'b01000; - - // redist10_expXmY_uid47_fpDivTest_q_13_cmp(LOGICAL,189) - assign redist10_expXmY_uid47_fpDivTest_q_13_cmp_b = {1'b0, redist10_expXmY_uid47_fpDivTest_q_13_rdmux_q}; - assign redist10_expXmY_uid47_fpDivTest_q_13_cmp_q = redist10_expXmY_uid47_fpDivTest_q_13_mem_last_q == redist10_expXmY_uid47_fpDivTest_q_13_cmp_b ? 1'b1 : 1'b0; - - // redist10_expXmY_uid47_fpDivTest_q_13_cmpReg(REG,190) - always @ (posedge clk or posedge areset) - begin - if (areset) - begin - redist10_expXmY_uid47_fpDivTest_q_13_cmpReg_q <= 1'b0; - end - else if (en == 1'b1) - begin - redist10_expXmY_uid47_fpDivTest_q_13_cmpReg_q <= redist10_expXmY_uid47_fpDivTest_q_13_cmp_q; - end - end - - // redist10_expXmY_uid47_fpDivTest_q_13_sticky_ena(REG,193) - always @ (posedge clk or posedge areset) - begin - if (areset) - begin - redist10_expXmY_uid47_fpDivTest_q_13_sticky_ena_q <= 1'b0; - end - else if (redist10_expXmY_uid47_fpDivTest_q_13_nor_q == 1'b1) - begin - redist10_expXmY_uid47_fpDivTest_q_13_sticky_ena_q <= redist10_expXmY_uid47_fpDivTest_q_13_cmpReg_q; - end - end - - // redist10_expXmY_uid47_fpDivTest_q_13_enaAnd(LOGICAL,194) - assign redist10_expXmY_uid47_fpDivTest_q_13_enaAnd_q = redist10_expXmY_uid47_fpDivTest_q_13_sticky_ena_q & en; - - // redist10_expXmY_uid47_fpDivTest_q_13_rdcnt(COUNTER,185) - // low=0, high=9, step=1, init=0 - always @ (posedge clk or posedge areset) - begin - if (areset) - begin - redist10_expXmY_uid47_fpDivTest_q_13_rdcnt_i <= 4'd0; - redist10_expXmY_uid47_fpDivTest_q_13_rdcnt_eq <= 1'b0; - end - else if (en == 1'b1) - begin - if (redist10_expXmY_uid47_fpDivTest_q_13_rdcnt_i == 4'd8) - begin - redist10_expXmY_uid47_fpDivTest_q_13_rdcnt_eq <= 1'b1; - end - else - begin - redist10_expXmY_uid47_fpDivTest_q_13_rdcnt_eq <= 1'b0; - end - if (redist10_expXmY_uid47_fpDivTest_q_13_rdcnt_eq == 1'b1) - begin - redist10_expXmY_uid47_fpDivTest_q_13_rdcnt_i <= $unsigned(redist10_expXmY_uid47_fpDivTest_q_13_rdcnt_i) + $unsigned(4'd7); - end - else - begin - redist10_expXmY_uid47_fpDivTest_q_13_rdcnt_i <= $unsigned(redist10_expXmY_uid47_fpDivTest_q_13_rdcnt_i) + $unsigned(4'd1); - end - end - end - assign redist10_expXmY_uid47_fpDivTest_q_13_rdcnt_q = redist10_expXmY_uid47_fpDivTest_q_13_rdcnt_i[3:0]; - - // redist10_expXmY_uid47_fpDivTest_q_13_rdmux(MUX,186) - assign redist10_expXmY_uid47_fpDivTest_q_13_rdmux_s = en; - always @(redist10_expXmY_uid47_fpDivTest_q_13_rdmux_s or redist10_expXmY_uid47_fpDivTest_q_13_wraddr_q or redist10_expXmY_uid47_fpDivTest_q_13_rdcnt_q) - begin - unique case (redist10_expXmY_uid47_fpDivTest_q_13_rdmux_s) - 1'b0 : redist10_expXmY_uid47_fpDivTest_q_13_rdmux_q = redist10_expXmY_uid47_fpDivTest_q_13_wraddr_q; - 1'b1 : redist10_expXmY_uid47_fpDivTest_q_13_rdmux_q = redist10_expXmY_uid47_fpDivTest_q_13_rdcnt_q; - default : redist10_expXmY_uid47_fpDivTest_q_13_rdmux_q = 4'b0; - endcase - end - - // expXmY_uid47_fpDivTest(SUB,46)@0 + 1 - assign expXmY_uid47_fpDivTest_a = {1'b0, expX_uid9_fpDivTest_b}; - assign expXmY_uid47_fpDivTest_b = {1'b0, expY_uid12_fpDivTest_b}; - always @ (posedge clk or posedge areset) - begin - if (areset) - begin - expXmY_uid47_fpDivTest_o <= 9'b0; - end - else if (en == 1'b1) - begin - expXmY_uid47_fpDivTest_o <= $unsigned(expXmY_uid47_fpDivTest_a) - $unsigned(expXmY_uid47_fpDivTest_b); - end - end - assign expXmY_uid47_fpDivTest_q = expXmY_uid47_fpDivTest_o[8:0]; - - // redist10_expXmY_uid47_fpDivTest_q_13_wraddr(REG,187) - always @ (posedge clk or posedge areset) - begin - if (areset) - begin - redist10_expXmY_uid47_fpDivTest_q_13_wraddr_q <= 4'b1001; - end - else - begin - redist10_expXmY_uid47_fpDivTest_q_13_wraddr_q <= redist10_expXmY_uid47_fpDivTest_q_13_rdmux_q; - end - end - - // redist10_expXmY_uid47_fpDivTest_q_13_mem(DUALMEM,184) - assign redist10_expXmY_uid47_fpDivTest_q_13_mem_ia = expXmY_uid47_fpDivTest_q; - assign redist10_expXmY_uid47_fpDivTest_q_13_mem_aa = redist10_expXmY_uid47_fpDivTest_q_13_wraddr_q; - assign redist10_expXmY_uid47_fpDivTest_q_13_mem_ab = redist10_expXmY_uid47_fpDivTest_q_13_rdmux_q; - assign redist10_expXmY_uid47_fpDivTest_q_13_mem_reset0 = areset; - altera_syncram #( - .ram_block_type("MLAB"), - .operation_mode("DUAL_PORT"), - .width_a(9), - .widthad_a(4), - .numwords_a(10), - .width_b(9), - .widthad_b(4), - .numwords_b(10), - .lpm_type("altera_syncram"), - .width_byteena_a(1), - .address_reg_b("CLOCK0"), - .indata_reg_b("CLOCK0"), - .rdcontrol_reg_b("CLOCK0"), - .byteena_reg_b("CLOCK0"), - .outdata_reg_b("CLOCK1"), - .outdata_aclr_b("CLEAR1"), - .clock_enable_input_a("NORMAL"), - .clock_enable_input_b("NORMAL"), - .clock_enable_output_b("NORMAL"), - .read_during_write_mode_mixed_ports("DONT_CARE"), - .power_up_uninitialized("TRUE"), - .intended_device_family("Arria 10") - ) redist10_expXmY_uid47_fpDivTest_q_13_mem_dmem ( - .clocken1(redist10_expXmY_uid47_fpDivTest_q_13_enaAnd_q[0]), - .clocken0(VCC_q[0]), - .clock0(clk), - .aclr1(redist10_expXmY_uid47_fpDivTest_q_13_mem_reset0), - .clock1(clk), - .address_a(redist10_expXmY_uid47_fpDivTest_q_13_mem_aa), - .data_a(redist10_expXmY_uid47_fpDivTest_q_13_mem_ia), - .wren_a(en[0]), - .address_b(redist10_expXmY_uid47_fpDivTest_q_13_mem_ab), - .q_b(redist10_expXmY_uid47_fpDivTest_q_13_mem_iq), - .wren_b(), - .rden_a(), - .rden_b(), - .data_b(), - .clocken2(), - .clocken3(), - .aclr0(), - .addressstall_a(), - .addressstall_b(), - .byteena_a(), - .byteena_b(), - .eccencbypass(), - .eccencparity(), - .sclr(), - .address2_a(), - .address2_b(), - .q_a(), - .eccstatus() - ); - assign redist10_expXmY_uid47_fpDivTest_q_13_mem_q = redist10_expXmY_uid47_fpDivTest_q_13_mem_iq[8:0]; - - // redist10_expXmY_uid47_fpDivTest_q_13_outputreg(DELAY,183) - dspba_delay_ver #( .width(9), .depth(1), .reset_kind("ASYNC") ) - redist10_expXmY_uid47_fpDivTest_q_13_outputreg ( .xin(redist10_expXmY_uid47_fpDivTest_q_13_mem_q), .xout(redist10_expXmY_uid47_fpDivTest_q_13_outputreg_q), .ena(en[0]), .clk(clk), .aclr(areset) ); - - // expR_uid48_fpDivTest(ADD,47)@13 - assign expR_uid48_fpDivTest_a = {{2{redist10_expXmY_uid47_fpDivTest_q_13_outputreg_q[8]}}, redist10_expXmY_uid47_fpDivTest_q_13_outputreg_q}; - assign expR_uid48_fpDivTest_b = {3'b000, cstBiasM1_uid6_fpDivTest_q}; - assign expR_uid48_fpDivTest_o = $signed(expR_uid48_fpDivTest_a) + $signed(expR_uid48_fpDivTest_b); - assign expR_uid48_fpDivTest_q = expR_uid48_fpDivTest_o[9:0]; - - // divValPreNormHigh_uid68_fpDivTest(BITSELECT,67)@13 - assign divValPreNormHigh_uid68_fpDivTest_in = divValPreNormTrunc_uid66_fpDivTest_q[24:0]; - assign divValPreNormHigh_uid68_fpDivTest_b = divValPreNormHigh_uid68_fpDivTest_in[24:1]; - - // divValPreNormLow_uid69_fpDivTest(BITSELECT,68)@13 - assign divValPreNormLow_uid69_fpDivTest_in = divValPreNormTrunc_uid66_fpDivTest_q[23:0]; - assign divValPreNormLow_uid69_fpDivTest_b = divValPreNormLow_uid69_fpDivTest_in[23:0]; - - // normFracRnd_uid70_fpDivTest(MUX,69)@13 - assign normFracRnd_uid70_fpDivTest_s = norm_uid67_fpDivTest_b; - always @(normFracRnd_uid70_fpDivTest_s or en or divValPreNormLow_uid69_fpDivTest_b or divValPreNormHigh_uid68_fpDivTest_b) - begin - unique case (normFracRnd_uid70_fpDivTest_s) - 1'b0 : normFracRnd_uid70_fpDivTest_q = divValPreNormLow_uid69_fpDivTest_b; - 1'b1 : normFracRnd_uid70_fpDivTest_q = divValPreNormHigh_uid68_fpDivTest_b; - default : normFracRnd_uid70_fpDivTest_q = 24'b0; - endcase - end - - // expFracRnd_uid71_fpDivTest(BITJOIN,70)@13 - assign expFracRnd_uid71_fpDivTest_q = {expR_uid48_fpDivTest_q, normFracRnd_uid70_fpDivTest_q}; - - // expFracPostRnd_uid76_fpDivTest(ADD,75)@13 + 1 - assign expFracPostRnd_uid76_fpDivTest_a = {{2{expFracRnd_uid71_fpDivTest_q[33]}}, expFracRnd_uid71_fpDivTest_q}; - assign expFracPostRnd_uid76_fpDivTest_b = {11'b00000000000, rndOp_uid75_fpDivTest_q}; - always @ (posedge clk or posedge areset) - begin - if (areset) - begin - expFracPostRnd_uid76_fpDivTest_o <= 36'b0; - end - else if (en == 1'b1) - begin - expFracPostRnd_uid76_fpDivTest_o <= $signed(expFracPostRnd_uid76_fpDivTest_a) + $signed(expFracPostRnd_uid76_fpDivTest_b); - end - end - assign expFracPostRnd_uid76_fpDivTest_q = expFracPostRnd_uid76_fpDivTest_o[34:0]; - - // excRPreExc_uid79_fpDivTest(BITSELECT,78)@14 - assign excRPreExc_uid79_fpDivTest_in = expFracPostRnd_uid76_fpDivTest_q[31:0]; - assign excRPreExc_uid79_fpDivTest_b = excRPreExc_uid79_fpDivTest_in[31:24]; - - // redist2_excRPreExc_uid79_fpDivTest_b_1(DELAY,154) - dspba_delay_ver #( .width(8), .depth(1), .reset_kind("ASYNC") ) - redist2_excRPreExc_uid79_fpDivTest_b_1 ( .xin(excRPreExc_uid79_fpDivTest_b), .xout(redist2_excRPreExc_uid79_fpDivTest_b_1_q), .ena(en[0]), .clk(clk), .aclr(areset) ); - - // invExpXIsMax_uid43_fpDivTest(LOGICAL,42)@14 - assign invExpXIsMax_uid43_fpDivTest_q = ~ (redist13_expXIsMax_uid38_fpDivTest_q_14_q); - - // InvExpXIsZero_uid44_fpDivTest(LOGICAL,43)@14 - assign InvExpXIsZero_uid44_fpDivTest_q = ~ (redist14_excZ_y_uid37_fpDivTest_q_14_q); - - // excR_y_uid45_fpDivTest(LOGICAL,44)@14 - assign excR_y_uid45_fpDivTest_q = InvExpXIsZero_uid44_fpDivTest_q & invExpXIsMax_uid43_fpDivTest_q; - - // excXIYR_uid93_fpDivTest(LOGICAL,92)@14 - assign excXIYR_uid93_fpDivTest_q = excI_x_uid27_fpDivTest_q & excR_y_uid45_fpDivTest_q; - - // excXIYZ_uid92_fpDivTest(LOGICAL,91)@14 - assign excXIYZ_uid92_fpDivTest_q = excI_x_uid27_fpDivTest_q & redist14_excZ_y_uid37_fpDivTest_q_14_q; - - // expRExt_uid80_fpDivTest(BITSELECT,79)@14 - assign expRExt_uid80_fpDivTest_b = expFracPostRnd_uid76_fpDivTest_q[34:24]; - - // expOvf_uid84_fpDivTest(COMPARE,83)@14 - assign expOvf_uid84_fpDivTest_a = {{2{expRExt_uid80_fpDivTest_b[10]}}, expRExt_uid80_fpDivTest_b}; - assign expOvf_uid84_fpDivTest_b = {5'b00000, cstAllOWE_uid18_fpDivTest_q}; - assign expOvf_uid84_fpDivTest_o = $signed(expOvf_uid84_fpDivTest_a) - $signed(expOvf_uid84_fpDivTest_b); - assign expOvf_uid84_fpDivTest_n[0] = ~ (expOvf_uid84_fpDivTest_o[12]); - - // invExpXIsMax_uid29_fpDivTest(LOGICAL,28)@14 - assign invExpXIsMax_uid29_fpDivTest_q = ~ (redist16_expXIsMax_uid24_fpDivTest_q_14_q); - - // InvExpXIsZero_uid30_fpDivTest(LOGICAL,29)@14 - assign InvExpXIsZero_uid30_fpDivTest_q = ~ (redist17_excZ_x_uid23_fpDivTest_q_14_q); - - // excR_x_uid31_fpDivTest(LOGICAL,30)@14 - assign excR_x_uid31_fpDivTest_q = InvExpXIsZero_uid30_fpDivTest_q & invExpXIsMax_uid29_fpDivTest_q; - - // excXRYROvf_uid91_fpDivTest(LOGICAL,90)@14 - assign excXRYROvf_uid91_fpDivTest_q = excR_x_uid31_fpDivTest_q & excR_y_uid45_fpDivTest_q & expOvf_uid84_fpDivTest_n; - - // excXRYZ_uid90_fpDivTest(LOGICAL,89)@14 - assign excXRYZ_uid90_fpDivTest_q = excR_x_uid31_fpDivTest_q & redist14_excZ_y_uid37_fpDivTest_q_14_q; - - // excRInf_uid94_fpDivTest(LOGICAL,93)@14 - assign excRInf_uid94_fpDivTest_q = excXRYZ_uid90_fpDivTest_q | excXRYROvf_uid91_fpDivTest_q | excXIYZ_uid92_fpDivTest_q | excXIYR_uid93_fpDivTest_q; - - // xRegOrZero_uid87_fpDivTest(LOGICAL,86)@14 - assign xRegOrZero_uid87_fpDivTest_q = excR_x_uid31_fpDivTest_q | redist17_excZ_x_uid23_fpDivTest_q_14_q; - - // regOrZeroOverInf_uid88_fpDivTest(LOGICAL,87)@14 - assign regOrZeroOverInf_uid88_fpDivTest_q = xRegOrZero_uid87_fpDivTest_q & excI_y_uid41_fpDivTest_q; - - // expUdf_uid81_fpDivTest(COMPARE,80)@14 - assign expUdf_uid81_fpDivTest_a = {12'b000000000000, GND_q}; - assign expUdf_uid81_fpDivTest_b = {{2{expRExt_uid80_fpDivTest_b[10]}}, expRExt_uid80_fpDivTest_b}; - assign expUdf_uid81_fpDivTest_o = $signed(expUdf_uid81_fpDivTest_a) - $signed(expUdf_uid81_fpDivTest_b); - assign expUdf_uid81_fpDivTest_n[0] = ~ (expUdf_uid81_fpDivTest_o[12]); - - // regOverRegWithUf_uid86_fpDivTest(LOGICAL,85)@14 - assign regOverRegWithUf_uid86_fpDivTest_q = expUdf_uid81_fpDivTest_n & excR_x_uid31_fpDivTest_q & excR_y_uid45_fpDivTest_q; - - // zeroOverReg_uid85_fpDivTest(LOGICAL,84)@14 - assign zeroOverReg_uid85_fpDivTest_q = redist17_excZ_x_uid23_fpDivTest_q_14_q & excR_y_uid45_fpDivTest_q; - - // excRZero_uid89_fpDivTest(LOGICAL,88)@14 - assign excRZero_uid89_fpDivTest_q = zeroOverReg_uid85_fpDivTest_q | regOverRegWithUf_uid86_fpDivTest_q | regOrZeroOverInf_uid88_fpDivTest_q; - - // concExc_uid98_fpDivTest(BITJOIN,97)@14 - assign concExc_uid98_fpDivTest_q = {excRNaN_uid97_fpDivTest_q, excRInf_uid94_fpDivTest_q, excRZero_uid89_fpDivTest_q}; - - // excREnc_uid99_fpDivTest(LOOKUP,98)@14 + 1 - always @ (posedge clk or posedge areset) - begin - if (areset) - begin - excREnc_uid99_fpDivTest_q <= 2'b01; - end - else if (en == 1'b1) - begin - unique case (concExc_uid98_fpDivTest_q) - 3'b000 : excREnc_uid99_fpDivTest_q <= 2'b01; - 3'b001 : excREnc_uid99_fpDivTest_q <= 2'b00; - 3'b010 : excREnc_uid99_fpDivTest_q <= 2'b10; - 3'b011 : excREnc_uid99_fpDivTest_q <= 2'b00; - 3'b100 : excREnc_uid99_fpDivTest_q <= 2'b11; - 3'b101 : excREnc_uid99_fpDivTest_q <= 2'b00; - 3'b110 : excREnc_uid99_fpDivTest_q <= 2'b00; - 3'b111 : excREnc_uid99_fpDivTest_q <= 2'b00; - default : begin - // unreachable - excREnc_uid99_fpDivTest_q <= 2'bxx; - end - endcase - end - end - - // expRPostExc_uid107_fpDivTest(MUX,106)@15 - assign expRPostExc_uid107_fpDivTest_s = excREnc_uid99_fpDivTest_q; - always @(expRPostExc_uid107_fpDivTest_s or en or cstAllZWE_uid20_fpDivTest_q or redist2_excRPreExc_uid79_fpDivTest_b_1_q or cstAllOWE_uid18_fpDivTest_q) - begin - unique case (expRPostExc_uid107_fpDivTest_s) - 2'b00 : expRPostExc_uid107_fpDivTest_q = cstAllZWE_uid20_fpDivTest_q; - 2'b01 : expRPostExc_uid107_fpDivTest_q = redist2_excRPreExc_uid79_fpDivTest_b_1_q; - 2'b10 : expRPostExc_uid107_fpDivTest_q = cstAllOWE_uid18_fpDivTest_q; - 2'b11 : expRPostExc_uid107_fpDivTest_q = cstAllOWE_uid18_fpDivTest_q; - default : expRPostExc_uid107_fpDivTest_q = 8'b0; - endcase - end - - // oneFracRPostExc2_uid100_fpDivTest(CONSTANT,99) - assign oneFracRPostExc2_uid100_fpDivTest_q = 23'b00000000000000000000001; - - // fracRPreExc_uid78_fpDivTest(BITSELECT,77)@14 - assign fracRPreExc_uid78_fpDivTest_in = expFracPostRnd_uid76_fpDivTest_q[23:0]; - assign fracRPreExc_uid78_fpDivTest_b = fracRPreExc_uid78_fpDivTest_in[23:1]; - - // redist3_fracRPreExc_uid78_fpDivTest_b_1(DELAY,155) - dspba_delay_ver #( .width(23), .depth(1), .reset_kind("ASYNC") ) - redist3_fracRPreExc_uid78_fpDivTest_b_1 ( .xin(fracRPreExc_uid78_fpDivTest_b), .xout(redist3_fracRPreExc_uid78_fpDivTest_b_1_q), .ena(en[0]), .clk(clk), .aclr(areset) ); - - // fracRPostExc_uid103_fpDivTest(MUX,102)@15 - assign fracRPostExc_uid103_fpDivTest_s = excREnc_uid99_fpDivTest_q; - always @(fracRPostExc_uid103_fpDivTest_s or en or paddingY_uid15_fpDivTest_q or redist3_fracRPreExc_uid78_fpDivTest_b_1_q or oneFracRPostExc2_uid100_fpDivTest_q) - begin - unique case (fracRPostExc_uid103_fpDivTest_s) - 2'b00 : fracRPostExc_uid103_fpDivTest_q = paddingY_uid15_fpDivTest_q; - 2'b01 : fracRPostExc_uid103_fpDivTest_q = redist3_fracRPreExc_uid78_fpDivTest_b_1_q; - 2'b10 : fracRPostExc_uid103_fpDivTest_q = paddingY_uid15_fpDivTest_q; - 2'b11 : fracRPostExc_uid103_fpDivTest_q = oneFracRPostExc2_uid100_fpDivTest_q; - default : fracRPostExc_uid103_fpDivTest_q = 23'b0; - endcase - end - - // divR_uid110_fpDivTest(BITJOIN,109)@15 - assign divR_uid110_fpDivTest_q = {sRPostExc_uid109_fpDivTest_q, expRPostExc_uid107_fpDivTest_q, fracRPostExc_uid103_fpDivTest_q}; - - // xOut(GPOUT,4)@15 - assign q = divR_uid110_fpDivTest_q; - -endmodule diff --git a/hw/rtl/fp_cores/altera/acl_fdiv_memoryC0_uid112_invTables_lutmem.hex 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-:0201E500011403 -:0201E600011303 -:0201E700011302 -:0201E800011400 -:0201E9000114FF -:0201EA00011002 -:0201EB00011100 -:0201EC00010F01 -:0201ED00010E01 -:0201EE00010D01 -:0201EF00010C01 -:0201F000010B01 -:0201F100010902 -:0201F200010BFF -:0201F300010801 -:0201F400010800 -:0201F500010601 -:0201F600010600 -:0201F7000107FE -:0201F8000105FF -:0201F900010300 -:0201FA00010200 -:0201FB000102FF -:0201FC000103FD -:0201FD000102FD -:0201FE000100FE -:0201FF000100FD -:00000001ff diff --git a/hw/rtl/fp_cores/altera/acl_fsqrt.sv b/hw/rtl/fp_cores/altera/acl_fsqrt.sv deleted file mode 100644 index 84241c6d..00000000 --- a/hw/rtl/fp_cores/altera/acl_fsqrt.sv +++ /dev/null @@ -1,1128 +0,0 @@ -// ------------------------------------------------------------------------- -// High Level Design Compiler for Intel(R) FPGAs Version 17.1 (Release Build #273) -// Quartus Prime development tool and MATLAB/Simulink Interface -// -// Legal Notice: Copyright 2017 Intel Corporation. All rights reserved. -// Your use of Intel Corporation's design tools, logic functions and other -// software and tools, and its AMPP partner logic functions, and any output -// files any of the foregoing (including device programming or simulation -// files), and any associated documentation or information are expressly -// subject to the terms and conditions of the Intel FPGA Software License -// Agreement, Intel MegaCore Function License Agreement, or other applicable -// license agreement, including, without limitation, that your use is for -// the sole purpose of programming logic devices manufactured by Intel -// and sold by Intel or its authorized distributors. Please refer to the -// applicable agreement for further details. -// --------------------------------------------------------------------------- - -// SystemVerilog created from acl_fsqrt -// SystemVerilog created on Wed Dec 9 01:17:51 2020 - - -(* altera_attribute = "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410; -name MESSAGE_DISABLE 113007; -name MESSAGE_DISABLE 10958" *) -module acl_fsqrt ( - input wire [31:0] a, - input wire [0:0] en, - output wire [31:0] q, - input wire clk, - input wire areset - ); - - wire [0:0] GND_q; - wire [0:0] VCC_q; - wire [7:0] expX_uid6_fpSqrtTest_b; - wire [0:0] signX_uid7_fpSqrtTest_b; - wire [7:0] cstAllOWE_uid8_fpSqrtTest_q; - wire [22:0] cstZeroWF_uid9_fpSqrtTest_q; - wire [7:0] cstAllZWE_uid10_fpSqrtTest_q; - wire [22:0] frac_x_uid12_fpSqrtTest_b; - wire [0:0] excZ_x_uid13_fpSqrtTest_qi; - reg [0:0] excZ_x_uid13_fpSqrtTest_q; - wire [0:0] expXIsMax_uid14_fpSqrtTest_qi; - reg [0:0] expXIsMax_uid14_fpSqrtTest_q; - wire [0:0] fracXIsZero_uid15_fpSqrtTest_qi; - reg [0:0] fracXIsZero_uid15_fpSqrtTest_q; - wire [0:0] fracXIsNotZero_uid16_fpSqrtTest_q; - wire [0:0] excI_x_uid17_fpSqrtTest_q; - wire [0:0] excN_x_uid18_fpSqrtTest_q; - wire [0:0] invExpXIsMax_uid19_fpSqrtTest_q; - wire [0:0] InvExpXIsZero_uid20_fpSqrtTest_q; - wire [0:0] excR_x_uid21_fpSqrtTest_q; - wire [7:0] sBias_uid22_fpSqrtTest_q; - wire [8:0] expEvenSig_uid24_fpSqrtTest_a; - wire [8:0] expEvenSig_uid24_fpSqrtTest_b; - logic [8:0] expEvenSig_uid24_fpSqrtTest_o; - wire [8:0] expEvenSig_uid24_fpSqrtTest_q; - wire [7:0] expREven_uid25_fpSqrtTest_b; - wire [7:0] sBiasM1_uid26_fpSqrtTest_q; - wire [8:0] expOddSig_uid27_fpSqrtTest_a; - wire [8:0] expOddSig_uid27_fpSqrtTest_b; - logic [8:0] expOddSig_uid27_fpSqrtTest_o; - wire [8:0] expOddSig_uid27_fpSqrtTest_q; - wire [7:0] expROdd_uid28_fpSqrtTest_b; - wire [0:0] expX0PS_uid29_fpSqrtTest_in; - wire [0:0] expX0PS_uid29_fpSqrtTest_b; - wire [0:0] expOddSelect_uid30_fpSqrtTest_q; - wire [0:0] expRMux_uid31_fpSqrtTest_s; - reg [7:0] expRMux_uid31_fpSqrtTest_q; - wire [23:0] addrFull_uid33_fpSqrtTest_q; - wire [7:0] yAddr_uid35_fpSqrtTest_b; - wire [15:0] yForPe_uid36_fpSqrtTest_in; - wire [15:0] yForPe_uid36_fpSqrtTest_b; - wire [30:0] expInc_uid38_fpSqrtTest_in; - wire [0:0] expInc_uid38_fpSqrtTest_b; - wire [28:0] fracRPostProcessings_uid39_fpSqrtTest_in; - wire [22:0] fracRPostProcessings_uid39_fpSqrtTest_b; - wire [8:0] expR_uid40_fpSqrtTest_a; - wire [8:0] expR_uid40_fpSqrtTest_b; - logic [8:0] expR_uid40_fpSqrtTest_o; - wire [8:0] expR_uid40_fpSqrtTest_q; - wire [0:0] invSignX_uid41_fpSqrtTest_q; - wire [0:0] inInfAndNotNeg_uid42_fpSqrtTest_q; - wire [0:0] minReg_uid43_fpSqrtTest_q; - wire [0:0] minInf_uid44_fpSqrtTest_q; - wire [0:0] excRNaN_uid45_fpSqrtTest_q; - wire [2:0] excConc_uid46_fpSqrtTest_q; - wire [3:0] fracSelIn_uid47_fpSqrtTest_q; - reg [1:0] fracSel_uid48_fpSqrtTest_q; - wire [7:0] expRR_uid51_fpSqrtTest_in; - wire [7:0] expRR_uid51_fpSqrtTest_b; - wire [1:0] expRPostExc_uid53_fpSqrtTest_s; - reg [7:0] expRPostExc_uid53_fpSqrtTest_q; - wire [22:0] fracNaN_uid54_fpSqrtTest_q; - wire [1:0] fracRPostExc_uid58_fpSqrtTest_s; - reg [22:0] fracRPostExc_uid58_fpSqrtTest_q; - wire [0:0] negZero_uid59_fpSqrtTest_qi; - reg [0:0] negZero_uid59_fpSqrtTest_q; - wire [31:0] RSqrt_uid60_fpSqrtTest_q; - wire [11:0] yT1_uid74_invPolyEval_b; - wire [0:0] lowRangeB_uid76_invPolyEval_in; - wire [0:0] lowRangeB_uid76_invPolyEval_b; - wire [11:0] highBBits_uid77_invPolyEval_b; - wire [21:0] s1sumAHighB_uid78_invPolyEval_a; - wire [21:0] s1sumAHighB_uid78_invPolyEval_b; - logic [21:0] s1sumAHighB_uid78_invPolyEval_o; - wire [21:0] s1sumAHighB_uid78_invPolyEval_q; - wire [22:0] s1_uid79_invPolyEval_q; - wire [1:0] lowRangeB_uid82_invPolyEval_in; - wire [1:0] lowRangeB_uid82_invPolyEval_b; - wire [21:0] highBBits_uid83_invPolyEval_b; - wire [29:0] s2sumAHighB_uid84_invPolyEval_a; - wire [29:0] s2sumAHighB_uid84_invPolyEval_b; - logic [29:0] s2sumAHighB_uid84_invPolyEval_o; - wire [29:0] s2sumAHighB_uid84_invPolyEval_q; - wire [31:0] s2_uid85_invPolyEval_q; - wire [12:0] osig_uid88_pT1_uid75_invPolyEval_b; - wire [23:0] osig_uid91_pT2_uid81_invPolyEval_b; - wire memoryC0_uid62_sqrtTables_lutmem_reset0; - wire [28:0] memoryC0_uid62_sqrtTables_lutmem_ia; - wire [7:0] memoryC0_uid62_sqrtTables_lutmem_aa; - wire [7:0] memoryC0_uid62_sqrtTables_lutmem_ab; - wire [28:0] memoryC0_uid62_sqrtTables_lutmem_ir; - wire [28:0] memoryC0_uid62_sqrtTables_lutmem_r; - wire memoryC1_uid65_sqrtTables_lutmem_reset0; - wire [20:0] memoryC1_uid65_sqrtTables_lutmem_ia; - wire [7:0] memoryC1_uid65_sqrtTables_lutmem_aa; - wire [7:0] memoryC1_uid65_sqrtTables_lutmem_ab; - wire [20:0] memoryC1_uid65_sqrtTables_lutmem_ir; - wire [20:0] memoryC1_uid65_sqrtTables_lutmem_r; - wire memoryC2_uid68_sqrtTables_lutmem_reset0; - wire [11:0] memoryC2_uid68_sqrtTables_lutmem_ia; - wire [7:0] memoryC2_uid68_sqrtTables_lutmem_aa; - wire [7:0] memoryC2_uid68_sqrtTables_lutmem_ab; - wire [11:0] memoryC2_uid68_sqrtTables_lutmem_ir; - wire [11:0] memoryC2_uid68_sqrtTables_lutmem_r; - wire prodXY_uid87_pT1_uid75_invPolyEval_cma_reset; - (* preserve, altera_attribute = "-name allow_synch_ctrl_usage off" *) reg [11:0] prodXY_uid87_pT1_uid75_invPolyEval_cma_a0 [0:0]; - (* preserve, altera_attribute = "-name allow_synch_ctrl_usage off" *) reg [11:0] prodXY_uid87_pT1_uid75_invPolyEval_cma_a1 [0:0]; - (* preserve, altera_attribute = "-name allow_synch_ctrl_usage off" *) reg signed [11:0] prodXY_uid87_pT1_uid75_invPolyEval_cma_c0 [0:0]; - (* preserve, altera_attribute = "-name allow_synch_ctrl_usage off" *) reg signed [11:0] prodXY_uid87_pT1_uid75_invPolyEval_cma_c1 [0:0]; - wire signed [12:0] prodXY_uid87_pT1_uid75_invPolyEval_cma_l [0:0]; - wire signed [24:0] prodXY_uid87_pT1_uid75_invPolyEval_cma_p [0:0]; - wire signed [24:0] prodXY_uid87_pT1_uid75_invPolyEval_cma_u [0:0]; - wire signed [24:0] prodXY_uid87_pT1_uid75_invPolyEval_cma_w [0:0]; - wire signed [24:0] prodXY_uid87_pT1_uid75_invPolyEval_cma_x [0:0]; - wire signed [24:0] prodXY_uid87_pT1_uid75_invPolyEval_cma_y [0:0]; - reg signed [24:0] prodXY_uid87_pT1_uid75_invPolyEval_cma_s [0:0]; - wire [23:0] prodXY_uid87_pT1_uid75_invPolyEval_cma_qq; - wire [23:0] prodXY_uid87_pT1_uid75_invPolyEval_cma_q; - wire prodXY_uid87_pT1_uid75_invPolyEval_cma_ena0; - wire prodXY_uid87_pT1_uid75_invPolyEval_cma_ena1; - wire prodXY_uid87_pT1_uid75_invPolyEval_cma_ena2; - wire prodXY_uid90_pT2_uid81_invPolyEval_cma_reset; - (* preserve, altera_attribute = "-name allow_synch_ctrl_usage off" *) reg [15:0] prodXY_uid90_pT2_uid81_invPolyEval_cma_a0 [0:0]; - (* preserve, altera_attribute = "-name allow_synch_ctrl_usage off" *) reg [15:0] prodXY_uid90_pT2_uid81_invPolyEval_cma_a1 [0:0]; - (* preserve, altera_attribute = "-name allow_synch_ctrl_usage off" *) reg signed [22:0] prodXY_uid90_pT2_uid81_invPolyEval_cma_c0 [0:0]; - (* preserve, altera_attribute = "-name allow_synch_ctrl_usage off" *) reg signed [22:0] prodXY_uid90_pT2_uid81_invPolyEval_cma_c1 [0:0]; - wire signed [16:0] prodXY_uid90_pT2_uid81_invPolyEval_cma_l [0:0]; - wire signed [39:0] prodXY_uid90_pT2_uid81_invPolyEval_cma_p [0:0]; - wire signed [39:0] prodXY_uid90_pT2_uid81_invPolyEval_cma_u [0:0]; - wire signed [39:0] prodXY_uid90_pT2_uid81_invPolyEval_cma_w [0:0]; - wire signed [39:0] prodXY_uid90_pT2_uid81_invPolyEval_cma_x [0:0]; - wire signed [39:0] prodXY_uid90_pT2_uid81_invPolyEval_cma_y [0:0]; - reg signed [39:0] prodXY_uid90_pT2_uid81_invPolyEval_cma_s [0:0]; - wire [38:0] prodXY_uid90_pT2_uid81_invPolyEval_cma_qq; - wire [38:0] prodXY_uid90_pT2_uid81_invPolyEval_cma_q; - wire prodXY_uid90_pT2_uid81_invPolyEval_cma_ena0; - wire prodXY_uid90_pT2_uid81_invPolyEval_cma_ena1; - wire prodXY_uid90_pT2_uid81_invPolyEval_cma_ena2; - reg [0:0] redist0_lowRangeB_uid76_invPolyEval_b_1_q; - reg [0:0] redist1_negZero_uid59_fpSqrtTest_q_9_q; - reg [1:0] redist2_fracSel_uid48_fpSqrtTest_q_9_q; - reg [22:0] redist3_fracRPostProcessings_uid39_fpSqrtTest_b_1_q; - reg [0:0] redist4_expInc_uid38_fpSqrtTest_b_1_q; - reg [15:0] redist5_yForPe_uid36_fpSqrtTest_b_2_q; - reg [7:0] redist7_yAddr_uid35_fpSqrtTest_b_3_q; - reg [7:0] redist8_yAddr_uid35_fpSqrtTest_b_7_q; - reg [0:0] redist10_signX_uid7_fpSqrtTest_b_1_q; - wire redist6_yForPe_uid36_fpSqrtTest_b_6_mem_reset0; - wire [15:0] redist6_yForPe_uid36_fpSqrtTest_b_6_mem_ia; - wire [1:0] redist6_yForPe_uid36_fpSqrtTest_b_6_mem_aa; - wire [1:0] redist6_yForPe_uid36_fpSqrtTest_b_6_mem_ab; - wire [15:0] redist6_yForPe_uid36_fpSqrtTest_b_6_mem_iq; - wire [15:0] redist6_yForPe_uid36_fpSqrtTest_b_6_mem_q; - wire [1:0] redist6_yForPe_uid36_fpSqrtTest_b_6_rdcnt_q; - (* preserve *) reg [1:0] redist6_yForPe_uid36_fpSqrtTest_b_6_rdcnt_i; - (* preserve *) reg redist6_yForPe_uid36_fpSqrtTest_b_6_rdcnt_eq; - wire [0:0] redist6_yForPe_uid36_fpSqrtTest_b_6_rdmux_s; - reg [1:0] redist6_yForPe_uid36_fpSqrtTest_b_6_rdmux_q; - reg [1:0] redist6_yForPe_uid36_fpSqrtTest_b_6_wraddr_q; - wire [1:0] redist6_yForPe_uid36_fpSqrtTest_b_6_mem_last_q; - wire [0:0] redist6_yForPe_uid36_fpSqrtTest_b_6_cmp_q; - reg [0:0] redist6_yForPe_uid36_fpSqrtTest_b_6_cmpReg_q; - wire [0:0] redist6_yForPe_uid36_fpSqrtTest_b_6_notEnable_q; - wire [0:0] redist6_yForPe_uid36_fpSqrtTest_b_6_nor_q; - (* preserve_syn_only *) reg [0:0] redist6_yForPe_uid36_fpSqrtTest_b_6_sticky_ena_q; - wire [0:0] redist6_yForPe_uid36_fpSqrtTest_b_6_enaAnd_q; - reg [7:0] redist9_expRMux_uid31_fpSqrtTest_q_10_outputreg_q; - wire redist9_expRMux_uid31_fpSqrtTest_q_10_mem_reset0; - wire [7:0] redist9_expRMux_uid31_fpSqrtTest_q_10_mem_ia; - wire [2:0] redist9_expRMux_uid31_fpSqrtTest_q_10_mem_aa; - wire [2:0] redist9_expRMux_uid31_fpSqrtTest_q_10_mem_ab; - wire [7:0] redist9_expRMux_uid31_fpSqrtTest_q_10_mem_iq; - wire [7:0] redist9_expRMux_uid31_fpSqrtTest_q_10_mem_q; - wire [2:0] redist9_expRMux_uid31_fpSqrtTest_q_10_rdcnt_q; - (* preserve *) reg [2:0] redist9_expRMux_uid31_fpSqrtTest_q_10_rdcnt_i; - (* preserve *) reg redist9_expRMux_uid31_fpSqrtTest_q_10_rdcnt_eq; - wire [0:0] redist9_expRMux_uid31_fpSqrtTest_q_10_rdmux_s; - reg [2:0] redist9_expRMux_uid31_fpSqrtTest_q_10_rdmux_q; - reg [2:0] redist9_expRMux_uid31_fpSqrtTest_q_10_wraddr_q; - wire [3:0] redist9_expRMux_uid31_fpSqrtTest_q_10_mem_last_q; - wire [3:0] redist9_expRMux_uid31_fpSqrtTest_q_10_cmp_b; - wire [0:0] redist9_expRMux_uid31_fpSqrtTest_q_10_cmp_q; - reg [0:0] redist9_expRMux_uid31_fpSqrtTest_q_10_cmpReg_q; - wire [0:0] redist9_expRMux_uid31_fpSqrtTest_q_10_notEnable_q; - wire [0:0] redist9_expRMux_uid31_fpSqrtTest_q_10_nor_q; - (* preserve_syn_only *) reg [0:0] redist9_expRMux_uid31_fpSqrtTest_q_10_sticky_ena_q; - wire [0:0] redist9_expRMux_uid31_fpSqrtTest_q_10_enaAnd_q; - - - // signX_uid7_fpSqrtTest(BITSELECT,6)@0 - assign signX_uid7_fpSqrtTest_b = a[31:31]; - - // redist10_signX_uid7_fpSqrtTest_b_1(DELAY,107) - dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") ) - redist10_signX_uid7_fpSqrtTest_b_1 ( .xin(signX_uid7_fpSqrtTest_b), .xout(redist10_signX_uid7_fpSqrtTest_b_1_q), .ena(en[0]), .clk(clk), .aclr(areset) ); - - // cstAllZWE_uid10_fpSqrtTest(CONSTANT,9) - assign cstAllZWE_uid10_fpSqrtTest_q = 8'b00000000; - - // expX_uid6_fpSqrtTest(BITSELECT,5)@0 - assign expX_uid6_fpSqrtTest_b = a[30:23]; - - // excZ_x_uid13_fpSqrtTest(LOGICAL,12)@0 + 1 - assign excZ_x_uid13_fpSqrtTest_qi = expX_uid6_fpSqrtTest_b == cstAllZWE_uid10_fpSqrtTest_q ? 1'b1 : 1'b0; - dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") ) - excZ_x_uid13_fpSqrtTest_delay ( .xin(excZ_x_uid13_fpSqrtTest_qi), .xout(excZ_x_uid13_fpSqrtTest_q), .ena(en[0]), .clk(clk), .aclr(areset) ); - - // negZero_uid59_fpSqrtTest(LOGICAL,58)@1 + 1 - assign negZero_uid59_fpSqrtTest_qi = excZ_x_uid13_fpSqrtTest_q & redist10_signX_uid7_fpSqrtTest_b_1_q; - dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") ) - negZero_uid59_fpSqrtTest_delay ( .xin(negZero_uid59_fpSqrtTest_qi), .xout(negZero_uid59_fpSqrtTest_q), .ena(en[0]), .clk(clk), .aclr(areset) ); - - // redist1_negZero_uid59_fpSqrtTest_q_9(DELAY,98) - dspba_delay_ver #( .width(1), .depth(8), .reset_kind("ASYNC") ) - redist1_negZero_uid59_fpSqrtTest_q_9 ( .xin(negZero_uid59_fpSqrtTest_q), .xout(redist1_negZero_uid59_fpSqrtTest_q_9_q), .ena(en[0]), .clk(clk), .aclr(areset) ); - - // cstAllOWE_uid8_fpSqrtTest(CONSTANT,7) - assign cstAllOWE_uid8_fpSqrtTest_q = 8'b11111111; - - // expX0PS_uid29_fpSqrtTest(BITSELECT,28)@0 - assign expX0PS_uid29_fpSqrtTest_in = expX_uid6_fpSqrtTest_b[0:0]; - assign expX0PS_uid29_fpSqrtTest_b = expX0PS_uid29_fpSqrtTest_in[0:0]; - - // expOddSelect_uid30_fpSqrtTest(LOGICAL,29)@0 - assign expOddSelect_uid30_fpSqrtTest_q = ~ (expX0PS_uid29_fpSqrtTest_b); - - // frac_x_uid12_fpSqrtTest(BITSELECT,11)@0 - assign frac_x_uid12_fpSqrtTest_b = a[22:0]; - - // addrFull_uid33_fpSqrtTest(BITJOIN,32)@0 - assign addrFull_uid33_fpSqrtTest_q = {expOddSelect_uid30_fpSqrtTest_q, frac_x_uid12_fpSqrtTest_b}; - - // yAddr_uid35_fpSqrtTest(BITSELECT,34)@0 - assign yAddr_uid35_fpSqrtTest_b = addrFull_uid33_fpSqrtTest_q[23:16]; - - // memoryC2_uid68_sqrtTables_lutmem(DUALMEM,94)@0 + 2 - // in j@20000000 - assign memoryC2_uid68_sqrtTables_lutmem_aa = yAddr_uid35_fpSqrtTest_b; - assign memoryC2_uid68_sqrtTables_lutmem_reset0 = areset; - altera_syncram #( - .ram_block_type("M20K"), - .operation_mode("ROM"), - .width_a(12), - .widthad_a(8), - .numwords_a(256), - .lpm_type("altera_syncram"), - .width_byteena_a(1), - .outdata_reg_a("CLOCK0"), - .outdata_aclr_a("CLEAR0"), - .clock_enable_input_a("NORMAL"), - .power_up_uninitialized("FALSE"), - .init_file("acl_fsqrt_memoryC2_uid68_sqrtTables_lutmem.hex"), - .init_file_layout("PORT_A"), - .intended_device_family("Arria 10") - ) memoryC2_uid68_sqrtTables_lutmem_dmem ( - .clocken0(en[0]), - .aclr0(memoryC2_uid68_sqrtTables_lutmem_reset0), - .clock0(clk), - .address_a(memoryC2_uid68_sqrtTables_lutmem_aa), - .q_a(memoryC2_uid68_sqrtTables_lutmem_ir), - .wren_a(), - .wren_b(), - .rden_a(), - .rden_b(), - .data_a(), - .data_b(), - .address_b(), - .clock1(), - .clocken1(), - .clocken2(), - .clocken3(), - .aclr1(), - .addressstall_a(), - .addressstall_b(), - .byteena_a(), - .byteena_b(), - .eccencbypass(), - .eccencparity(), - .sclr(), - .address2_a(), - .address2_b(), - .q_b(), - .eccstatus() - ); - assign memoryC2_uid68_sqrtTables_lutmem_r = memoryC2_uid68_sqrtTables_lutmem_ir[11:0]; - - // yForPe_uid36_fpSqrtTest(BITSELECT,35)@0 - assign yForPe_uid36_fpSqrtTest_in = frac_x_uid12_fpSqrtTest_b[15:0]; - assign yForPe_uid36_fpSqrtTest_b = yForPe_uid36_fpSqrtTest_in[15:0]; - - // redist5_yForPe_uid36_fpSqrtTest_b_2(DELAY,102) - dspba_delay_ver #( .width(16), .depth(2), .reset_kind("ASYNC") ) - redist5_yForPe_uid36_fpSqrtTest_b_2 ( .xin(yForPe_uid36_fpSqrtTest_b), .xout(redist5_yForPe_uid36_fpSqrtTest_b_2_q), .ena(en[0]), .clk(clk), .aclr(areset) ); - - // yT1_uid74_invPolyEval(BITSELECT,73)@2 - assign yT1_uid74_invPolyEval_b = redist5_yForPe_uid36_fpSqrtTest_b_2_q[15:4]; - - // prodXY_uid87_pT1_uid75_invPolyEval_cma(CHAINMULTADD,95)@2 + 3 - assign prodXY_uid87_pT1_uid75_invPolyEval_cma_reset = areset; - assign prodXY_uid87_pT1_uid75_invPolyEval_cma_ena0 = en[0]; - assign prodXY_uid87_pT1_uid75_invPolyEval_cma_ena1 = prodXY_uid87_pT1_uid75_invPolyEval_cma_ena0; - assign prodXY_uid87_pT1_uid75_invPolyEval_cma_ena2 = prodXY_uid87_pT1_uid75_invPolyEval_cma_ena0; - assign prodXY_uid87_pT1_uid75_invPolyEval_cma_l[0] = $signed({1'b0, prodXY_uid87_pT1_uid75_invPolyEval_cma_a1[0][11:0]}); - assign prodXY_uid87_pT1_uid75_invPolyEval_cma_p[0] = prodXY_uid87_pT1_uid75_invPolyEval_cma_l[0] * prodXY_uid87_pT1_uid75_invPolyEval_cma_c1[0]; - assign prodXY_uid87_pT1_uid75_invPolyEval_cma_u[0] = prodXY_uid87_pT1_uid75_invPolyEval_cma_p[0][24:0]; - assign prodXY_uid87_pT1_uid75_invPolyEval_cma_w[0] = prodXY_uid87_pT1_uid75_invPolyEval_cma_u[0]; - assign prodXY_uid87_pT1_uid75_invPolyEval_cma_x[0] = prodXY_uid87_pT1_uid75_invPolyEval_cma_w[0]; - assign prodXY_uid87_pT1_uid75_invPolyEval_cma_y[0] = prodXY_uid87_pT1_uid75_invPolyEval_cma_x[0]; - always @ (posedge clk or posedge areset) - begin - if (areset) - begin - prodXY_uid87_pT1_uid75_invPolyEval_cma_a0 <= '{default: '0}; - prodXY_uid87_pT1_uid75_invPolyEval_cma_c0 <= '{default: '0}; - end - else - begin - if (prodXY_uid87_pT1_uid75_invPolyEval_cma_ena0 == 1'b1) - begin - prodXY_uid87_pT1_uid75_invPolyEval_cma_a0[0] <= yT1_uid74_invPolyEval_b; - prodXY_uid87_pT1_uid75_invPolyEval_cma_c0[0] <= memoryC2_uid68_sqrtTables_lutmem_r; - end - end - end - always @ (posedge clk or posedge areset) - begin - if (areset) - begin - prodXY_uid87_pT1_uid75_invPolyEval_cma_a1 <= '{default: '0}; - prodXY_uid87_pT1_uid75_invPolyEval_cma_c1 <= '{default: '0}; - end - else - begin - if (prodXY_uid87_pT1_uid75_invPolyEval_cma_ena2 == 1'b1) - begin - prodXY_uid87_pT1_uid75_invPolyEval_cma_a1 <= prodXY_uid87_pT1_uid75_invPolyEval_cma_a0; - prodXY_uid87_pT1_uid75_invPolyEval_cma_c1 <= prodXY_uid87_pT1_uid75_invPolyEval_cma_c0; - end - end - end - always @ (posedge clk or posedge areset) - begin - if (areset) - begin - prodXY_uid87_pT1_uid75_invPolyEval_cma_s <= '{default: '0}; - end - else - begin - if (prodXY_uid87_pT1_uid75_invPolyEval_cma_ena1 == 1'b1) - begin - prodXY_uid87_pT1_uid75_invPolyEval_cma_s[0] <= prodXY_uid87_pT1_uid75_invPolyEval_cma_y[0]; - end - end - end - dspba_delay_ver #( .width(24), .depth(0), .reset_kind("ASYNC") ) - prodXY_uid87_pT1_uid75_invPolyEval_cma_delay ( .xin(prodXY_uid87_pT1_uid75_invPolyEval_cma_s[0][23:0]), .xout(prodXY_uid87_pT1_uid75_invPolyEval_cma_qq), .ena(en[0]), .clk(clk), .aclr(areset) ); - assign prodXY_uid87_pT1_uid75_invPolyEval_cma_q = prodXY_uid87_pT1_uid75_invPolyEval_cma_qq[23:0]; - - // osig_uid88_pT1_uid75_invPolyEval(BITSELECT,87)@5 - assign osig_uid88_pT1_uid75_invPolyEval_b = prodXY_uid87_pT1_uid75_invPolyEval_cma_q[23:11]; - - // highBBits_uid77_invPolyEval(BITSELECT,76)@5 - assign highBBits_uid77_invPolyEval_b = osig_uid88_pT1_uid75_invPolyEval_b[12:1]; - - // redist7_yAddr_uid35_fpSqrtTest_b_3(DELAY,104) - dspba_delay_ver #( .width(8), .depth(3), .reset_kind("ASYNC") ) - redist7_yAddr_uid35_fpSqrtTest_b_3 ( .xin(yAddr_uid35_fpSqrtTest_b), .xout(redist7_yAddr_uid35_fpSqrtTest_b_3_q), .ena(en[0]), .clk(clk), .aclr(areset) ); - - // memoryC1_uid65_sqrtTables_lutmem(DUALMEM,93)@3 + 2 - // in j@20000000 - assign memoryC1_uid65_sqrtTables_lutmem_aa = redist7_yAddr_uid35_fpSqrtTest_b_3_q; - assign memoryC1_uid65_sqrtTables_lutmem_reset0 = areset; - altera_syncram #( - .ram_block_type("M20K"), - .operation_mode("ROM"), - .width_a(21), - .widthad_a(8), - .numwords_a(256), - .lpm_type("altera_syncram"), - .width_byteena_a(1), - .outdata_reg_a("CLOCK0"), - .outdata_aclr_a("CLEAR0"), - .clock_enable_input_a("NORMAL"), - .power_up_uninitialized("FALSE"), - .init_file("acl_fsqrt_memoryC1_uid65_sqrtTables_lutmem.hex"), - .init_file_layout("PORT_A"), - .intended_device_family("Arria 10") - ) memoryC1_uid65_sqrtTables_lutmem_dmem ( - .clocken0(en[0]), - .aclr0(memoryC1_uid65_sqrtTables_lutmem_reset0), - .clock0(clk), - .address_a(memoryC1_uid65_sqrtTables_lutmem_aa), - .q_a(memoryC1_uid65_sqrtTables_lutmem_ir), - .wren_a(), - .wren_b(), - .rden_a(), - .rden_b(), - .data_a(), - .data_b(), - .address_b(), - .clock1(), - .clocken1(), - .clocken2(), - .clocken3(), - .aclr1(), - .addressstall_a(), - .addressstall_b(), - .byteena_a(), - .byteena_b(), - .eccencbypass(), - .eccencparity(), - .sclr(), - .address2_a(), - .address2_b(), - .q_b(), - .eccstatus() - ); - assign memoryC1_uid65_sqrtTables_lutmem_r = memoryC1_uid65_sqrtTables_lutmem_ir[20:0]; - - // s1sumAHighB_uid78_invPolyEval(ADD,77)@5 + 1 - assign s1sumAHighB_uid78_invPolyEval_a = {{1{memoryC1_uid65_sqrtTables_lutmem_r[20]}}, memoryC1_uid65_sqrtTables_lutmem_r}; - assign s1sumAHighB_uid78_invPolyEval_b = {{10{highBBits_uid77_invPolyEval_b[11]}}, highBBits_uid77_invPolyEval_b}; - always @ (posedge clk or posedge areset) - begin - if (areset) - begin - s1sumAHighB_uid78_invPolyEval_o <= 22'b0; - end - else if (en == 1'b1) - begin - s1sumAHighB_uid78_invPolyEval_o <= $signed(s1sumAHighB_uid78_invPolyEval_a) + $signed(s1sumAHighB_uid78_invPolyEval_b); - end - end - assign s1sumAHighB_uid78_invPolyEval_q = s1sumAHighB_uid78_invPolyEval_o[21:0]; - - // lowRangeB_uid76_invPolyEval(BITSELECT,75)@5 - assign lowRangeB_uid76_invPolyEval_in = osig_uid88_pT1_uid75_invPolyEval_b[0:0]; - assign lowRangeB_uid76_invPolyEval_b = lowRangeB_uid76_invPolyEval_in[0:0]; - - // redist0_lowRangeB_uid76_invPolyEval_b_1(DELAY,97) - dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") ) - redist0_lowRangeB_uid76_invPolyEval_b_1 ( .xin(lowRangeB_uid76_invPolyEval_b), .xout(redist0_lowRangeB_uid76_invPolyEval_b_1_q), .ena(en[0]), .clk(clk), .aclr(areset) ); - - // s1_uid79_invPolyEval(BITJOIN,78)@6 - assign s1_uid79_invPolyEval_q = {s1sumAHighB_uid78_invPolyEval_q, redist0_lowRangeB_uid76_invPolyEval_b_1_q}; - - // redist6_yForPe_uid36_fpSqrtTest_b_6_notEnable(LOGICAL,115) - assign redist6_yForPe_uid36_fpSqrtTest_b_6_notEnable_q = ~ (en); - - // redist6_yForPe_uid36_fpSqrtTest_b_6_nor(LOGICAL,116) - assign redist6_yForPe_uid36_fpSqrtTest_b_6_nor_q = ~ (redist6_yForPe_uid36_fpSqrtTest_b_6_notEnable_q | redist6_yForPe_uid36_fpSqrtTest_b_6_sticky_ena_q); - - // redist6_yForPe_uid36_fpSqrtTest_b_6_mem_last(CONSTANT,112) - assign redist6_yForPe_uid36_fpSqrtTest_b_6_mem_last_q = 2'b01; - - // redist6_yForPe_uid36_fpSqrtTest_b_6_cmp(LOGICAL,113) - assign redist6_yForPe_uid36_fpSqrtTest_b_6_cmp_q = redist6_yForPe_uid36_fpSqrtTest_b_6_mem_last_q == redist6_yForPe_uid36_fpSqrtTest_b_6_rdmux_q ? 1'b1 : 1'b0; - - // redist6_yForPe_uid36_fpSqrtTest_b_6_cmpReg(REG,114) - always @ (posedge clk or posedge areset) - begin - if (areset) - begin - redist6_yForPe_uid36_fpSqrtTest_b_6_cmpReg_q <= 1'b0; - end - else if (en == 1'b1) - begin - redist6_yForPe_uid36_fpSqrtTest_b_6_cmpReg_q <= redist6_yForPe_uid36_fpSqrtTest_b_6_cmp_q; - end - end - - // redist6_yForPe_uid36_fpSqrtTest_b_6_sticky_ena(REG,117) - always @ (posedge clk or posedge areset) - begin - if (areset) - begin - redist6_yForPe_uid36_fpSqrtTest_b_6_sticky_ena_q <= 1'b0; - end - else if (redist6_yForPe_uid36_fpSqrtTest_b_6_nor_q == 1'b1) - begin - redist6_yForPe_uid36_fpSqrtTest_b_6_sticky_ena_q <= redist6_yForPe_uid36_fpSqrtTest_b_6_cmpReg_q; - end - end - - // redist6_yForPe_uid36_fpSqrtTest_b_6_enaAnd(LOGICAL,118) - assign redist6_yForPe_uid36_fpSqrtTest_b_6_enaAnd_q = redist6_yForPe_uid36_fpSqrtTest_b_6_sticky_ena_q & en; - - // redist6_yForPe_uid36_fpSqrtTest_b_6_rdcnt(COUNTER,109) - // low=0, high=2, step=1, init=0 - always @ (posedge clk or posedge areset) - begin - if (areset) - begin - redist6_yForPe_uid36_fpSqrtTest_b_6_rdcnt_i <= 2'd0; - redist6_yForPe_uid36_fpSqrtTest_b_6_rdcnt_eq <= 1'b0; - end - else if (en == 1'b1) - begin - if (redist6_yForPe_uid36_fpSqrtTest_b_6_rdcnt_i == 2'd1) - begin - redist6_yForPe_uid36_fpSqrtTest_b_6_rdcnt_eq <= 1'b1; - end - else - begin - redist6_yForPe_uid36_fpSqrtTest_b_6_rdcnt_eq <= 1'b0; - end - if (redist6_yForPe_uid36_fpSqrtTest_b_6_rdcnt_eq == 1'b1) - begin - redist6_yForPe_uid36_fpSqrtTest_b_6_rdcnt_i <= $unsigned(redist6_yForPe_uid36_fpSqrtTest_b_6_rdcnt_i) + $unsigned(2'd2); - end - else - begin - redist6_yForPe_uid36_fpSqrtTest_b_6_rdcnt_i <= $unsigned(redist6_yForPe_uid36_fpSqrtTest_b_6_rdcnt_i) + $unsigned(2'd1); - end - end - end - assign redist6_yForPe_uid36_fpSqrtTest_b_6_rdcnt_q = redist6_yForPe_uid36_fpSqrtTest_b_6_rdcnt_i[1:0]; - - // redist6_yForPe_uid36_fpSqrtTest_b_6_rdmux(MUX,110) - assign redist6_yForPe_uid36_fpSqrtTest_b_6_rdmux_s = en; - always @(redist6_yForPe_uid36_fpSqrtTest_b_6_rdmux_s or redist6_yForPe_uid36_fpSqrtTest_b_6_wraddr_q or redist6_yForPe_uid36_fpSqrtTest_b_6_rdcnt_q) - begin - unique case (redist6_yForPe_uid36_fpSqrtTest_b_6_rdmux_s) - 1'b0 : redist6_yForPe_uid36_fpSqrtTest_b_6_rdmux_q = redist6_yForPe_uid36_fpSqrtTest_b_6_wraddr_q; - 1'b1 : redist6_yForPe_uid36_fpSqrtTest_b_6_rdmux_q = redist6_yForPe_uid36_fpSqrtTest_b_6_rdcnt_q; - default : redist6_yForPe_uid36_fpSqrtTest_b_6_rdmux_q = 2'b0; - endcase - end - - // VCC(CONSTANT,1) - assign VCC_q = 1'b1; - - // redist6_yForPe_uid36_fpSqrtTest_b_6_wraddr(REG,111) - always @ (posedge clk or posedge areset) - begin - if (areset) - begin - redist6_yForPe_uid36_fpSqrtTest_b_6_wraddr_q <= 2'b10; - end - else - begin - redist6_yForPe_uid36_fpSqrtTest_b_6_wraddr_q <= redist6_yForPe_uid36_fpSqrtTest_b_6_rdmux_q; - end - end - - // redist6_yForPe_uid36_fpSqrtTest_b_6_mem(DUALMEM,108) - assign redist6_yForPe_uid36_fpSqrtTest_b_6_mem_ia = redist5_yForPe_uid36_fpSqrtTest_b_2_q; - assign redist6_yForPe_uid36_fpSqrtTest_b_6_mem_aa = redist6_yForPe_uid36_fpSqrtTest_b_6_wraddr_q; - assign redist6_yForPe_uid36_fpSqrtTest_b_6_mem_ab = redist6_yForPe_uid36_fpSqrtTest_b_6_rdmux_q; - assign redist6_yForPe_uid36_fpSqrtTest_b_6_mem_reset0 = areset; - altera_syncram #( - .ram_block_type("MLAB"), - .operation_mode("DUAL_PORT"), - .width_a(16), - .widthad_a(2), - .numwords_a(3), - .width_b(16), - .widthad_b(2), - .numwords_b(3), - .lpm_type("altera_syncram"), - .width_byteena_a(1), - .address_reg_b("CLOCK0"), - .indata_reg_b("CLOCK0"), - .rdcontrol_reg_b("CLOCK0"), - .byteena_reg_b("CLOCK0"), - .outdata_reg_b("CLOCK1"), - .outdata_aclr_b("CLEAR1"), - .clock_enable_input_a("NORMAL"), - .clock_enable_input_b("NORMAL"), - .clock_enable_output_b("NORMAL"), - .read_during_write_mode_mixed_ports("DONT_CARE"), - .power_up_uninitialized("TRUE"), - .intended_device_family("Arria 10") - ) redist6_yForPe_uid36_fpSqrtTest_b_6_mem_dmem ( - .clocken1(redist6_yForPe_uid36_fpSqrtTest_b_6_enaAnd_q[0]), - .clocken0(VCC_q[0]), - .clock0(clk), - .aclr1(redist6_yForPe_uid36_fpSqrtTest_b_6_mem_reset0), - .clock1(clk), - .address_a(redist6_yForPe_uid36_fpSqrtTest_b_6_mem_aa), - .data_a(redist6_yForPe_uid36_fpSqrtTest_b_6_mem_ia), - .wren_a(en[0]), - .address_b(redist6_yForPe_uid36_fpSqrtTest_b_6_mem_ab), - .q_b(redist6_yForPe_uid36_fpSqrtTest_b_6_mem_iq), - .wren_b(), - .rden_a(), - .rden_b(), - .data_b(), - .clocken2(), - .clocken3(), - .aclr0(), - .addressstall_a(), - .addressstall_b(), - .byteena_a(), - .byteena_b(), - .eccencbypass(), - .eccencparity(), - .sclr(), - .address2_a(), - .address2_b(), - .q_a(), - .eccstatus() - ); - assign redist6_yForPe_uid36_fpSqrtTest_b_6_mem_q = redist6_yForPe_uid36_fpSqrtTest_b_6_mem_iq[15:0]; - - // GND(CONSTANT,0) - assign GND_q = 1'b0; - - // prodXY_uid90_pT2_uid81_invPolyEval_cma(CHAINMULTADD,96)@6 + 3 - assign prodXY_uid90_pT2_uid81_invPolyEval_cma_reset = areset; - assign prodXY_uid90_pT2_uid81_invPolyEval_cma_ena0 = en[0]; - assign prodXY_uid90_pT2_uid81_invPolyEval_cma_ena1 = prodXY_uid90_pT2_uid81_invPolyEval_cma_ena0; - assign prodXY_uid90_pT2_uid81_invPolyEval_cma_ena2 = prodXY_uid90_pT2_uid81_invPolyEval_cma_ena0; - assign prodXY_uid90_pT2_uid81_invPolyEval_cma_l[0] = $signed({1'b0, prodXY_uid90_pT2_uid81_invPolyEval_cma_a1[0][15:0]}); - assign prodXY_uid90_pT2_uid81_invPolyEval_cma_p[0] = prodXY_uid90_pT2_uid81_invPolyEval_cma_l[0] * prodXY_uid90_pT2_uid81_invPolyEval_cma_c1[0]; - assign prodXY_uid90_pT2_uid81_invPolyEval_cma_u[0] = prodXY_uid90_pT2_uid81_invPolyEval_cma_p[0][39:0]; - assign prodXY_uid90_pT2_uid81_invPolyEval_cma_w[0] = prodXY_uid90_pT2_uid81_invPolyEval_cma_u[0]; - assign prodXY_uid90_pT2_uid81_invPolyEval_cma_x[0] = prodXY_uid90_pT2_uid81_invPolyEval_cma_w[0]; - assign prodXY_uid90_pT2_uid81_invPolyEval_cma_y[0] = prodXY_uid90_pT2_uid81_invPolyEval_cma_x[0]; - always @ (posedge clk or posedge areset) - begin - if (areset) - begin - prodXY_uid90_pT2_uid81_invPolyEval_cma_a0 <= '{default: '0}; - prodXY_uid90_pT2_uid81_invPolyEval_cma_c0 <= '{default: '0}; - end - else - begin - if (prodXY_uid90_pT2_uid81_invPolyEval_cma_ena0 == 1'b1) - begin - prodXY_uid90_pT2_uid81_invPolyEval_cma_a0[0] <= redist6_yForPe_uid36_fpSqrtTest_b_6_mem_q; - prodXY_uid90_pT2_uid81_invPolyEval_cma_c0[0] <= s1_uid79_invPolyEval_q; - end - end - end - always @ (posedge clk or posedge areset) - begin - if (areset) - begin - prodXY_uid90_pT2_uid81_invPolyEval_cma_a1 <= '{default: '0}; - prodXY_uid90_pT2_uid81_invPolyEval_cma_c1 <= '{default: '0}; - end - else - begin - if (prodXY_uid90_pT2_uid81_invPolyEval_cma_ena2 == 1'b1) - begin - prodXY_uid90_pT2_uid81_invPolyEval_cma_a1 <= prodXY_uid90_pT2_uid81_invPolyEval_cma_a0; - prodXY_uid90_pT2_uid81_invPolyEval_cma_c1 <= prodXY_uid90_pT2_uid81_invPolyEval_cma_c0; - end - end - end - always @ (posedge clk or posedge areset) - begin - if (areset) - begin - prodXY_uid90_pT2_uid81_invPolyEval_cma_s <= '{default: '0}; - end - else - begin - if (prodXY_uid90_pT2_uid81_invPolyEval_cma_ena1 == 1'b1) - begin - prodXY_uid90_pT2_uid81_invPolyEval_cma_s[0] <= prodXY_uid90_pT2_uid81_invPolyEval_cma_y[0]; - end - end - end - dspba_delay_ver #( .width(39), .depth(0), .reset_kind("ASYNC") ) - prodXY_uid90_pT2_uid81_invPolyEval_cma_delay ( .xin(prodXY_uid90_pT2_uid81_invPolyEval_cma_s[0][38:0]), .xout(prodXY_uid90_pT2_uid81_invPolyEval_cma_qq), .ena(en[0]), .clk(clk), .aclr(areset) ); - assign prodXY_uid90_pT2_uid81_invPolyEval_cma_q = prodXY_uid90_pT2_uid81_invPolyEval_cma_qq[38:0]; - - // osig_uid91_pT2_uid81_invPolyEval(BITSELECT,90)@9 - assign osig_uid91_pT2_uid81_invPolyEval_b = prodXY_uid90_pT2_uid81_invPolyEval_cma_q[38:15]; - - // highBBits_uid83_invPolyEval(BITSELECT,82)@9 - assign highBBits_uid83_invPolyEval_b = osig_uid91_pT2_uid81_invPolyEval_b[23:2]; - - // redist8_yAddr_uid35_fpSqrtTest_b_7(DELAY,105) - dspba_delay_ver #( .width(8), .depth(4), .reset_kind("ASYNC") ) - redist8_yAddr_uid35_fpSqrtTest_b_7 ( .xin(redist7_yAddr_uid35_fpSqrtTest_b_3_q), .xout(redist8_yAddr_uid35_fpSqrtTest_b_7_q), .ena(en[0]), .clk(clk), .aclr(areset) ); - - // memoryC0_uid62_sqrtTables_lutmem(DUALMEM,92)@7 + 2 - // in j@20000000 - assign memoryC0_uid62_sqrtTables_lutmem_aa = redist8_yAddr_uid35_fpSqrtTest_b_7_q; - assign memoryC0_uid62_sqrtTables_lutmem_reset0 = areset; - altera_syncram #( - .ram_block_type("M20K"), - .operation_mode("ROM"), - .width_a(29), - .widthad_a(8), - .numwords_a(256), - .lpm_type("altera_syncram"), - .width_byteena_a(1), - .outdata_reg_a("CLOCK0"), - .outdata_aclr_a("CLEAR0"), - .clock_enable_input_a("NORMAL"), - .power_up_uninitialized("FALSE"), - .init_file("acl_fsqrt_memoryC0_uid62_sqrtTables_lutmem.hex"), - .init_file_layout("PORT_A"), - .intended_device_family("Arria 10") - ) memoryC0_uid62_sqrtTables_lutmem_dmem ( - .clocken0(en[0]), - .aclr0(memoryC0_uid62_sqrtTables_lutmem_reset0), - .clock0(clk), - .address_a(memoryC0_uid62_sqrtTables_lutmem_aa), - .q_a(memoryC0_uid62_sqrtTables_lutmem_ir), - .wren_a(), - .wren_b(), - .rden_a(), - .rden_b(), - .data_a(), - .data_b(), - .address_b(), - .clock1(), - .clocken1(), - .clocken2(), - .clocken3(), - .aclr1(), - .addressstall_a(), - .addressstall_b(), - .byteena_a(), - .byteena_b(), - .eccencbypass(), - .eccencparity(), - .sclr(), - .address2_a(), - .address2_b(), - .q_b(), - .eccstatus() - ); - assign memoryC0_uid62_sqrtTables_lutmem_r = memoryC0_uid62_sqrtTables_lutmem_ir[28:0]; - - // s2sumAHighB_uid84_invPolyEval(ADD,83)@9 - assign s2sumAHighB_uid84_invPolyEval_a = {{1{memoryC0_uid62_sqrtTables_lutmem_r[28]}}, memoryC0_uid62_sqrtTables_lutmem_r}; - assign s2sumAHighB_uid84_invPolyEval_b = {{8{highBBits_uid83_invPolyEval_b[21]}}, highBBits_uid83_invPolyEval_b}; - assign s2sumAHighB_uid84_invPolyEval_o = $signed(s2sumAHighB_uid84_invPolyEval_a) + $signed(s2sumAHighB_uid84_invPolyEval_b); - assign s2sumAHighB_uid84_invPolyEval_q = s2sumAHighB_uid84_invPolyEval_o[29:0]; - - // lowRangeB_uid82_invPolyEval(BITSELECT,81)@9 - assign lowRangeB_uid82_invPolyEval_in = osig_uid91_pT2_uid81_invPolyEval_b[1:0]; - assign lowRangeB_uid82_invPolyEval_b = lowRangeB_uid82_invPolyEval_in[1:0]; - - // s2_uid85_invPolyEval(BITJOIN,84)@9 - assign s2_uid85_invPolyEval_q = {s2sumAHighB_uid84_invPolyEval_q, lowRangeB_uid82_invPolyEval_b}; - - // expInc_uid38_fpSqrtTest(BITSELECT,37)@9 - assign expInc_uid38_fpSqrtTest_in = s2_uid85_invPolyEval_q[30:0]; - assign expInc_uid38_fpSqrtTest_b = expInc_uid38_fpSqrtTest_in[30:30]; - - // redist4_expInc_uid38_fpSqrtTest_b_1(DELAY,101) - dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") ) - redist4_expInc_uid38_fpSqrtTest_b_1 ( .xin(expInc_uid38_fpSqrtTest_b), .xout(redist4_expInc_uid38_fpSqrtTest_b_1_q), .ena(en[0]), .clk(clk), .aclr(areset) ); - - // redist9_expRMux_uid31_fpSqrtTest_q_10_notEnable(LOGICAL,127) - assign redist9_expRMux_uid31_fpSqrtTest_q_10_notEnable_q = ~ (en); - - // redist9_expRMux_uid31_fpSqrtTest_q_10_nor(LOGICAL,128) - assign redist9_expRMux_uid31_fpSqrtTest_q_10_nor_q = ~ (redist9_expRMux_uid31_fpSqrtTest_q_10_notEnable_q | redist9_expRMux_uid31_fpSqrtTest_q_10_sticky_ena_q); - - // redist9_expRMux_uid31_fpSqrtTest_q_10_mem_last(CONSTANT,124) - assign redist9_expRMux_uid31_fpSqrtTest_q_10_mem_last_q = 4'b0101; - - // redist9_expRMux_uid31_fpSqrtTest_q_10_cmp(LOGICAL,125) - assign redist9_expRMux_uid31_fpSqrtTest_q_10_cmp_b = {1'b0, redist9_expRMux_uid31_fpSqrtTest_q_10_rdmux_q}; - assign redist9_expRMux_uid31_fpSqrtTest_q_10_cmp_q = redist9_expRMux_uid31_fpSqrtTest_q_10_mem_last_q == redist9_expRMux_uid31_fpSqrtTest_q_10_cmp_b ? 1'b1 : 1'b0; - - // redist9_expRMux_uid31_fpSqrtTest_q_10_cmpReg(REG,126) - always @ (posedge clk or posedge areset) - begin - if (areset) - begin - redist9_expRMux_uid31_fpSqrtTest_q_10_cmpReg_q <= 1'b0; - end - else if (en == 1'b1) - begin - redist9_expRMux_uid31_fpSqrtTest_q_10_cmpReg_q <= redist9_expRMux_uid31_fpSqrtTest_q_10_cmp_q; - end - end - - // redist9_expRMux_uid31_fpSqrtTest_q_10_sticky_ena(REG,129) - always @ (posedge clk or posedge areset) - begin - if (areset) - begin - redist9_expRMux_uid31_fpSqrtTest_q_10_sticky_ena_q <= 1'b0; - end - else if (redist9_expRMux_uid31_fpSqrtTest_q_10_nor_q == 1'b1) - begin - redist9_expRMux_uid31_fpSqrtTest_q_10_sticky_ena_q <= redist9_expRMux_uid31_fpSqrtTest_q_10_cmpReg_q; - end - end - - // redist9_expRMux_uid31_fpSqrtTest_q_10_enaAnd(LOGICAL,130) - assign redist9_expRMux_uid31_fpSqrtTest_q_10_enaAnd_q = redist9_expRMux_uid31_fpSqrtTest_q_10_sticky_ena_q & en; - - // redist9_expRMux_uid31_fpSqrtTest_q_10_rdcnt(COUNTER,121) - // low=0, high=6, step=1, init=0 - always @ (posedge clk or posedge areset) - begin - if (areset) - begin - redist9_expRMux_uid31_fpSqrtTest_q_10_rdcnt_i <= 3'd0; - redist9_expRMux_uid31_fpSqrtTest_q_10_rdcnt_eq <= 1'b0; - end - else if (en == 1'b1) - begin - if (redist9_expRMux_uid31_fpSqrtTest_q_10_rdcnt_i == 3'd5) - begin - redist9_expRMux_uid31_fpSqrtTest_q_10_rdcnt_eq <= 1'b1; - end - else - begin - redist9_expRMux_uid31_fpSqrtTest_q_10_rdcnt_eq <= 1'b0; - end - if (redist9_expRMux_uid31_fpSqrtTest_q_10_rdcnt_eq == 1'b1) - begin - redist9_expRMux_uid31_fpSqrtTest_q_10_rdcnt_i <= $unsigned(redist9_expRMux_uid31_fpSqrtTest_q_10_rdcnt_i) + $unsigned(3'd2); - end - else - begin - redist9_expRMux_uid31_fpSqrtTest_q_10_rdcnt_i <= $unsigned(redist9_expRMux_uid31_fpSqrtTest_q_10_rdcnt_i) + $unsigned(3'd1); - end - end - end - assign redist9_expRMux_uid31_fpSqrtTest_q_10_rdcnt_q = redist9_expRMux_uid31_fpSqrtTest_q_10_rdcnt_i[2:0]; - - // redist9_expRMux_uid31_fpSqrtTest_q_10_rdmux(MUX,122) - assign redist9_expRMux_uid31_fpSqrtTest_q_10_rdmux_s = en; - always @(redist9_expRMux_uid31_fpSqrtTest_q_10_rdmux_s or redist9_expRMux_uid31_fpSqrtTest_q_10_wraddr_q or redist9_expRMux_uid31_fpSqrtTest_q_10_rdcnt_q) - begin - unique case (redist9_expRMux_uid31_fpSqrtTest_q_10_rdmux_s) - 1'b0 : redist9_expRMux_uid31_fpSqrtTest_q_10_rdmux_q = redist9_expRMux_uid31_fpSqrtTest_q_10_wraddr_q; - 1'b1 : redist9_expRMux_uid31_fpSqrtTest_q_10_rdmux_q = redist9_expRMux_uid31_fpSqrtTest_q_10_rdcnt_q; - default : redist9_expRMux_uid31_fpSqrtTest_q_10_rdmux_q = 3'b0; - endcase - end - - // sBiasM1_uid26_fpSqrtTest(CONSTANT,25) - assign sBiasM1_uid26_fpSqrtTest_q = 8'b01111110; - - // expOddSig_uid27_fpSqrtTest(ADD,26)@0 - assign expOddSig_uid27_fpSqrtTest_a = {1'b0, expX_uid6_fpSqrtTest_b}; - assign expOddSig_uid27_fpSqrtTest_b = {1'b0, sBiasM1_uid26_fpSqrtTest_q}; - assign expOddSig_uid27_fpSqrtTest_o = $unsigned(expOddSig_uid27_fpSqrtTest_a) + $unsigned(expOddSig_uid27_fpSqrtTest_b); - assign expOddSig_uid27_fpSqrtTest_q = expOddSig_uid27_fpSqrtTest_o[8:0]; - - // expROdd_uid28_fpSqrtTest(BITSELECT,27)@0 - assign expROdd_uid28_fpSqrtTest_b = expOddSig_uid27_fpSqrtTest_q[8:1]; - - // sBias_uid22_fpSqrtTest(CONSTANT,21) - assign sBias_uid22_fpSqrtTest_q = 8'b01111111; - - // expEvenSig_uid24_fpSqrtTest(ADD,23)@0 - assign expEvenSig_uid24_fpSqrtTest_a = {1'b0, expX_uid6_fpSqrtTest_b}; - assign expEvenSig_uid24_fpSqrtTest_b = {1'b0, sBias_uid22_fpSqrtTest_q}; - assign expEvenSig_uid24_fpSqrtTest_o = $unsigned(expEvenSig_uid24_fpSqrtTest_a) + $unsigned(expEvenSig_uid24_fpSqrtTest_b); - assign expEvenSig_uid24_fpSqrtTest_q = expEvenSig_uid24_fpSqrtTest_o[8:0]; - - // expREven_uid25_fpSqrtTest(BITSELECT,24)@0 - assign expREven_uid25_fpSqrtTest_b = expEvenSig_uid24_fpSqrtTest_q[8:1]; - - // expRMux_uid31_fpSqrtTest(MUX,30)@0 + 1 - assign expRMux_uid31_fpSqrtTest_s = expOddSelect_uid30_fpSqrtTest_q; - always @ (posedge clk or posedge areset) - begin - if (areset) - begin - expRMux_uid31_fpSqrtTest_q <= 8'b0; - end - else if (en == 1'b1) - begin - unique case (expRMux_uid31_fpSqrtTest_s) - 1'b0 : expRMux_uid31_fpSqrtTest_q <= expREven_uid25_fpSqrtTest_b; - 1'b1 : expRMux_uid31_fpSqrtTest_q <= expROdd_uid28_fpSqrtTest_b; - default : expRMux_uid31_fpSqrtTest_q <= 8'b0; - endcase - end - end - - // redist9_expRMux_uid31_fpSqrtTest_q_10_wraddr(REG,123) - always @ (posedge clk or posedge areset) - begin - if (areset) - begin - redist9_expRMux_uid31_fpSqrtTest_q_10_wraddr_q <= 3'b110; - end - else - begin - redist9_expRMux_uid31_fpSqrtTest_q_10_wraddr_q <= redist9_expRMux_uid31_fpSqrtTest_q_10_rdmux_q; - end - end - - // redist9_expRMux_uid31_fpSqrtTest_q_10_mem(DUALMEM,120) - assign redist9_expRMux_uid31_fpSqrtTest_q_10_mem_ia = expRMux_uid31_fpSqrtTest_q; - assign redist9_expRMux_uid31_fpSqrtTest_q_10_mem_aa = redist9_expRMux_uid31_fpSqrtTest_q_10_wraddr_q; - assign redist9_expRMux_uid31_fpSqrtTest_q_10_mem_ab = redist9_expRMux_uid31_fpSqrtTest_q_10_rdmux_q; - assign redist9_expRMux_uid31_fpSqrtTest_q_10_mem_reset0 = areset; - altera_syncram #( - .ram_block_type("MLAB"), - .operation_mode("DUAL_PORT"), - .width_a(8), - .widthad_a(3), - .numwords_a(7), - .width_b(8), - .widthad_b(3), - .numwords_b(7), - .lpm_type("altera_syncram"), - .width_byteena_a(1), - .address_reg_b("CLOCK0"), - .indata_reg_b("CLOCK0"), - .rdcontrol_reg_b("CLOCK0"), - .byteena_reg_b("CLOCK0"), - .outdata_reg_b("CLOCK1"), - .outdata_aclr_b("CLEAR1"), - .clock_enable_input_a("NORMAL"), - .clock_enable_input_b("NORMAL"), - .clock_enable_output_b("NORMAL"), - .read_during_write_mode_mixed_ports("DONT_CARE"), - .power_up_uninitialized("TRUE"), - .intended_device_family("Arria 10") - ) redist9_expRMux_uid31_fpSqrtTest_q_10_mem_dmem ( - .clocken1(redist9_expRMux_uid31_fpSqrtTest_q_10_enaAnd_q[0]), - .clocken0(VCC_q[0]), - .clock0(clk), - .aclr1(redist9_expRMux_uid31_fpSqrtTest_q_10_mem_reset0), - .clock1(clk), - .address_a(redist9_expRMux_uid31_fpSqrtTest_q_10_mem_aa), - .data_a(redist9_expRMux_uid31_fpSqrtTest_q_10_mem_ia), - .wren_a(en[0]), - .address_b(redist9_expRMux_uid31_fpSqrtTest_q_10_mem_ab), - .q_b(redist9_expRMux_uid31_fpSqrtTest_q_10_mem_iq), - .wren_b(), - .rden_a(), - .rden_b(), - .data_b(), - .clocken2(), - .clocken3(), - .aclr0(), - .addressstall_a(), - .addressstall_b(), - .byteena_a(), - .byteena_b(), - .eccencbypass(), - .eccencparity(), - .sclr(), - .address2_a(), - .address2_b(), - .q_a(), - .eccstatus() - ); - assign redist9_expRMux_uid31_fpSqrtTest_q_10_mem_q = redist9_expRMux_uid31_fpSqrtTest_q_10_mem_iq[7:0]; - - // redist9_expRMux_uid31_fpSqrtTest_q_10_outputreg(DELAY,119) - dspba_delay_ver #( .width(8), .depth(1), .reset_kind("ASYNC") ) - redist9_expRMux_uid31_fpSqrtTest_q_10_outputreg ( .xin(redist9_expRMux_uid31_fpSqrtTest_q_10_mem_q), .xout(redist9_expRMux_uid31_fpSqrtTest_q_10_outputreg_q), .ena(en[0]), .clk(clk), .aclr(areset) ); - - // expR_uid40_fpSqrtTest(ADD,39)@10 - assign expR_uid40_fpSqrtTest_a = {1'b0, redist9_expRMux_uid31_fpSqrtTest_q_10_outputreg_q}; - assign expR_uid40_fpSqrtTest_b = {8'b00000000, redist4_expInc_uid38_fpSqrtTest_b_1_q}; - assign expR_uid40_fpSqrtTest_o = $unsigned(expR_uid40_fpSqrtTest_a) + $unsigned(expR_uid40_fpSqrtTest_b); - assign expR_uid40_fpSqrtTest_q = expR_uid40_fpSqrtTest_o[8:0]; - - // expRR_uid51_fpSqrtTest(BITSELECT,50)@10 - assign expRR_uid51_fpSqrtTest_in = expR_uid40_fpSqrtTest_q[7:0]; - assign expRR_uid51_fpSqrtTest_b = expRR_uid51_fpSqrtTest_in[7:0]; - - // expXIsMax_uid14_fpSqrtTest(LOGICAL,13)@0 + 1 - assign expXIsMax_uid14_fpSqrtTest_qi = expX_uid6_fpSqrtTest_b == cstAllOWE_uid8_fpSqrtTest_q ? 1'b1 : 1'b0; - dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") ) - expXIsMax_uid14_fpSqrtTest_delay ( .xin(expXIsMax_uid14_fpSqrtTest_qi), .xout(expXIsMax_uid14_fpSqrtTest_q), .ena(en[0]), .clk(clk), .aclr(areset) ); - - // invExpXIsMax_uid19_fpSqrtTest(LOGICAL,18)@1 - assign invExpXIsMax_uid19_fpSqrtTest_q = ~ (expXIsMax_uid14_fpSqrtTest_q); - - // InvExpXIsZero_uid20_fpSqrtTest(LOGICAL,19)@1 - assign InvExpXIsZero_uid20_fpSqrtTest_q = ~ (excZ_x_uid13_fpSqrtTest_q); - - // excR_x_uid21_fpSqrtTest(LOGICAL,20)@1 - assign excR_x_uid21_fpSqrtTest_q = InvExpXIsZero_uid20_fpSqrtTest_q & invExpXIsMax_uid19_fpSqrtTest_q; - - // minReg_uid43_fpSqrtTest(LOGICAL,42)@1 - assign minReg_uid43_fpSqrtTest_q = excR_x_uid21_fpSqrtTest_q & redist10_signX_uid7_fpSqrtTest_b_1_q; - - // cstZeroWF_uid9_fpSqrtTest(CONSTANT,8) - assign cstZeroWF_uid9_fpSqrtTest_q = 23'b00000000000000000000000; - - // fracXIsZero_uid15_fpSqrtTest(LOGICAL,14)@0 + 1 - assign fracXIsZero_uid15_fpSqrtTest_qi = cstZeroWF_uid9_fpSqrtTest_q == frac_x_uid12_fpSqrtTest_b ? 1'b1 : 1'b0; - dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") ) - fracXIsZero_uid15_fpSqrtTest_delay ( .xin(fracXIsZero_uid15_fpSqrtTest_qi), .xout(fracXIsZero_uid15_fpSqrtTest_q), .ena(en[0]), .clk(clk), .aclr(areset) ); - - // excI_x_uid17_fpSqrtTest(LOGICAL,16)@1 - assign excI_x_uid17_fpSqrtTest_q = expXIsMax_uid14_fpSqrtTest_q & fracXIsZero_uid15_fpSqrtTest_q; - - // minInf_uid44_fpSqrtTest(LOGICAL,43)@1 - assign minInf_uid44_fpSqrtTest_q = excI_x_uid17_fpSqrtTest_q & redist10_signX_uid7_fpSqrtTest_b_1_q; - - // fracXIsNotZero_uid16_fpSqrtTest(LOGICAL,15)@1 - assign fracXIsNotZero_uid16_fpSqrtTest_q = ~ (fracXIsZero_uid15_fpSqrtTest_q); - - // excN_x_uid18_fpSqrtTest(LOGICAL,17)@1 - assign excN_x_uid18_fpSqrtTest_q = expXIsMax_uid14_fpSqrtTest_q & fracXIsNotZero_uid16_fpSqrtTest_q; - - // excRNaN_uid45_fpSqrtTest(LOGICAL,44)@1 - assign excRNaN_uid45_fpSqrtTest_q = excN_x_uid18_fpSqrtTest_q | minInf_uid44_fpSqrtTest_q | minReg_uid43_fpSqrtTest_q; - - // invSignX_uid41_fpSqrtTest(LOGICAL,40)@1 - assign invSignX_uid41_fpSqrtTest_q = ~ (redist10_signX_uid7_fpSqrtTest_b_1_q); - - // inInfAndNotNeg_uid42_fpSqrtTest(LOGICAL,41)@1 - assign inInfAndNotNeg_uid42_fpSqrtTest_q = excI_x_uid17_fpSqrtTest_q & invSignX_uid41_fpSqrtTest_q; - - // excConc_uid46_fpSqrtTest(BITJOIN,45)@1 - assign excConc_uid46_fpSqrtTest_q = {excRNaN_uid45_fpSqrtTest_q, inInfAndNotNeg_uid42_fpSqrtTest_q, excZ_x_uid13_fpSqrtTest_q}; - - // fracSelIn_uid47_fpSqrtTest(BITJOIN,46)@1 - assign fracSelIn_uid47_fpSqrtTest_q = {redist10_signX_uid7_fpSqrtTest_b_1_q, excConc_uid46_fpSqrtTest_q}; - - // fracSel_uid48_fpSqrtTest(LOOKUP,47)@1 + 1 - always @ (posedge clk or posedge areset) - begin - if (areset) - begin - fracSel_uid48_fpSqrtTest_q <= 2'b01; - end - else if (en == 1'b1) - begin - unique case (fracSelIn_uid47_fpSqrtTest_q) - 4'b0000 : fracSel_uid48_fpSqrtTest_q <= 2'b01; - 4'b0001 : fracSel_uid48_fpSqrtTest_q <= 2'b00; - 4'b0010 : fracSel_uid48_fpSqrtTest_q <= 2'b10; - 4'b0011 : fracSel_uid48_fpSqrtTest_q <= 2'b00; - 4'b0100 : fracSel_uid48_fpSqrtTest_q <= 2'b11; - 4'b0101 : fracSel_uid48_fpSqrtTest_q <= 2'b00; - 4'b0110 : fracSel_uid48_fpSqrtTest_q <= 2'b10; - 4'b0111 : fracSel_uid48_fpSqrtTest_q <= 2'b00; - 4'b1000 : fracSel_uid48_fpSqrtTest_q <= 2'b11; - 4'b1001 : fracSel_uid48_fpSqrtTest_q <= 2'b00; - 4'b1010 : fracSel_uid48_fpSqrtTest_q <= 2'b11; - 4'b1011 : fracSel_uid48_fpSqrtTest_q <= 2'b11; - 4'b1100 : fracSel_uid48_fpSqrtTest_q <= 2'b11; - 4'b1101 : fracSel_uid48_fpSqrtTest_q <= 2'b11; - 4'b1110 : fracSel_uid48_fpSqrtTest_q <= 2'b11; - 4'b1111 : fracSel_uid48_fpSqrtTest_q <= 2'b11; - default : begin - // unreachable - fracSel_uid48_fpSqrtTest_q <= 2'bxx; - end - endcase - end - end - - // redist2_fracSel_uid48_fpSqrtTest_q_9(DELAY,99) - dspba_delay_ver #( .width(2), .depth(8), .reset_kind("ASYNC") ) - redist2_fracSel_uid48_fpSqrtTest_q_9 ( .xin(fracSel_uid48_fpSqrtTest_q), .xout(redist2_fracSel_uid48_fpSqrtTest_q_9_q), .ena(en[0]), .clk(clk), .aclr(areset) ); - - // expRPostExc_uid53_fpSqrtTest(MUX,52)@10 - assign expRPostExc_uid53_fpSqrtTest_s = redist2_fracSel_uid48_fpSqrtTest_q_9_q; - always @(expRPostExc_uid53_fpSqrtTest_s or en or cstAllZWE_uid10_fpSqrtTest_q or expRR_uid51_fpSqrtTest_b or cstAllOWE_uid8_fpSqrtTest_q) - begin - unique case (expRPostExc_uid53_fpSqrtTest_s) - 2'b00 : expRPostExc_uid53_fpSqrtTest_q = cstAllZWE_uid10_fpSqrtTest_q; - 2'b01 : expRPostExc_uid53_fpSqrtTest_q = expRR_uid51_fpSqrtTest_b; - 2'b10 : expRPostExc_uid53_fpSqrtTest_q = cstAllOWE_uid8_fpSqrtTest_q; - 2'b11 : expRPostExc_uid53_fpSqrtTest_q = cstAllOWE_uid8_fpSqrtTest_q; - default : expRPostExc_uid53_fpSqrtTest_q = 8'b0; - endcase - end - - // fracNaN_uid54_fpSqrtTest(CONSTANT,53) - assign fracNaN_uid54_fpSqrtTest_q = 23'b00000000000000000000001; - - // fracRPostProcessings_uid39_fpSqrtTest(BITSELECT,38)@9 - assign fracRPostProcessings_uid39_fpSqrtTest_in = s2_uid85_invPolyEval_q[28:0]; - assign fracRPostProcessings_uid39_fpSqrtTest_b = fracRPostProcessings_uid39_fpSqrtTest_in[28:6]; - - // redist3_fracRPostProcessings_uid39_fpSqrtTest_b_1(DELAY,100) - dspba_delay_ver #( .width(23), .depth(1), .reset_kind("ASYNC") ) - redist3_fracRPostProcessings_uid39_fpSqrtTest_b_1 ( .xin(fracRPostProcessings_uid39_fpSqrtTest_b), .xout(redist3_fracRPostProcessings_uid39_fpSqrtTest_b_1_q), .ena(en[0]), .clk(clk), .aclr(areset) ); - - // fracRPostExc_uid58_fpSqrtTest(MUX,57)@10 - assign fracRPostExc_uid58_fpSqrtTest_s = redist2_fracSel_uid48_fpSqrtTest_q_9_q; - always @(fracRPostExc_uid58_fpSqrtTest_s or en or cstZeroWF_uid9_fpSqrtTest_q or redist3_fracRPostProcessings_uid39_fpSqrtTest_b_1_q or fracNaN_uid54_fpSqrtTest_q) - begin - unique case (fracRPostExc_uid58_fpSqrtTest_s) - 2'b00 : fracRPostExc_uid58_fpSqrtTest_q = cstZeroWF_uid9_fpSqrtTest_q; - 2'b01 : fracRPostExc_uid58_fpSqrtTest_q = redist3_fracRPostProcessings_uid39_fpSqrtTest_b_1_q; - 2'b10 : fracRPostExc_uid58_fpSqrtTest_q = cstZeroWF_uid9_fpSqrtTest_q; - 2'b11 : fracRPostExc_uid58_fpSqrtTest_q = fracNaN_uid54_fpSqrtTest_q; - default : fracRPostExc_uid58_fpSqrtTest_q = 23'b0; - endcase - end - - // RSqrt_uid60_fpSqrtTest(BITJOIN,59)@10 - assign RSqrt_uid60_fpSqrtTest_q = {redist1_negZero_uid59_fpSqrtTest_q_9_q, expRPostExc_uid53_fpSqrtTest_q, fracRPostExc_uid58_fpSqrtTest_q}; - - // xOut(GPOUT,4)@10 - assign q = RSqrt_uid60_fpSqrtTest_q; - -endmodule diff --git a/hw/rtl/fp_cores/altera/acl_gen.log b/hw/rtl/fp_cores/altera/acl_gen.log deleted file mode 100644 index eb65a009..00000000 --- a/hw/rtl/fp_cores/altera/acl_gen.log +++ /dev/null @@ -1,169 +0,0 @@ -starting execution ... -build model options ... -argc=21 -Generation context: - HardFP is enabled enabling set to true - Faithful rounding constraint detected - Will not generate valid and channel signals - The new component name is acl_s10_fdiv - Frequency 250MHz - Deployment FPGA Stratix10 -Estimated resources LUTs 681, DSPs 5, RAMBits 32768, RAMBlocks 3 -The pipeline depth of the block is 25 cycle(s) -@@start -@name FPDiv@ -@latency 25@ -@LUT 681@ -@DSP 5@ -@RAMBits 32768@ -@RAMBlockUsage 3@ -@enable 1@ -@subnormals 0@ -@error 1.00@ -@rounding NA@ -@method polynomial approximation@ -@inPort 0 fpieee 8 23@ -@inPort 1 fpieee 8 23@ -@outPort 0 fpieee 8 23@ -@nochanvalid 1@ -@@end -starting execution ... -build model options ... -argc=20 -Generation context: - HardFP is enabled enabling set to true - Faithful rounding constraint detected - Will not generate valid and channel signals - The new component name is acl_s10_fsqrt - Frequency 250MHz - Deployment FPGA Stratix10 -Estimated resources LUTs 349, DSPs 3, RAMBits 15872, RAMBlocks 3 -The pipeline depth of the block is 17 cycle(s) -@@start -@name FPSqrt@ -@latency 17@ -@LUT 349@ -@DSP 3@ -@RAMBits 15872@ -@RAMBlockUsage 3@ -@enable 1@ -@subnormals 0@ -@error 1.00@ -@rounding NA@ -@method polynomial approximation@ -@inPort 0 fpieee 8 23@ -@outPort 0 fpieee 8 23@ -@nochanvalid 1@ -@@end -starting execution ... -build model options ... -argc=23 -Generation context: - HardFP is enabled enabling set to true - Faithful rounding constraint detected - Will not generate valid and channel signals - The new component name is acl_s10_ftoi - Frequency 250MHz - Deployment FPGA Stratix10 -Estimated resources LUTs 344, DSPs 0, RAMBits 0, RAMBlocks 0 -The pipeline depth of the block is 3 cycle(s) -@@start -@name FPToFXP@ -@latency 3@ -@LUT 344@ -@DSP 0@ -@RAMBits 0@ -@RAMBlockUsage 0@ -@enable 1@ -@subnormals 0@ -@error 1.00@ -@rounding NA@ -@method default@ -@inPort 0 fpieee 8 23@ -@outPort 0 fxp 32 0 1@ -@nochanvalid 1@ -@@end -starting execution ... -build model options ... -argc=23 -Generation context: - HardFP is enabled enabling set to true - Faithful rounding constraint detected - Will not generate valid and channel signals - The new component name is acl_s10_ftou - Frequency 250MHz - Deployment FPGA Stratix10 -Estimated resources LUTs 272, DSPs 0, RAMBits 0, RAMBlocks 0 -The pipeline depth of the block is 3 cycle(s) -@@start -@name FPToFXP@ -@latency 3@ -@LUT 272@ -@DSP 0@ -@RAMBits 0@ -@RAMBlockUsage 0@ -@enable 1@ -@subnormals 0@ -@error 1.00@ -@rounding NA@ -@method default@ -@inPort 0 fpieee 8 23@ -@outPort 0 fxp 32 0 0@ -@nochanvalid 1@ -@@end -starting execution ... -build model options ... -argc=23 -Generation context: - HardFP is enabled enabling set to true - Faithful rounding constraint detected - Will not generate valid and channel signals - The new component name is acl_s10_itof - Frequency 250MHz - Deployment FPGA Stratix10 -Estimated resources LUTs 362, DSPs 0, RAMBits 0, RAMBlocks 0 -The pipeline depth of the block is 7 cycle(s) -@@start -@name FXPToFP@ -@latency 7@ -@LUT 362@ -@DSP 0@ -@RAMBits 0@ -@RAMBlockUsage 0@ -@enable 1@ -@subnormals 0@ -@error 1.00@ -@rounding NA@ -@method default@ -@inPort 0 fxp 32 0 1@ -@outPort 0 fpieee 8 23@ -@nochanvalid 1@ -@@end -starting execution ... -build model options ... -argc=23 -Generation context: - HardFP is enabled enabling set to true - Faithful rounding constraint detected - Will not generate valid and channel signals - The new component name is acl_s10_utof - Frequency 300MHz - Deployment FPGA Stratix10 -Estimated resources LUTs 310, DSPs 0, RAMBits 0, RAMBlocks 0 -The pipeline depth of the block is 7 cycle(s) -@@start -@name FXPToFP@ -@latency 7@ -@LUT 310@ -@DSP 0@ -@RAMBits 0@ -@RAMBlockUsage 0@ -@enable 1@ -@subnormals 0@ -@error 1.00@ -@rounding NA@ -@method default@ -@inPort 0 fxp 32 0 0@ -@outPort 0 fpieee 8 23@ -@nochanvalid 1@ -@@end diff --git a/hw/rtl/fp_cores/altera/acl_gen.sh b/hw/rtl/fp_cores/altera/acl_gen.sh deleted file mode 100755 index 463b1f31..00000000 --- a/hw/rtl/fp_cores/altera/acl_gen.sh +++ /dev/null @@ -1,25 +0,0 @@ -#!/bin/bash - -CMD_POLY_EVAL_PATH=$QUARTUS_HOME/dspba/backend/linux64 - -OPTIONS="-target Stratix10 -lang verilog -enableHardFP 1 -printMachineReadable -faithfulRounding -noChanValid -enable -speedgrade 2" - -export LD_LIBRARY_PATH=$CMD_POLY_EVAL_PATH:$LD_LIBRARY_PATH - -CMD="$CMD_POLY_EVAL_PATH/cmdPolyEval $OPTIONS" - -EXP_BITS=8 -MAN_BITS=23 -FBITS="f$(($EXP_BITS + $MAN_BITS + 1))" - -echo Generating IP cores for $FBITS -{ - $CMD -name acl_s10_fdiv -frequency 250 FPDiv $EXP_BITS $MAN_BITS 0 - $CMD -name acl_s10_fsqrt -frequency 250 FPSqrt $EXP_BITS $MAN_BITS - $CMD -name acl_s10_ftoi -frequency 250 FPToFXP $EXP_BITS $MAN_BITS 32 0 1 - $CMD -name acl_s10_ftou -frequency 250 FPToFXP $EXP_BITS $MAN_BITS 32 0 0 - $CMD -name acl_s10_itof -frequency 250 FXPToFP 32 0 1 $EXP_BITS $MAN_BITS - $CMD -name acl_s10_utof -frequency 300 FXPToFP 32 0 0 $EXP_BITS $MAN_BITS -} > acl_gen.log 2>&1 - -#cp $QUARTUS_HOME/dspba/backend/Libraries/sv/base/dspba_library_ver.sv . \ No newline at end of file diff --git a/hw/rtl/fp_cores/altera/arria10/acl_fadd.sv b/hw/rtl/fp_cores/altera/arria10/acl_fadd.sv new file mode 100644 index 00000000..7fff5a66 --- /dev/null +++ b/hw/rtl/fp_cores/altera/arria10/acl_fadd.sv @@ -0,0 +1,67 @@ +// ------------------------------------------------------------------------- +// High Level Design Compiler for Intel(R) FPGAs Version 17.1 (Release Build #273) +// Quartus Prime development tool and MATLAB/Simulink Interface +// +// Legal Notice: Copyright 2017 Intel Corporation. All rights reserved. +// Your use of Intel Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly +// subject to the terms and conditions of the Intel FPGA Software License +// Agreement, Intel MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for +// the sole purpose of programming logic devices manufactured by Intel +// and sold by Intel or its authorized distributors. Please refer to the +// applicable agreement for further details. +// --------------------------------------------------------------------------- + +// SystemVerilog created from acl_fadd +// SystemVerilog created on Sun Dec 27 09:47:20 2020 + + +(* altera_attribute = "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410; -name MESSAGE_DISABLE 113007; -name MESSAGE_DISABLE 10958" *) +module acl_fadd ( + input wire [31:0] a, + input wire [31:0] b, + input wire [0:0] en, + output wire [31:0] q, + input wire clk, + input wire areset + ); + + wire [31:0] fpAddTest_impl_ax0; + wire [31:0] fpAddTest_impl_ay0; + wire [31:0] fpAddTest_impl_q0; + wire fpAddTest_impl_reset0; + wire fpAddTest_impl_fpAddTest_impl_ena0; + + + // fpAddTest_impl(FPCOLUMN,5)@0 + // out q0@3 + assign fpAddTest_impl_ax0 = b; + assign fpAddTest_impl_ay0 = a; + assign fpAddTest_impl_reset0 = areset; + assign fpAddTest_impl_fpAddTest_impl_ena0 = en[0]; + twentynm_fp_mac #( + .operation_mode("sp_add"), + .ax_clock("0"), + .ay_clock("0"), + .adder_input_clock("0"), + .output_clock("0") + ) fpAddTest_impl_DSP0 ( + .aclr({ fpAddTest_impl_reset0, fpAddTest_impl_reset0 }), + .clk({1'b0,1'b0,clk}), + .ena({ 1'b0, 1'b0, fpAddTest_impl_fpAddTest_impl_ena0 }), + .ax(fpAddTest_impl_ax0), + .ay(fpAddTest_impl_ay0), + .resulta(fpAddTest_impl_q0), + .accumulate(), + .az(), + .chainin(), + .chainout() + ); + + // xOut(GPOUT,4)@3 + assign q = fpAddTest_impl_q0; + +endmodule diff --git a/hw/rtl/fp_cores/altera/arria10/acl_fdiv.sv b/hw/rtl/fp_cores/altera/arria10/acl_fdiv.sv new file mode 100644 index 00000000..a01558bd --- /dev/null +++ b/hw/rtl/fp_cores/altera/arria10/acl_fdiv.sv @@ -0,0 +1,2632 @@ +// ------------------------------------------------------------------------- +// High Level Design Compiler for Intel(R) FPGAs Version 17.1 (Release Build #273) +// Quartus Prime development tool and MATLAB/Simulink Interface +// +// Legal Notice: Copyright 2017 Intel Corporation. All rights reserved. +// Your use of Intel Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly +// subject to the terms and conditions of the Intel FPGA Software License +// Agreement, Intel MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for +// the sole purpose of programming logic devices manufactured by Intel +// and sold by Intel or its authorized distributors. Please refer to the +// applicable agreement for further details. +// --------------------------------------------------------------------------- + +// SystemVerilog created from acl_fdiv +// SystemVerilog created on Sun Dec 27 09:47:21 2020 + + +(* altera_attribute = "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410; -name MESSAGE_DISABLE 113007; -name MESSAGE_DISABLE 10958" *) +module acl_fdiv ( + input wire [31:0] a, + input wire [31:0] b, + input wire [0:0] en, + output wire [31:0] q, + input wire clk, + input wire areset + ); + + wire [0:0] GND_q; + wire [0:0] VCC_q; + wire [7:0] cstBiasM1_uid6_fpDivTest_q; + wire [7:0] cstBias_uid7_fpDivTest_q; + wire [7:0] expX_uid9_fpDivTest_b; + wire [22:0] fracX_uid10_fpDivTest_b; + wire [0:0] signX_uid11_fpDivTest_b; + wire [7:0] expY_uid12_fpDivTest_b; + wire [22:0] fracY_uid13_fpDivTest_b; + wire [0:0] signY_uid14_fpDivTest_b; + wire [22:0] paddingY_uid15_fpDivTest_q; + wire [23:0] updatedY_uid16_fpDivTest_q; + wire [23:0] fracYZero_uid15_fpDivTest_a; + wire [0:0] fracYZero_uid15_fpDivTest_qi; + reg [0:0] fracYZero_uid15_fpDivTest_q; + wire [7:0] cstAllOWE_uid18_fpDivTest_q; + wire [7:0] cstAllZWE_uid20_fpDivTest_q; + wire [0:0] excZ_x_uid23_fpDivTest_q; + wire [0:0] expXIsMax_uid24_fpDivTest_q; + wire [0:0] fracXIsZero_uid25_fpDivTest_q; + wire [0:0] fracXIsNotZero_uid26_fpDivTest_q; + wire [0:0] excI_x_uid27_fpDivTest_q; + wire [0:0] excN_x_uid28_fpDivTest_q; + wire [0:0] invExpXIsMax_uid29_fpDivTest_q; + wire [0:0] InvExpXIsZero_uid30_fpDivTest_q; + wire [0:0] excR_x_uid31_fpDivTest_q; + wire [0:0] excZ_y_uid37_fpDivTest_q; + wire [0:0] expXIsMax_uid38_fpDivTest_q; + wire [0:0] fracXIsZero_uid39_fpDivTest_q; + wire [0:0] fracXIsNotZero_uid40_fpDivTest_q; + wire [0:0] excI_y_uid41_fpDivTest_q; + wire [0:0] excN_y_uid42_fpDivTest_q; + wire [0:0] invExpXIsMax_uid43_fpDivTest_q; + wire [0:0] InvExpXIsZero_uid44_fpDivTest_q; + wire [0:0] excR_y_uid45_fpDivTest_q; + wire [0:0] signR_uid46_fpDivTest_qi; + reg [0:0] signR_uid46_fpDivTest_q; + wire [8:0] expXmY_uid47_fpDivTest_a; + wire [8:0] expXmY_uid47_fpDivTest_b; + logic [8:0] expXmY_uid47_fpDivTest_o; + wire [8:0] expXmY_uid47_fpDivTest_q; + wire [10:0] expR_uid48_fpDivTest_a; + wire [10:0] expR_uid48_fpDivTest_b; + logic [10:0] expR_uid48_fpDivTest_o; + wire [9:0] expR_uid48_fpDivTest_q; + wire [8:0] yAddr_uid51_fpDivTest_b; + wire [13:0] yPE_uid52_fpDivTest_b; + wire [31:0] invY_uid54_fpDivTest_in; + wire [26:0] invY_uid54_fpDivTest_b; + wire [32:0] invYO_uid55_fpDivTest_in; + wire [0:0] invYO_uid55_fpDivTest_b; + wire [23:0] lOAdded_uid57_fpDivTest_q; + wire [3:0] z4_uid60_fpDivTest_q; + wire [27:0] oFracXZ4_uid61_fpDivTest_q; + wire [0:0] divValPreNormYPow2Exc_uid63_fpDivTest_s; + reg [27:0] divValPreNormYPow2Exc_uid63_fpDivTest_q; + wire [0:0] norm_uid64_fpDivTest_b; + wire [26:0] divValPreNormHigh_uid65_fpDivTest_in; + wire [24:0] divValPreNormHigh_uid65_fpDivTest_b; + wire [25:0] divValPreNormLow_uid66_fpDivTest_in; + wire [24:0] divValPreNormLow_uid66_fpDivTest_b; + wire [0:0] normFracRnd_uid67_fpDivTest_s; + reg [24:0] normFracRnd_uid67_fpDivTest_q; + wire [34:0] expFracRnd_uid68_fpDivTest_q; + wire [23:0] zeroPaddingInAddition_uid74_fpDivTest_q; + wire [25:0] expFracPostRnd_uid75_fpDivTest_q; + wire [36:0] expFracPostRnd_uid76_fpDivTest_a; + wire [36:0] expFracPostRnd_uid76_fpDivTest_b; + logic [36:0] expFracPostRnd_uid76_fpDivTest_o; + wire [35:0] expFracPostRnd_uid76_fpDivTest_q; + wire [23:0] fracXExt_uid77_fpDivTest_q; + wire [24:0] fracPostRndF_uid79_fpDivTest_in; + wire [23:0] fracPostRndF_uid79_fpDivTest_b; + wire [0:0] fracPostRndF_uid80_fpDivTest_s; + reg [23:0] fracPostRndF_uid80_fpDivTest_q; + wire [32:0] expPostRndFR_uid81_fpDivTest_in; + wire [7:0] expPostRndFR_uid81_fpDivTest_b; + wire [0:0] expPostRndF_uid82_fpDivTest_s; + reg [7:0] expPostRndF_uid82_fpDivTest_q; + wire [24:0] lOAdded_uid84_fpDivTest_q; + wire [23:0] lOAdded_uid87_fpDivTest_q; + wire [0:0] qDivProdNorm_uid90_fpDivTest_b; + wire [47:0] qDivProdFracHigh_uid91_fpDivTest_in; + wire [23:0] qDivProdFracHigh_uid91_fpDivTest_b; + wire [46:0] qDivProdFracLow_uid92_fpDivTest_in; + wire [23:0] qDivProdFracLow_uid92_fpDivTest_b; + wire [0:0] qDivProdFrac_uid93_fpDivTest_s; + reg [23:0] qDivProdFrac_uid93_fpDivTest_q; + wire [8:0] qDivProdExp_opA_uid94_fpDivTest_a; + wire [8:0] qDivProdExp_opA_uid94_fpDivTest_b; + logic [8:0] qDivProdExp_opA_uid94_fpDivTest_o; + wire [8:0] qDivProdExp_opA_uid94_fpDivTest_q; + wire [8:0] qDivProdExp_opBs_uid95_fpDivTest_a; + wire [8:0] qDivProdExp_opBs_uid95_fpDivTest_b; + logic [8:0] qDivProdExp_opBs_uid95_fpDivTest_o; + wire [8:0] qDivProdExp_opBs_uid95_fpDivTest_q; + wire [11:0] qDivProdExp_uid96_fpDivTest_a; + wire [11:0] qDivProdExp_uid96_fpDivTest_b; + logic [11:0] qDivProdExp_uid96_fpDivTest_o; + wire [10:0] qDivProdExp_uid96_fpDivTest_q; + wire [22:0] qDivProdFracWF_uid97_fpDivTest_b; + wire [7:0] qDivProdLTX_opA_uid98_fpDivTest_in; + wire [7:0] qDivProdLTX_opA_uid98_fpDivTest_b; + wire [30:0] qDivProdLTX_opA_uid99_fpDivTest_q; + wire [30:0] qDivProdLTX_opB_uid100_fpDivTest_q; + wire [32:0] qDividerProdLTX_uid101_fpDivTest_a; + wire [32:0] qDividerProdLTX_uid101_fpDivTest_b; + logic [32:0] qDividerProdLTX_uid101_fpDivTest_o; + wire [0:0] qDividerProdLTX_uid101_fpDivTest_c; + wire [0:0] betweenFPwF_uid102_fpDivTest_in; + wire [0:0] betweenFPwF_uid102_fpDivTest_b; + wire [0:0] extraUlp_uid103_fpDivTest_q; + wire [22:0] fracPostRndFT_uid104_fpDivTest_b; + wire [23:0] fracRPreExcExt_uid105_fpDivTest_a; + wire [23:0] fracRPreExcExt_uid105_fpDivTest_b; + logic [23:0] fracRPreExcExt_uid105_fpDivTest_o; + wire [23:0] fracRPreExcExt_uid105_fpDivTest_q; + wire [22:0] fracPostRndFPostUlp_uid106_fpDivTest_in; + wire [22:0] fracPostRndFPostUlp_uid106_fpDivTest_b; + wire [0:0] fracRPreExc_uid107_fpDivTest_s; + reg [22:0] fracRPreExc_uid107_fpDivTest_q; + wire [0:0] ovfIncRnd_uid109_fpDivTest_b; + wire [8:0] expFracPostRndInc_uid110_fpDivTest_a; + wire [8:0] expFracPostRndInc_uid110_fpDivTest_b; + logic [8:0] expFracPostRndInc_uid110_fpDivTest_o; + wire [8:0] expFracPostRndInc_uid110_fpDivTest_q; + wire [7:0] expFracPostRndR_uid111_fpDivTest_in; + wire [7:0] expFracPostRndR_uid111_fpDivTest_b; + wire [0:0] expRPreExc_uid112_fpDivTest_s; + reg [7:0] expRPreExc_uid112_fpDivTest_q; + wire [10:0] expRExt_uid114_fpDivTest_b; + wire [12:0] expUdf_uid115_fpDivTest_a; + wire [12:0] expUdf_uid115_fpDivTest_b; + logic [12:0] expUdf_uid115_fpDivTest_o; + wire [0:0] expUdf_uid115_fpDivTest_n; + wire [12:0] expOvf_uid118_fpDivTest_a; + wire [12:0] expOvf_uid118_fpDivTest_b; + logic [12:0] expOvf_uid118_fpDivTest_o; + wire [0:0] expOvf_uid118_fpDivTest_n; + wire [0:0] zeroOverReg_uid119_fpDivTest_qi; + reg [0:0] zeroOverReg_uid119_fpDivTest_q; + wire [0:0] regOverRegWithUf_uid120_fpDivTest_qi; + reg [0:0] regOverRegWithUf_uid120_fpDivTest_q; + wire [0:0] xRegOrZero_uid121_fpDivTest_q; + wire [0:0] regOrZeroOverInf_uid122_fpDivTest_qi; + reg [0:0] regOrZeroOverInf_uid122_fpDivTest_q; + wire [0:0] excRZero_uid123_fpDivTest_q; + wire [0:0] excXRYZ_uid124_fpDivTest_q; + wire [0:0] excXRYROvf_uid125_fpDivTest_q; + wire [0:0] excXIYZ_uid126_fpDivTest_q; + wire [0:0] excXIYR_uid127_fpDivTest_q; + wire [0:0] excRInf_uid128_fpDivTest_qi; + reg [0:0] excRInf_uid128_fpDivTest_q; + wire [0:0] excXZYZ_uid129_fpDivTest_q; + wire [0:0] excXIYI_uid130_fpDivTest_q; + wire [0:0] excRNaN_uid131_fpDivTest_qi; + reg [0:0] excRNaN_uid131_fpDivTest_q; + wire [2:0] concExc_uid132_fpDivTest_q; + reg [1:0] excREnc_uid133_fpDivTest_q; + wire [22:0] oneFracRPostExc2_uid134_fpDivTest_q; + wire [1:0] fracRPostExc_uid137_fpDivTest_s; + reg [22:0] fracRPostExc_uid137_fpDivTest_q; + wire [1:0] expRPostExc_uid141_fpDivTest_s; + reg [7:0] expRPostExc_uid141_fpDivTest_q; + wire [0:0] invExcRNaN_uid142_fpDivTest_q; + wire [0:0] sRPostExc_uid143_fpDivTest_qi; + reg [0:0] sRPostExc_uid143_fpDivTest_q; + wire [31:0] divR_uid144_fpDivTest_q; + wire [12:0] yT1_uid158_invPolyEval_b; + wire [0:0] lowRangeB_uid160_invPolyEval_in; + wire [0:0] lowRangeB_uid160_invPolyEval_b; + wire [12:0] highBBits_uid161_invPolyEval_b; + wire [22:0] s1sumAHighB_uid162_invPolyEval_a; + wire [22:0] s1sumAHighB_uid162_invPolyEval_b; + logic [22:0] s1sumAHighB_uid162_invPolyEval_o; + wire [22:0] s1sumAHighB_uid162_invPolyEval_q; + wire [23:0] s1_uid163_invPolyEval_q; + wire [1:0] lowRangeB_uid166_invPolyEval_in; + wire [1:0] lowRangeB_uid166_invPolyEval_b; + wire [22:0] highBBits_uid167_invPolyEval_b; + wire [32:0] s2sumAHighB_uid168_invPolyEval_a; + wire [32:0] s2sumAHighB_uid168_invPolyEval_b; + logic [32:0] s2sumAHighB_uid168_invPolyEval_o; + wire [32:0] s2sumAHighB_uid168_invPolyEval_q; + wire [34:0] s2_uid169_invPolyEval_q; + wire [27:0] osig_uid172_divValPreNorm_uid59_fpDivTest_b; + wire [13:0] osig_uid175_pT1_uid159_invPolyEval_b; + wire [24:0] osig_uid178_pT2_uid165_invPolyEval_b; + wire memoryC0_uid146_invTables_lutmem_reset0; + wire [31:0] memoryC0_uid146_invTables_lutmem_ia; + wire [8:0] memoryC0_uid146_invTables_lutmem_aa; + wire [8:0] memoryC0_uid146_invTables_lutmem_ab; + wire [31:0] memoryC0_uid146_invTables_lutmem_ir; + wire [31:0] memoryC0_uid146_invTables_lutmem_r; + wire memoryC1_uid149_invTables_lutmem_reset0; + wire [21:0] memoryC1_uid149_invTables_lutmem_ia; + wire [8:0] memoryC1_uid149_invTables_lutmem_aa; + wire [8:0] memoryC1_uid149_invTables_lutmem_ab; + wire [21:0] memoryC1_uid149_invTables_lutmem_ir; + wire [21:0] memoryC1_uid149_invTables_lutmem_r; + wire memoryC2_uid152_invTables_lutmem_reset0; + wire [12:0] memoryC2_uid152_invTables_lutmem_ia; + wire [8:0] memoryC2_uid152_invTables_lutmem_aa; + wire [8:0] memoryC2_uid152_invTables_lutmem_ab; + wire [12:0] memoryC2_uid152_invTables_lutmem_ir; + wire [12:0] memoryC2_uid152_invTables_lutmem_r; + wire qDivProd_uid89_fpDivTest_cma_reset; + (* preserve, altera_attribute = "-name allow_synch_ctrl_usage off" *) reg [24:0] qDivProd_uid89_fpDivTest_cma_a0 [0:0]; + (* preserve, altera_attribute = "-name allow_synch_ctrl_usage off" *) reg [24:0] qDivProd_uid89_fpDivTest_cma_a1 [0:0]; + (* preserve, altera_attribute = "-name allow_synch_ctrl_usage off" *) reg [23:0] qDivProd_uid89_fpDivTest_cma_c0 [0:0]; + (* preserve, altera_attribute = "-name allow_synch_ctrl_usage off" *) reg [23:0] qDivProd_uid89_fpDivTest_cma_c1 [0:0]; + wire [48:0] qDivProd_uid89_fpDivTest_cma_p [0:0]; + wire [48:0] qDivProd_uid89_fpDivTest_cma_u [0:0]; + wire [48:0] qDivProd_uid89_fpDivTest_cma_w [0:0]; + wire [48:0] qDivProd_uid89_fpDivTest_cma_x [0:0]; + wire [48:0] qDivProd_uid89_fpDivTest_cma_y [0:0]; + reg [48:0] qDivProd_uid89_fpDivTest_cma_s [0:0]; + wire [48:0] qDivProd_uid89_fpDivTest_cma_qq; + wire [48:0] qDivProd_uid89_fpDivTest_cma_q; + wire qDivProd_uid89_fpDivTest_cma_ena0; + wire qDivProd_uid89_fpDivTest_cma_ena1; + wire qDivProd_uid89_fpDivTest_cma_ena2; + wire prodXY_uid171_divValPreNorm_uid59_fpDivTest_cma_reset; + (* preserve, altera_attribute = "-name allow_synch_ctrl_usage off" *) reg [26:0] prodXY_uid171_divValPreNorm_uid59_fpDivTest_cma_a0 [0:0]; + (* preserve, altera_attribute = "-name allow_synch_ctrl_usage off" *) reg [26:0] prodXY_uid171_divValPreNorm_uid59_fpDivTest_cma_a1 [0:0]; + (* preserve, altera_attribute = "-name allow_synch_ctrl_usage off" *) reg [23:0] prodXY_uid171_divValPreNorm_uid59_fpDivTest_cma_c0 [0:0]; + (* preserve, altera_attribute = "-name allow_synch_ctrl_usage off" *) reg [23:0] prodXY_uid171_divValPreNorm_uid59_fpDivTest_cma_c1 [0:0]; + wire [50:0] prodXY_uid171_divValPreNorm_uid59_fpDivTest_cma_p [0:0]; + wire [50:0] prodXY_uid171_divValPreNorm_uid59_fpDivTest_cma_u [0:0]; + wire [50:0] prodXY_uid171_divValPreNorm_uid59_fpDivTest_cma_w [0:0]; + wire [50:0] prodXY_uid171_divValPreNorm_uid59_fpDivTest_cma_x [0:0]; + wire [50:0] prodXY_uid171_divValPreNorm_uid59_fpDivTest_cma_y [0:0]; + reg [50:0] prodXY_uid171_divValPreNorm_uid59_fpDivTest_cma_s [0:0]; + wire [50:0] prodXY_uid171_divValPreNorm_uid59_fpDivTest_cma_qq; + wire [50:0] prodXY_uid171_divValPreNorm_uid59_fpDivTest_cma_q; + wire prodXY_uid171_divValPreNorm_uid59_fpDivTest_cma_ena0; + wire prodXY_uid171_divValPreNorm_uid59_fpDivTest_cma_ena1; + wire prodXY_uid171_divValPreNorm_uid59_fpDivTest_cma_ena2; + wire prodXY_uid174_pT1_uid159_invPolyEval_cma_reset; + (* preserve, altera_attribute = "-name allow_synch_ctrl_usage off" *) reg [12:0] prodXY_uid174_pT1_uid159_invPolyEval_cma_a0 [0:0]; + (* preserve, altera_attribute = "-name allow_synch_ctrl_usage off" *) reg [12:0] prodXY_uid174_pT1_uid159_invPolyEval_cma_a1 [0:0]; + (* preserve, altera_attribute = "-name allow_synch_ctrl_usage off" *) reg signed [12:0] prodXY_uid174_pT1_uid159_invPolyEval_cma_c0 [0:0]; + (* preserve, altera_attribute = "-name allow_synch_ctrl_usage off" *) reg signed [12:0] prodXY_uid174_pT1_uid159_invPolyEval_cma_c1 [0:0]; + wire signed [13:0] prodXY_uid174_pT1_uid159_invPolyEval_cma_l [0:0]; + wire signed [26:0] prodXY_uid174_pT1_uid159_invPolyEval_cma_p [0:0]; + wire signed [26:0] prodXY_uid174_pT1_uid159_invPolyEval_cma_u [0:0]; + wire signed [26:0] prodXY_uid174_pT1_uid159_invPolyEval_cma_w [0:0]; + wire signed [26:0] prodXY_uid174_pT1_uid159_invPolyEval_cma_x [0:0]; + wire signed [26:0] prodXY_uid174_pT1_uid159_invPolyEval_cma_y [0:0]; + reg signed [26:0] prodXY_uid174_pT1_uid159_invPolyEval_cma_s [0:0]; + wire [25:0] prodXY_uid174_pT1_uid159_invPolyEval_cma_qq; + wire [25:0] prodXY_uid174_pT1_uid159_invPolyEval_cma_q; + wire prodXY_uid174_pT1_uid159_invPolyEval_cma_ena0; + wire prodXY_uid174_pT1_uid159_invPolyEval_cma_ena1; + wire prodXY_uid174_pT1_uid159_invPolyEval_cma_ena2; + wire prodXY_uid177_pT2_uid165_invPolyEval_cma_reset; + (* preserve, altera_attribute = "-name allow_synch_ctrl_usage off" *) reg [13:0] prodXY_uid177_pT2_uid165_invPolyEval_cma_a0 [0:0]; + (* preserve, altera_attribute = "-name allow_synch_ctrl_usage off" *) reg [13:0] prodXY_uid177_pT2_uid165_invPolyEval_cma_a1 [0:0]; + (* preserve, altera_attribute = "-name allow_synch_ctrl_usage off" *) reg signed [23:0] prodXY_uid177_pT2_uid165_invPolyEval_cma_c0 [0:0]; + (* preserve, altera_attribute = "-name allow_synch_ctrl_usage off" *) reg signed [23:0] prodXY_uid177_pT2_uid165_invPolyEval_cma_c1 [0:0]; + wire signed [14:0] prodXY_uid177_pT2_uid165_invPolyEval_cma_l [0:0]; + wire signed [38:0] prodXY_uid177_pT2_uid165_invPolyEval_cma_p [0:0]; + wire signed [38:0] prodXY_uid177_pT2_uid165_invPolyEval_cma_u [0:0]; + wire signed [38:0] prodXY_uid177_pT2_uid165_invPolyEval_cma_w [0:0]; + wire signed [38:0] prodXY_uid177_pT2_uid165_invPolyEval_cma_x [0:0]; + wire signed [38:0] prodXY_uid177_pT2_uid165_invPolyEval_cma_y [0:0]; + reg signed [38:0] prodXY_uid177_pT2_uid165_invPolyEval_cma_s [0:0]; + wire [37:0] prodXY_uid177_pT2_uid165_invPolyEval_cma_qq; + wire [37:0] prodXY_uid177_pT2_uid165_invPolyEval_cma_q; + wire prodXY_uid177_pT2_uid165_invPolyEval_cma_ena0; + wire prodXY_uid177_pT2_uid165_invPolyEval_cma_ena1; + wire prodXY_uid177_pT2_uid165_invPolyEval_cma_ena2; + reg [0:0] redist0_lowRangeB_uid160_invPolyEval_b_1_q; + reg [0:0] redist1_sRPostExc_uid143_fpDivTest_q_5_q; + reg [1:0] redist2_excREnc_uid133_fpDivTest_q_5_q; + reg [0:0] redist3_ovfIncRnd_uid109_fpDivTest_b_1_q; + reg [0:0] redist4_extraUlp_uid103_fpDivTest_q_1_q; + reg [22:0] redist5_qDivProdFracWF_uid97_fpDivTest_b_1_q; + reg [8:0] redist6_qDivProdExp_opA_uid94_fpDivTest_q_4_q; + reg [23:0] redist9_lOAdded_uid57_fpDivTest_q_3_q; + reg [0:0] redist10_invYO_uid55_fpDivTest_b_5_q; + reg [26:0] redist11_invY_uid54_fpDivTest_b_1_q; + reg [13:0] redist12_yPE_uid52_fpDivTest_b_2_q; + reg [8:0] redist14_yAddr_uid51_fpDivTest_b_3_q; + reg [8:0] redist15_yAddr_uid51_fpDivTest_b_7_q; + reg [0:0] redist16_signR_uid46_fpDivTest_q_15_q; + reg [22:0] redist18_fracY_uid13_fpDivTest_b_14_q; + reg [7:0] redist20_expY_uid12_fpDivTest_b_14_q; + reg [22:0] redist22_fracX_uid10_fpDivTest_b_14_q; + reg [22:0] redist23_fracX_uid10_fpDivTest_b_18_q; + reg [7:0] redist25_expX_uid9_fpDivTest_b_14_q; + reg [7:0] redist26_expX_uid9_fpDivTest_b_18_q; + reg [7:0] redist7_expPostRndFR_uid81_fpDivTest_b_6_outputreg_q; + wire redist7_expPostRndFR_uid81_fpDivTest_b_6_mem_reset0; + wire [7:0] redist7_expPostRndFR_uid81_fpDivTest_b_6_mem_ia; + wire [1:0] redist7_expPostRndFR_uid81_fpDivTest_b_6_mem_aa; + wire [1:0] redist7_expPostRndFR_uid81_fpDivTest_b_6_mem_ab; + wire [7:0] redist7_expPostRndFR_uid81_fpDivTest_b_6_mem_iq; + wire [7:0] redist7_expPostRndFR_uid81_fpDivTest_b_6_mem_q; + wire [1:0] redist7_expPostRndFR_uid81_fpDivTest_b_6_rdcnt_q; + (* preserve *) reg [1:0] redist7_expPostRndFR_uid81_fpDivTest_b_6_rdcnt_i; + wire [0:0] redist7_expPostRndFR_uid81_fpDivTest_b_6_rdmux_s; + reg [1:0] redist7_expPostRndFR_uid81_fpDivTest_b_6_rdmux_q; + reg [1:0] redist7_expPostRndFR_uid81_fpDivTest_b_6_wraddr_q; + wire [2:0] redist7_expPostRndFR_uid81_fpDivTest_b_6_mem_last_q; + wire [2:0] redist7_expPostRndFR_uid81_fpDivTest_b_6_cmp_b; + wire [0:0] redist7_expPostRndFR_uid81_fpDivTest_b_6_cmp_q; + reg [0:0] redist7_expPostRndFR_uid81_fpDivTest_b_6_cmpReg_q; + wire [0:0] redist7_expPostRndFR_uid81_fpDivTest_b_6_notEnable_q; + wire [0:0] redist7_expPostRndFR_uid81_fpDivTest_b_6_nor_q; + (* preserve_syn_only *) reg [0:0] redist7_expPostRndFR_uid81_fpDivTest_b_6_sticky_ena_q; + wire [0:0] redist7_expPostRndFR_uid81_fpDivTest_b_6_enaAnd_q; + reg [23:0] redist8_fracPostRndF_uid80_fpDivTest_q_5_outputreg_q; + wire redist8_fracPostRndF_uid80_fpDivTest_q_5_mem_reset0; + wire [23:0] redist8_fracPostRndF_uid80_fpDivTest_q_5_mem_ia; + wire [1:0] redist8_fracPostRndF_uid80_fpDivTest_q_5_mem_aa; + wire [1:0] redist8_fracPostRndF_uid80_fpDivTest_q_5_mem_ab; + wire [23:0] redist8_fracPostRndF_uid80_fpDivTest_q_5_mem_iq; + wire [23:0] redist8_fracPostRndF_uid80_fpDivTest_q_5_mem_q; + wire [1:0] redist8_fracPostRndF_uid80_fpDivTest_q_5_rdcnt_q; + (* preserve *) reg [1:0] redist8_fracPostRndF_uid80_fpDivTest_q_5_rdcnt_i; + (* preserve *) reg redist8_fracPostRndF_uid80_fpDivTest_q_5_rdcnt_eq; + wire [0:0] redist8_fracPostRndF_uid80_fpDivTest_q_5_rdmux_s; + reg [1:0] redist8_fracPostRndF_uid80_fpDivTest_q_5_rdmux_q; + reg [1:0] redist8_fracPostRndF_uid80_fpDivTest_q_5_wraddr_q; + wire [1:0] redist8_fracPostRndF_uid80_fpDivTest_q_5_mem_last_q; + wire [0:0] redist8_fracPostRndF_uid80_fpDivTest_q_5_cmp_q; + reg [0:0] redist8_fracPostRndF_uid80_fpDivTest_q_5_cmpReg_q; + wire [0:0] redist8_fracPostRndF_uid80_fpDivTest_q_5_notEnable_q; + wire [0:0] redist8_fracPostRndF_uid80_fpDivTest_q_5_nor_q; + (* preserve_syn_only *) reg [0:0] redist8_fracPostRndF_uid80_fpDivTest_q_5_sticky_ena_q; + wire [0:0] redist8_fracPostRndF_uid80_fpDivTest_q_5_enaAnd_q; + wire redist13_yPE_uid52_fpDivTest_b_6_mem_reset0; + wire [13:0] redist13_yPE_uid52_fpDivTest_b_6_mem_ia; + wire [1:0] redist13_yPE_uid52_fpDivTest_b_6_mem_aa; + wire [1:0] redist13_yPE_uid52_fpDivTest_b_6_mem_ab; + wire [13:0] redist13_yPE_uid52_fpDivTest_b_6_mem_iq; + wire [13:0] redist13_yPE_uid52_fpDivTest_b_6_mem_q; + wire [1:0] redist13_yPE_uid52_fpDivTest_b_6_rdcnt_q; + (* preserve *) reg [1:0] redist13_yPE_uid52_fpDivTest_b_6_rdcnt_i; + (* preserve *) reg redist13_yPE_uid52_fpDivTest_b_6_rdcnt_eq; + wire [0:0] redist13_yPE_uid52_fpDivTest_b_6_rdmux_s; + reg [1:0] redist13_yPE_uid52_fpDivTest_b_6_rdmux_q; + reg [1:0] redist13_yPE_uid52_fpDivTest_b_6_wraddr_q; + wire [1:0] redist13_yPE_uid52_fpDivTest_b_6_mem_last_q; + wire [0:0] redist13_yPE_uid52_fpDivTest_b_6_cmp_q; + reg [0:0] redist13_yPE_uid52_fpDivTest_b_6_cmpReg_q; + wire [0:0] redist13_yPE_uid52_fpDivTest_b_6_notEnable_q; + wire [0:0] redist13_yPE_uid52_fpDivTest_b_6_nor_q; + (* preserve_syn_only *) reg [0:0] redist13_yPE_uid52_fpDivTest_b_6_sticky_ena_q; + wire [0:0] redist13_yPE_uid52_fpDivTest_b_6_enaAnd_q; + reg [22:0] redist17_fracY_uid13_fpDivTest_b_12_outputreg_q; + wire redist17_fracY_uid13_fpDivTest_b_12_mem_reset0; + wire [22:0] redist17_fracY_uid13_fpDivTest_b_12_mem_ia; + wire [3:0] redist17_fracY_uid13_fpDivTest_b_12_mem_aa; + wire [3:0] redist17_fracY_uid13_fpDivTest_b_12_mem_ab; + wire [22:0] redist17_fracY_uid13_fpDivTest_b_12_mem_iq; + wire [22:0] redist17_fracY_uid13_fpDivTest_b_12_mem_q; + wire [3:0] redist17_fracY_uid13_fpDivTest_b_12_rdcnt_q; + (* preserve *) reg [3:0] redist17_fracY_uid13_fpDivTest_b_12_rdcnt_i; + (* preserve *) reg redist17_fracY_uid13_fpDivTest_b_12_rdcnt_eq; + wire [0:0] redist17_fracY_uid13_fpDivTest_b_12_rdmux_s; + reg [3:0] redist17_fracY_uid13_fpDivTest_b_12_rdmux_q; + reg [3:0] redist17_fracY_uid13_fpDivTest_b_12_wraddr_q; + wire [4:0] redist17_fracY_uid13_fpDivTest_b_12_mem_last_q; + wire [4:0] redist17_fracY_uid13_fpDivTest_b_12_cmp_b; + wire [0:0] redist17_fracY_uid13_fpDivTest_b_12_cmp_q; + reg [0:0] redist17_fracY_uid13_fpDivTest_b_12_cmpReg_q; + wire [0:0] redist17_fracY_uid13_fpDivTest_b_12_notEnable_q; + wire [0:0] redist17_fracY_uid13_fpDivTest_b_12_nor_q; + (* preserve_syn_only *) reg [0:0] redist17_fracY_uid13_fpDivTest_b_12_sticky_ena_q; + wire [0:0] redist17_fracY_uid13_fpDivTest_b_12_enaAnd_q; + reg [7:0] redist19_expY_uid12_fpDivTest_b_12_outputreg_q; + wire redist19_expY_uid12_fpDivTest_b_12_mem_reset0; + wire [7:0] redist19_expY_uid12_fpDivTest_b_12_mem_ia; + wire [3:0] redist19_expY_uid12_fpDivTest_b_12_mem_aa; + wire [3:0] redist19_expY_uid12_fpDivTest_b_12_mem_ab; + wire [7:0] redist19_expY_uid12_fpDivTest_b_12_mem_iq; + wire [7:0] redist19_expY_uid12_fpDivTest_b_12_mem_q; + wire [3:0] redist19_expY_uid12_fpDivTest_b_12_rdcnt_q; + (* preserve *) reg [3:0] redist19_expY_uid12_fpDivTest_b_12_rdcnt_i; + (* preserve *) reg redist19_expY_uid12_fpDivTest_b_12_rdcnt_eq; + wire [0:0] redist19_expY_uid12_fpDivTest_b_12_rdmux_s; + reg [3:0] redist19_expY_uid12_fpDivTest_b_12_rdmux_q; + reg [3:0] redist19_expY_uid12_fpDivTest_b_12_wraddr_q; + wire [4:0] redist19_expY_uid12_fpDivTest_b_12_mem_last_q; + wire [4:0] redist19_expY_uid12_fpDivTest_b_12_cmp_b; + wire [0:0] redist19_expY_uid12_fpDivTest_b_12_cmp_q; + reg [0:0] redist19_expY_uid12_fpDivTest_b_12_cmpReg_q; + wire [0:0] redist19_expY_uid12_fpDivTest_b_12_notEnable_q; + wire [0:0] redist19_expY_uid12_fpDivTest_b_12_nor_q; + (* preserve_syn_only *) reg [0:0] redist19_expY_uid12_fpDivTest_b_12_sticky_ena_q; + wire [0:0] redist19_expY_uid12_fpDivTest_b_12_enaAnd_q; + reg [22:0] redist21_fracX_uid10_fpDivTest_b_10_outputreg_q; + wire redist21_fracX_uid10_fpDivTest_b_10_mem_reset0; + wire [22:0] redist21_fracX_uid10_fpDivTest_b_10_mem_ia; + wire [2:0] redist21_fracX_uid10_fpDivTest_b_10_mem_aa; + wire [2:0] redist21_fracX_uid10_fpDivTest_b_10_mem_ab; + wire [22:0] redist21_fracX_uid10_fpDivTest_b_10_mem_iq; + wire [22:0] redist21_fracX_uid10_fpDivTest_b_10_mem_q; + wire [2:0] redist21_fracX_uid10_fpDivTest_b_10_rdcnt_q; + (* preserve *) reg [2:0] redist21_fracX_uid10_fpDivTest_b_10_rdcnt_i; + wire [0:0] redist21_fracX_uid10_fpDivTest_b_10_rdmux_s; + reg [2:0] redist21_fracX_uid10_fpDivTest_b_10_rdmux_q; + reg [2:0] redist21_fracX_uid10_fpDivTest_b_10_wraddr_q; + wire [3:0] redist21_fracX_uid10_fpDivTest_b_10_mem_last_q; + wire [3:0] redist21_fracX_uid10_fpDivTest_b_10_cmp_b; + wire [0:0] redist21_fracX_uid10_fpDivTest_b_10_cmp_q; + reg [0:0] redist21_fracX_uid10_fpDivTest_b_10_cmpReg_q; + wire [0:0] redist21_fracX_uid10_fpDivTest_b_10_notEnable_q; + wire [0:0] redist21_fracX_uid10_fpDivTest_b_10_nor_q; + (* preserve_syn_only *) reg [0:0] redist21_fracX_uid10_fpDivTest_b_10_sticky_ena_q; + wire [0:0] redist21_fracX_uid10_fpDivTest_b_10_enaAnd_q; + reg [22:0] redist22_fracX_uid10_fpDivTest_b_14_inputreg_q; + reg [22:0] redist23_fracX_uid10_fpDivTest_b_18_inputreg_q; + reg [7:0] redist24_expX_uid9_fpDivTest_b_12_outputreg_q; + wire redist24_expX_uid9_fpDivTest_b_12_mem_reset0; + wire [7:0] redist24_expX_uid9_fpDivTest_b_12_mem_ia; + wire [3:0] redist24_expX_uid9_fpDivTest_b_12_mem_aa; + wire [3:0] redist24_expX_uid9_fpDivTest_b_12_mem_ab; + wire [7:0] redist24_expX_uid9_fpDivTest_b_12_mem_iq; + wire [7:0] redist24_expX_uid9_fpDivTest_b_12_mem_q; + wire [3:0] redist24_expX_uid9_fpDivTest_b_12_rdcnt_q; + (* preserve *) reg [3:0] redist24_expX_uid9_fpDivTest_b_12_rdcnt_i; + (* preserve *) reg redist24_expX_uid9_fpDivTest_b_12_rdcnt_eq; + wire [0:0] redist24_expX_uid9_fpDivTest_b_12_rdmux_s; + reg [3:0] redist24_expX_uid9_fpDivTest_b_12_rdmux_q; + reg [3:0] redist24_expX_uid9_fpDivTest_b_12_wraddr_q; + wire [4:0] redist24_expX_uid9_fpDivTest_b_12_mem_last_q; + wire [4:0] redist24_expX_uid9_fpDivTest_b_12_cmp_b; + wire [0:0] redist24_expX_uid9_fpDivTest_b_12_cmp_q; + reg [0:0] redist24_expX_uid9_fpDivTest_b_12_cmpReg_q; + wire [0:0] redist24_expX_uid9_fpDivTest_b_12_notEnable_q; + wire [0:0] redist24_expX_uid9_fpDivTest_b_12_nor_q; + (* preserve_syn_only *) reg [0:0] redist24_expX_uid9_fpDivTest_b_12_sticky_ena_q; + wire [0:0] redist24_expX_uid9_fpDivTest_b_12_enaAnd_q; + + + // redist17_fracY_uid13_fpDivTest_b_12_notEnable(LOGICAL,256) + assign redist17_fracY_uid13_fpDivTest_b_12_notEnable_q = ~ (en); + + // redist17_fracY_uid13_fpDivTest_b_12_nor(LOGICAL,257) + assign redist17_fracY_uid13_fpDivTest_b_12_nor_q = ~ (redist17_fracY_uid13_fpDivTest_b_12_notEnable_q | redist17_fracY_uid13_fpDivTest_b_12_sticky_ena_q); + + // redist17_fracY_uid13_fpDivTest_b_12_mem_last(CONSTANT,253) + assign redist17_fracY_uid13_fpDivTest_b_12_mem_last_q = 5'b01000; + + // redist17_fracY_uid13_fpDivTest_b_12_cmp(LOGICAL,254) + assign redist17_fracY_uid13_fpDivTest_b_12_cmp_b = {1'b0, redist17_fracY_uid13_fpDivTest_b_12_rdmux_q}; + assign redist17_fracY_uid13_fpDivTest_b_12_cmp_q = redist17_fracY_uid13_fpDivTest_b_12_mem_last_q == redist17_fracY_uid13_fpDivTest_b_12_cmp_b ? 1'b1 : 1'b0; + + // redist17_fracY_uid13_fpDivTest_b_12_cmpReg(REG,255) + always @ (posedge clk or posedge areset) + begin + if (areset) + begin + redist17_fracY_uid13_fpDivTest_b_12_cmpReg_q <= 1'b0; + end + else if (en == 1'b1) + begin + redist17_fracY_uid13_fpDivTest_b_12_cmpReg_q <= redist17_fracY_uid13_fpDivTest_b_12_cmp_q; + end + end + + // redist17_fracY_uid13_fpDivTest_b_12_sticky_ena(REG,258) + always @ (posedge clk or posedge areset) + begin + if (areset) + begin + redist17_fracY_uid13_fpDivTest_b_12_sticky_ena_q <= 1'b0; + end + else if (redist17_fracY_uid13_fpDivTest_b_12_nor_q == 1'b1) + begin + redist17_fracY_uid13_fpDivTest_b_12_sticky_ena_q <= redist17_fracY_uid13_fpDivTest_b_12_cmpReg_q; + end + end + + // redist17_fracY_uid13_fpDivTest_b_12_enaAnd(LOGICAL,259) + assign redist17_fracY_uid13_fpDivTest_b_12_enaAnd_q = redist17_fracY_uid13_fpDivTest_b_12_sticky_ena_q & en; + + // redist17_fracY_uid13_fpDivTest_b_12_rdcnt(COUNTER,250) + // low=0, high=9, step=1, init=0 + always @ (posedge clk or posedge areset) + begin + if (areset) + begin + redist17_fracY_uid13_fpDivTest_b_12_rdcnt_i <= 4'd0; + redist17_fracY_uid13_fpDivTest_b_12_rdcnt_eq <= 1'b0; + end + else if (en == 1'b1) + begin + if (redist17_fracY_uid13_fpDivTest_b_12_rdcnt_i == 4'd8) + begin + redist17_fracY_uid13_fpDivTest_b_12_rdcnt_eq <= 1'b1; + end + else + begin + redist17_fracY_uid13_fpDivTest_b_12_rdcnt_eq <= 1'b0; + end + if (redist17_fracY_uid13_fpDivTest_b_12_rdcnt_eq == 1'b1) + begin + redist17_fracY_uid13_fpDivTest_b_12_rdcnt_i <= $unsigned(redist17_fracY_uid13_fpDivTest_b_12_rdcnt_i) + $unsigned(4'd7); + end + else + begin + redist17_fracY_uid13_fpDivTest_b_12_rdcnt_i <= $unsigned(redist17_fracY_uid13_fpDivTest_b_12_rdcnt_i) + $unsigned(4'd1); + end + end + end + assign redist17_fracY_uid13_fpDivTest_b_12_rdcnt_q = redist17_fracY_uid13_fpDivTest_b_12_rdcnt_i[3:0]; + + // redist17_fracY_uid13_fpDivTest_b_12_rdmux(MUX,251) + assign redist17_fracY_uid13_fpDivTest_b_12_rdmux_s = en; + always @(redist17_fracY_uid13_fpDivTest_b_12_rdmux_s or redist17_fracY_uid13_fpDivTest_b_12_wraddr_q or redist17_fracY_uid13_fpDivTest_b_12_rdcnt_q) + begin + unique case (redist17_fracY_uid13_fpDivTest_b_12_rdmux_s) + 1'b0 : redist17_fracY_uid13_fpDivTest_b_12_rdmux_q = redist17_fracY_uid13_fpDivTest_b_12_wraddr_q; + 1'b1 : redist17_fracY_uid13_fpDivTest_b_12_rdmux_q = redist17_fracY_uid13_fpDivTest_b_12_rdcnt_q; + default : redist17_fracY_uid13_fpDivTest_b_12_rdmux_q = 4'b0; + endcase + end + + // VCC(CONSTANT,1) + assign VCC_q = 1'b1; + + // fracY_uid13_fpDivTest(BITSELECT,12)@0 + assign fracY_uid13_fpDivTest_b = b[22:0]; + + // redist17_fracY_uid13_fpDivTest_b_12_wraddr(REG,252) + always @ (posedge clk or posedge areset) + begin + if (areset) + begin + redist17_fracY_uid13_fpDivTest_b_12_wraddr_q <= 4'b1001; + end + else + begin + redist17_fracY_uid13_fpDivTest_b_12_wraddr_q <= redist17_fracY_uid13_fpDivTest_b_12_rdmux_q; + end + end + + // redist17_fracY_uid13_fpDivTest_b_12_mem(DUALMEM,249) + assign redist17_fracY_uid13_fpDivTest_b_12_mem_ia = fracY_uid13_fpDivTest_b; + assign redist17_fracY_uid13_fpDivTest_b_12_mem_aa = redist17_fracY_uid13_fpDivTest_b_12_wraddr_q; + assign redist17_fracY_uid13_fpDivTest_b_12_mem_ab = redist17_fracY_uid13_fpDivTest_b_12_rdmux_q; + assign redist17_fracY_uid13_fpDivTest_b_12_mem_reset0 = areset; + altera_syncram #( + .ram_block_type("MLAB"), + .operation_mode("DUAL_PORT"), + .width_a(23), + .widthad_a(4), + .numwords_a(10), + .width_b(23), + .widthad_b(4), + .numwords_b(10), + .lpm_type("altera_syncram"), + .width_byteena_a(1), + .address_reg_b("CLOCK0"), + .indata_reg_b("CLOCK0"), + .rdcontrol_reg_b("CLOCK0"), + .byteena_reg_b("CLOCK0"), + .outdata_reg_b("CLOCK1"), + .outdata_aclr_b("CLEAR1"), + .clock_enable_input_a("NORMAL"), + .clock_enable_input_b("NORMAL"), + .clock_enable_output_b("NORMAL"), + .read_during_write_mode_mixed_ports("DONT_CARE"), + .power_up_uninitialized("TRUE"), + .intended_device_family("Arria 10") + ) redist17_fracY_uid13_fpDivTest_b_12_mem_dmem ( + .clocken1(redist17_fracY_uid13_fpDivTest_b_12_enaAnd_q[0]), + .clocken0(VCC_q[0]), + .clock0(clk), + .aclr1(redist17_fracY_uid13_fpDivTest_b_12_mem_reset0), + .clock1(clk), + .address_a(redist17_fracY_uid13_fpDivTest_b_12_mem_aa), + .data_a(redist17_fracY_uid13_fpDivTest_b_12_mem_ia), + .wren_a(en[0]), + .address_b(redist17_fracY_uid13_fpDivTest_b_12_mem_ab), + .q_b(redist17_fracY_uid13_fpDivTest_b_12_mem_iq), + .wren_b(), + .rden_a(), + .rden_b(), + .data_b(), + .clocken2(), + .clocken3(), + .aclr0(), + .addressstall_a(), + .addressstall_b(), + .byteena_a(), + .byteena_b(), + .eccencbypass(), + .eccencparity(), + .sclr(), + .address2_a(), + .address2_b(), + .q_a(), + .eccstatus() + ); + assign redist17_fracY_uid13_fpDivTest_b_12_mem_q = redist17_fracY_uid13_fpDivTest_b_12_mem_iq[22:0]; + + // redist17_fracY_uid13_fpDivTest_b_12_outputreg(DELAY,248) + dspba_delay_ver #( .width(23), .depth(1), .reset_kind("ASYNC") ) + redist17_fracY_uid13_fpDivTest_b_12_outputreg ( .xin(redist17_fracY_uid13_fpDivTest_b_12_mem_q), .xout(redist17_fracY_uid13_fpDivTest_b_12_outputreg_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // redist18_fracY_uid13_fpDivTest_b_14(DELAY,204) + dspba_delay_ver #( .width(23), .depth(2), .reset_kind("ASYNC") ) + redist18_fracY_uid13_fpDivTest_b_14 ( .xin(redist17_fracY_uid13_fpDivTest_b_12_outputreg_q), .xout(redist18_fracY_uid13_fpDivTest_b_14_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // paddingY_uid15_fpDivTest(CONSTANT,14) + assign paddingY_uid15_fpDivTest_q = 23'b00000000000000000000000; + + // fracXIsZero_uid39_fpDivTest(LOGICAL,38)@14 + assign fracXIsZero_uid39_fpDivTest_q = paddingY_uid15_fpDivTest_q == redist18_fracY_uid13_fpDivTest_b_14_q ? 1'b1 : 1'b0; + + // cstAllOWE_uid18_fpDivTest(CONSTANT,17) + assign cstAllOWE_uid18_fpDivTest_q = 8'b11111111; + + // redist19_expY_uid12_fpDivTest_b_12_notEnable(LOGICAL,268) + assign redist19_expY_uid12_fpDivTest_b_12_notEnable_q = ~ (en); + + // redist19_expY_uid12_fpDivTest_b_12_nor(LOGICAL,269) + assign redist19_expY_uid12_fpDivTest_b_12_nor_q = ~ (redist19_expY_uid12_fpDivTest_b_12_notEnable_q | redist19_expY_uid12_fpDivTest_b_12_sticky_ena_q); + + // redist19_expY_uid12_fpDivTest_b_12_mem_last(CONSTANT,265) + assign redist19_expY_uid12_fpDivTest_b_12_mem_last_q = 5'b01000; + + // redist19_expY_uid12_fpDivTest_b_12_cmp(LOGICAL,266) + assign redist19_expY_uid12_fpDivTest_b_12_cmp_b = {1'b0, redist19_expY_uid12_fpDivTest_b_12_rdmux_q}; + assign redist19_expY_uid12_fpDivTest_b_12_cmp_q = redist19_expY_uid12_fpDivTest_b_12_mem_last_q == redist19_expY_uid12_fpDivTest_b_12_cmp_b ? 1'b1 : 1'b0; + + // redist19_expY_uid12_fpDivTest_b_12_cmpReg(REG,267) + always @ (posedge clk or posedge areset) + begin + if (areset) + begin + redist19_expY_uid12_fpDivTest_b_12_cmpReg_q <= 1'b0; + end + else if (en == 1'b1) + begin + redist19_expY_uid12_fpDivTest_b_12_cmpReg_q <= redist19_expY_uid12_fpDivTest_b_12_cmp_q; + end + end + + // redist19_expY_uid12_fpDivTest_b_12_sticky_ena(REG,270) + always @ (posedge clk or posedge areset) + begin + if (areset) + begin + redist19_expY_uid12_fpDivTest_b_12_sticky_ena_q <= 1'b0; + end + else if (redist19_expY_uid12_fpDivTest_b_12_nor_q == 1'b1) + begin + redist19_expY_uid12_fpDivTest_b_12_sticky_ena_q <= redist19_expY_uid12_fpDivTest_b_12_cmpReg_q; + end + end + + // redist19_expY_uid12_fpDivTest_b_12_enaAnd(LOGICAL,271) + assign redist19_expY_uid12_fpDivTest_b_12_enaAnd_q = redist19_expY_uid12_fpDivTest_b_12_sticky_ena_q & en; + + // redist19_expY_uid12_fpDivTest_b_12_rdcnt(COUNTER,262) + // low=0, high=9, step=1, init=0 + always @ (posedge clk or posedge areset) + begin + if (areset) + begin + redist19_expY_uid12_fpDivTest_b_12_rdcnt_i <= 4'd0; + redist19_expY_uid12_fpDivTest_b_12_rdcnt_eq <= 1'b0; + end + else if (en == 1'b1) + begin + if (redist19_expY_uid12_fpDivTest_b_12_rdcnt_i == 4'd8) + begin + redist19_expY_uid12_fpDivTest_b_12_rdcnt_eq <= 1'b1; + end + else + begin + redist19_expY_uid12_fpDivTest_b_12_rdcnt_eq <= 1'b0; + end + if (redist19_expY_uid12_fpDivTest_b_12_rdcnt_eq == 1'b1) + begin + redist19_expY_uid12_fpDivTest_b_12_rdcnt_i <= $unsigned(redist19_expY_uid12_fpDivTest_b_12_rdcnt_i) + $unsigned(4'd7); + end + else + begin + redist19_expY_uid12_fpDivTest_b_12_rdcnt_i <= $unsigned(redist19_expY_uid12_fpDivTest_b_12_rdcnt_i) + $unsigned(4'd1); + end + end + end + assign redist19_expY_uid12_fpDivTest_b_12_rdcnt_q = redist19_expY_uid12_fpDivTest_b_12_rdcnt_i[3:0]; + + // redist19_expY_uid12_fpDivTest_b_12_rdmux(MUX,263) + assign redist19_expY_uid12_fpDivTest_b_12_rdmux_s = en; + always @(redist19_expY_uid12_fpDivTest_b_12_rdmux_s or redist19_expY_uid12_fpDivTest_b_12_wraddr_q or redist19_expY_uid12_fpDivTest_b_12_rdcnt_q) + begin + unique case (redist19_expY_uid12_fpDivTest_b_12_rdmux_s) + 1'b0 : redist19_expY_uid12_fpDivTest_b_12_rdmux_q = redist19_expY_uid12_fpDivTest_b_12_wraddr_q; + 1'b1 : redist19_expY_uid12_fpDivTest_b_12_rdmux_q = redist19_expY_uid12_fpDivTest_b_12_rdcnt_q; + default : redist19_expY_uid12_fpDivTest_b_12_rdmux_q = 4'b0; + endcase + end + + // expY_uid12_fpDivTest(BITSELECT,11)@0 + assign expY_uid12_fpDivTest_b = b[30:23]; + + // redist19_expY_uid12_fpDivTest_b_12_wraddr(REG,264) + always @ (posedge clk or posedge areset) + begin + if (areset) + begin + redist19_expY_uid12_fpDivTest_b_12_wraddr_q <= 4'b1001; + end + else + begin + redist19_expY_uid12_fpDivTest_b_12_wraddr_q <= redist19_expY_uid12_fpDivTest_b_12_rdmux_q; + end + end + + // redist19_expY_uid12_fpDivTest_b_12_mem(DUALMEM,261) + assign redist19_expY_uid12_fpDivTest_b_12_mem_ia = expY_uid12_fpDivTest_b; + assign redist19_expY_uid12_fpDivTest_b_12_mem_aa = redist19_expY_uid12_fpDivTest_b_12_wraddr_q; + assign redist19_expY_uid12_fpDivTest_b_12_mem_ab = redist19_expY_uid12_fpDivTest_b_12_rdmux_q; + assign redist19_expY_uid12_fpDivTest_b_12_mem_reset0 = areset; + altera_syncram #( + .ram_block_type("MLAB"), + .operation_mode("DUAL_PORT"), + .width_a(8), + .widthad_a(4), + .numwords_a(10), + .width_b(8), + .widthad_b(4), + .numwords_b(10), + .lpm_type("altera_syncram"), + .width_byteena_a(1), + .address_reg_b("CLOCK0"), + .indata_reg_b("CLOCK0"), + .rdcontrol_reg_b("CLOCK0"), + .byteena_reg_b("CLOCK0"), + .outdata_reg_b("CLOCK1"), + .outdata_aclr_b("CLEAR1"), + .clock_enable_input_a("NORMAL"), + .clock_enable_input_b("NORMAL"), + .clock_enable_output_b("NORMAL"), + .read_during_write_mode_mixed_ports("DONT_CARE"), + .power_up_uninitialized("TRUE"), + .intended_device_family("Arria 10") + ) redist19_expY_uid12_fpDivTest_b_12_mem_dmem ( + .clocken1(redist19_expY_uid12_fpDivTest_b_12_enaAnd_q[0]), + .clocken0(VCC_q[0]), + .clock0(clk), + .aclr1(redist19_expY_uid12_fpDivTest_b_12_mem_reset0), + .clock1(clk), + .address_a(redist19_expY_uid12_fpDivTest_b_12_mem_aa), + .data_a(redist19_expY_uid12_fpDivTest_b_12_mem_ia), + .wren_a(en[0]), + .address_b(redist19_expY_uid12_fpDivTest_b_12_mem_ab), + .q_b(redist19_expY_uid12_fpDivTest_b_12_mem_iq), + .wren_b(), + .rden_a(), + .rden_b(), + .data_b(), + .clocken2(), + .clocken3(), + .aclr0(), + .addressstall_a(), + .addressstall_b(), + .byteena_a(), + .byteena_b(), + .eccencbypass(), + .eccencparity(), + .sclr(), + .address2_a(), + .address2_b(), + .q_a(), + .eccstatus() + ); + assign redist19_expY_uid12_fpDivTest_b_12_mem_q = redist19_expY_uid12_fpDivTest_b_12_mem_iq[7:0]; + + // redist19_expY_uid12_fpDivTest_b_12_outputreg(DELAY,260) + dspba_delay_ver #( .width(8), .depth(1), .reset_kind("ASYNC") ) + redist19_expY_uid12_fpDivTest_b_12_outputreg ( .xin(redist19_expY_uid12_fpDivTest_b_12_mem_q), .xout(redist19_expY_uid12_fpDivTest_b_12_outputreg_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // redist20_expY_uid12_fpDivTest_b_14(DELAY,206) + dspba_delay_ver #( .width(8), .depth(2), .reset_kind("ASYNC") ) + redist20_expY_uid12_fpDivTest_b_14 ( .xin(redist19_expY_uid12_fpDivTest_b_12_outputreg_q), .xout(redist20_expY_uid12_fpDivTest_b_14_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // expXIsMax_uid38_fpDivTest(LOGICAL,37)@14 + assign expXIsMax_uid38_fpDivTest_q = redist20_expY_uid12_fpDivTest_b_14_q == cstAllOWE_uid18_fpDivTest_q ? 1'b1 : 1'b0; + + // excI_y_uid41_fpDivTest(LOGICAL,40)@14 + assign excI_y_uid41_fpDivTest_q = expXIsMax_uid38_fpDivTest_q & fracXIsZero_uid39_fpDivTest_q; + + // redist21_fracX_uid10_fpDivTest_b_10_notEnable(LOGICAL,280) + assign redist21_fracX_uid10_fpDivTest_b_10_notEnable_q = ~ (en); + + // redist21_fracX_uid10_fpDivTest_b_10_nor(LOGICAL,281) + assign redist21_fracX_uid10_fpDivTest_b_10_nor_q = ~ (redist21_fracX_uid10_fpDivTest_b_10_notEnable_q | redist21_fracX_uid10_fpDivTest_b_10_sticky_ena_q); + + // redist21_fracX_uid10_fpDivTest_b_10_mem_last(CONSTANT,277) + assign redist21_fracX_uid10_fpDivTest_b_10_mem_last_q = 4'b0110; + + // redist21_fracX_uid10_fpDivTest_b_10_cmp(LOGICAL,278) + assign redist21_fracX_uid10_fpDivTest_b_10_cmp_b = {1'b0, redist21_fracX_uid10_fpDivTest_b_10_rdmux_q}; + assign redist21_fracX_uid10_fpDivTest_b_10_cmp_q = redist21_fracX_uid10_fpDivTest_b_10_mem_last_q == redist21_fracX_uid10_fpDivTest_b_10_cmp_b ? 1'b1 : 1'b0; + + // redist21_fracX_uid10_fpDivTest_b_10_cmpReg(REG,279) + always @ (posedge clk or posedge areset) + begin + if (areset) + begin + redist21_fracX_uid10_fpDivTest_b_10_cmpReg_q <= 1'b0; + end + else if (en == 1'b1) + begin + redist21_fracX_uid10_fpDivTest_b_10_cmpReg_q <= redist21_fracX_uid10_fpDivTest_b_10_cmp_q; + end + end + + // redist21_fracX_uid10_fpDivTest_b_10_sticky_ena(REG,282) + always @ (posedge clk or posedge areset) + begin + if (areset) + begin + redist21_fracX_uid10_fpDivTest_b_10_sticky_ena_q <= 1'b0; + end + else if (redist21_fracX_uid10_fpDivTest_b_10_nor_q == 1'b1) + begin + redist21_fracX_uid10_fpDivTest_b_10_sticky_ena_q <= redist21_fracX_uid10_fpDivTest_b_10_cmpReg_q; + end + end + + // redist21_fracX_uid10_fpDivTest_b_10_enaAnd(LOGICAL,283) + assign redist21_fracX_uid10_fpDivTest_b_10_enaAnd_q = redist21_fracX_uid10_fpDivTest_b_10_sticky_ena_q & en; + + // redist21_fracX_uid10_fpDivTest_b_10_rdcnt(COUNTER,274) + // low=0, high=7, step=1, init=0 + always @ (posedge clk or posedge areset) + begin + if (areset) + begin + redist21_fracX_uid10_fpDivTest_b_10_rdcnt_i <= 3'd0; + end + else if (en == 1'b1) + begin + redist21_fracX_uid10_fpDivTest_b_10_rdcnt_i <= $unsigned(redist21_fracX_uid10_fpDivTest_b_10_rdcnt_i) + $unsigned(3'd1); + end + end + assign redist21_fracX_uid10_fpDivTest_b_10_rdcnt_q = redist21_fracX_uid10_fpDivTest_b_10_rdcnt_i[2:0]; + + // redist21_fracX_uid10_fpDivTest_b_10_rdmux(MUX,275) + assign redist21_fracX_uid10_fpDivTest_b_10_rdmux_s = en; + always @(redist21_fracX_uid10_fpDivTest_b_10_rdmux_s or redist21_fracX_uid10_fpDivTest_b_10_wraddr_q or redist21_fracX_uid10_fpDivTest_b_10_rdcnt_q) + begin + unique case (redist21_fracX_uid10_fpDivTest_b_10_rdmux_s) + 1'b0 : redist21_fracX_uid10_fpDivTest_b_10_rdmux_q = redist21_fracX_uid10_fpDivTest_b_10_wraddr_q; + 1'b1 : redist21_fracX_uid10_fpDivTest_b_10_rdmux_q = redist21_fracX_uid10_fpDivTest_b_10_rdcnt_q; + default : redist21_fracX_uid10_fpDivTest_b_10_rdmux_q = 3'b0; + endcase + end + + // fracX_uid10_fpDivTest(BITSELECT,9)@0 + assign fracX_uid10_fpDivTest_b = a[22:0]; + + // redist21_fracX_uid10_fpDivTest_b_10_wraddr(REG,276) + always @ (posedge clk or posedge areset) + begin + if (areset) + begin + redist21_fracX_uid10_fpDivTest_b_10_wraddr_q <= 3'b111; + end + else + begin + redist21_fracX_uid10_fpDivTest_b_10_wraddr_q <= redist21_fracX_uid10_fpDivTest_b_10_rdmux_q; + end + end + + // redist21_fracX_uid10_fpDivTest_b_10_mem(DUALMEM,273) + assign redist21_fracX_uid10_fpDivTest_b_10_mem_ia = fracX_uid10_fpDivTest_b; + assign redist21_fracX_uid10_fpDivTest_b_10_mem_aa = redist21_fracX_uid10_fpDivTest_b_10_wraddr_q; + assign redist21_fracX_uid10_fpDivTest_b_10_mem_ab = redist21_fracX_uid10_fpDivTest_b_10_rdmux_q; + assign redist21_fracX_uid10_fpDivTest_b_10_mem_reset0 = areset; + altera_syncram #( + .ram_block_type("MLAB"), + .operation_mode("DUAL_PORT"), + .width_a(23), + .widthad_a(3), + .numwords_a(8), + .width_b(23), + .widthad_b(3), + .numwords_b(8), + .lpm_type("altera_syncram"), + .width_byteena_a(1), + .address_reg_b("CLOCK0"), + .indata_reg_b("CLOCK0"), + .rdcontrol_reg_b("CLOCK0"), + .byteena_reg_b("CLOCK0"), + .outdata_reg_b("CLOCK1"), + .outdata_aclr_b("CLEAR1"), + .clock_enable_input_a("NORMAL"), + .clock_enable_input_b("NORMAL"), + .clock_enable_output_b("NORMAL"), + .read_during_write_mode_mixed_ports("DONT_CARE"), + .power_up_uninitialized("TRUE"), + .intended_device_family("Arria 10") + ) redist21_fracX_uid10_fpDivTest_b_10_mem_dmem ( + .clocken1(redist21_fracX_uid10_fpDivTest_b_10_enaAnd_q[0]), + .clocken0(VCC_q[0]), + .clock0(clk), + .aclr1(redist21_fracX_uid10_fpDivTest_b_10_mem_reset0), + .clock1(clk), + .address_a(redist21_fracX_uid10_fpDivTest_b_10_mem_aa), + .data_a(redist21_fracX_uid10_fpDivTest_b_10_mem_ia), + .wren_a(en[0]), + .address_b(redist21_fracX_uid10_fpDivTest_b_10_mem_ab), + .q_b(redist21_fracX_uid10_fpDivTest_b_10_mem_iq), + .wren_b(), + .rden_a(), + .rden_b(), + .data_b(), + .clocken2(), + .clocken3(), + .aclr0(), + .addressstall_a(), + .addressstall_b(), + .byteena_a(), + .byteena_b(), + .eccencbypass(), + .eccencparity(), + .sclr(), + .address2_a(), + .address2_b(), + .q_a(), + .eccstatus() + ); + assign redist21_fracX_uid10_fpDivTest_b_10_mem_q = redist21_fracX_uid10_fpDivTest_b_10_mem_iq[22:0]; + + // redist21_fracX_uid10_fpDivTest_b_10_outputreg(DELAY,272) + dspba_delay_ver #( .width(23), .depth(1), .reset_kind("ASYNC") ) + redist21_fracX_uid10_fpDivTest_b_10_outputreg ( .xin(redist21_fracX_uid10_fpDivTest_b_10_mem_q), .xout(redist21_fracX_uid10_fpDivTest_b_10_outputreg_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // redist22_fracX_uid10_fpDivTest_b_14_inputreg(DELAY,284) + dspba_delay_ver #( .width(23), .depth(1), .reset_kind("ASYNC") ) + redist22_fracX_uid10_fpDivTest_b_14_inputreg ( .xin(redist21_fracX_uid10_fpDivTest_b_10_outputreg_q), .xout(redist22_fracX_uid10_fpDivTest_b_14_inputreg_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // redist22_fracX_uid10_fpDivTest_b_14(DELAY,208) + dspba_delay_ver #( .width(23), .depth(3), .reset_kind("ASYNC") ) + redist22_fracX_uid10_fpDivTest_b_14 ( .xin(redist22_fracX_uid10_fpDivTest_b_14_inputreg_q), .xout(redist22_fracX_uid10_fpDivTest_b_14_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // fracXIsZero_uid25_fpDivTest(LOGICAL,24)@14 + assign fracXIsZero_uid25_fpDivTest_q = paddingY_uid15_fpDivTest_q == redist22_fracX_uid10_fpDivTest_b_14_q ? 1'b1 : 1'b0; + + // redist24_expX_uid9_fpDivTest_b_12_notEnable(LOGICAL,294) + assign redist24_expX_uid9_fpDivTest_b_12_notEnable_q = ~ (en); + + // redist24_expX_uid9_fpDivTest_b_12_nor(LOGICAL,295) + assign redist24_expX_uid9_fpDivTest_b_12_nor_q = ~ (redist24_expX_uid9_fpDivTest_b_12_notEnable_q | redist24_expX_uid9_fpDivTest_b_12_sticky_ena_q); + + // redist24_expX_uid9_fpDivTest_b_12_mem_last(CONSTANT,291) + assign redist24_expX_uid9_fpDivTest_b_12_mem_last_q = 5'b01000; + + // redist24_expX_uid9_fpDivTest_b_12_cmp(LOGICAL,292) + assign redist24_expX_uid9_fpDivTest_b_12_cmp_b = {1'b0, redist24_expX_uid9_fpDivTest_b_12_rdmux_q}; + assign redist24_expX_uid9_fpDivTest_b_12_cmp_q = redist24_expX_uid9_fpDivTest_b_12_mem_last_q == redist24_expX_uid9_fpDivTest_b_12_cmp_b ? 1'b1 : 1'b0; + + // redist24_expX_uid9_fpDivTest_b_12_cmpReg(REG,293) + always @ (posedge clk or posedge areset) + begin + if (areset) + begin + redist24_expX_uid9_fpDivTest_b_12_cmpReg_q <= 1'b0; + end + else if (en == 1'b1) + begin + redist24_expX_uid9_fpDivTest_b_12_cmpReg_q <= redist24_expX_uid9_fpDivTest_b_12_cmp_q; + end + end + + // redist24_expX_uid9_fpDivTest_b_12_sticky_ena(REG,296) + always @ (posedge clk or posedge areset) + begin + if (areset) + begin + redist24_expX_uid9_fpDivTest_b_12_sticky_ena_q <= 1'b0; + end + else if (redist24_expX_uid9_fpDivTest_b_12_nor_q == 1'b1) + begin + redist24_expX_uid9_fpDivTest_b_12_sticky_ena_q <= redist24_expX_uid9_fpDivTest_b_12_cmpReg_q; + end + end + + // redist24_expX_uid9_fpDivTest_b_12_enaAnd(LOGICAL,297) + assign redist24_expX_uid9_fpDivTest_b_12_enaAnd_q = redist24_expX_uid9_fpDivTest_b_12_sticky_ena_q & en; + + // redist24_expX_uid9_fpDivTest_b_12_rdcnt(COUNTER,288) + // low=0, high=9, step=1, init=0 + always @ (posedge clk or posedge areset) + begin + if (areset) + begin + redist24_expX_uid9_fpDivTest_b_12_rdcnt_i <= 4'd0; + redist24_expX_uid9_fpDivTest_b_12_rdcnt_eq <= 1'b0; + end + else if (en == 1'b1) + begin + if (redist24_expX_uid9_fpDivTest_b_12_rdcnt_i == 4'd8) + begin + redist24_expX_uid9_fpDivTest_b_12_rdcnt_eq <= 1'b1; + end + else + begin + redist24_expX_uid9_fpDivTest_b_12_rdcnt_eq <= 1'b0; + end + if (redist24_expX_uid9_fpDivTest_b_12_rdcnt_eq == 1'b1) + begin + redist24_expX_uid9_fpDivTest_b_12_rdcnt_i <= $unsigned(redist24_expX_uid9_fpDivTest_b_12_rdcnt_i) + $unsigned(4'd7); + end + else + begin + redist24_expX_uid9_fpDivTest_b_12_rdcnt_i <= $unsigned(redist24_expX_uid9_fpDivTest_b_12_rdcnt_i) + $unsigned(4'd1); + end + end + end + assign redist24_expX_uid9_fpDivTest_b_12_rdcnt_q = redist24_expX_uid9_fpDivTest_b_12_rdcnt_i[3:0]; + + // redist24_expX_uid9_fpDivTest_b_12_rdmux(MUX,289) + assign redist24_expX_uid9_fpDivTest_b_12_rdmux_s = en; + always @(redist24_expX_uid9_fpDivTest_b_12_rdmux_s or redist24_expX_uid9_fpDivTest_b_12_wraddr_q or redist24_expX_uid9_fpDivTest_b_12_rdcnt_q) + begin + unique case (redist24_expX_uid9_fpDivTest_b_12_rdmux_s) + 1'b0 : redist24_expX_uid9_fpDivTest_b_12_rdmux_q = redist24_expX_uid9_fpDivTest_b_12_wraddr_q; + 1'b1 : redist24_expX_uid9_fpDivTest_b_12_rdmux_q = redist24_expX_uid9_fpDivTest_b_12_rdcnt_q; + default : redist24_expX_uid9_fpDivTest_b_12_rdmux_q = 4'b0; + endcase + end + + // expX_uid9_fpDivTest(BITSELECT,8)@0 + assign expX_uid9_fpDivTest_b = a[30:23]; + + // redist24_expX_uid9_fpDivTest_b_12_wraddr(REG,290) + always @ (posedge clk or posedge areset) + begin + if (areset) + begin + redist24_expX_uid9_fpDivTest_b_12_wraddr_q <= 4'b1001; + end + else + begin + redist24_expX_uid9_fpDivTest_b_12_wraddr_q <= redist24_expX_uid9_fpDivTest_b_12_rdmux_q; + end + end + + // redist24_expX_uid9_fpDivTest_b_12_mem(DUALMEM,287) + assign redist24_expX_uid9_fpDivTest_b_12_mem_ia = expX_uid9_fpDivTest_b; + assign redist24_expX_uid9_fpDivTest_b_12_mem_aa = redist24_expX_uid9_fpDivTest_b_12_wraddr_q; + assign redist24_expX_uid9_fpDivTest_b_12_mem_ab = redist24_expX_uid9_fpDivTest_b_12_rdmux_q; + assign redist24_expX_uid9_fpDivTest_b_12_mem_reset0 = areset; + altera_syncram #( + .ram_block_type("MLAB"), + .operation_mode("DUAL_PORT"), + .width_a(8), + .widthad_a(4), + .numwords_a(10), + .width_b(8), + .widthad_b(4), + .numwords_b(10), + .lpm_type("altera_syncram"), + .width_byteena_a(1), + .address_reg_b("CLOCK0"), + .indata_reg_b("CLOCK0"), + .rdcontrol_reg_b("CLOCK0"), + .byteena_reg_b("CLOCK0"), + .outdata_reg_b("CLOCK1"), + .outdata_aclr_b("CLEAR1"), + .clock_enable_input_a("NORMAL"), + .clock_enable_input_b("NORMAL"), + .clock_enable_output_b("NORMAL"), + .read_during_write_mode_mixed_ports("DONT_CARE"), + .power_up_uninitialized("TRUE"), + .intended_device_family("Arria 10") + ) redist24_expX_uid9_fpDivTest_b_12_mem_dmem ( + .clocken1(redist24_expX_uid9_fpDivTest_b_12_enaAnd_q[0]), + .clocken0(VCC_q[0]), + .clock0(clk), + .aclr1(redist24_expX_uid9_fpDivTest_b_12_mem_reset0), + .clock1(clk), + .address_a(redist24_expX_uid9_fpDivTest_b_12_mem_aa), + .data_a(redist24_expX_uid9_fpDivTest_b_12_mem_ia), + .wren_a(en[0]), + .address_b(redist24_expX_uid9_fpDivTest_b_12_mem_ab), + .q_b(redist24_expX_uid9_fpDivTest_b_12_mem_iq), + .wren_b(), + .rden_a(), + .rden_b(), + .data_b(), + .clocken2(), + .clocken3(), + .aclr0(), + .addressstall_a(), + .addressstall_b(), + .byteena_a(), + .byteena_b(), + .eccencbypass(), + .eccencparity(), + .sclr(), + .address2_a(), + .address2_b(), + .q_a(), + .eccstatus() + ); + assign redist24_expX_uid9_fpDivTest_b_12_mem_q = redist24_expX_uid9_fpDivTest_b_12_mem_iq[7:0]; + + // redist24_expX_uid9_fpDivTest_b_12_outputreg(DELAY,286) + dspba_delay_ver #( .width(8), .depth(1), .reset_kind("ASYNC") ) + redist24_expX_uid9_fpDivTest_b_12_outputreg ( .xin(redist24_expX_uid9_fpDivTest_b_12_mem_q), .xout(redist24_expX_uid9_fpDivTest_b_12_outputreg_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // redist25_expX_uid9_fpDivTest_b_14(DELAY,211) + dspba_delay_ver #( .width(8), .depth(2), .reset_kind("ASYNC") ) + redist25_expX_uid9_fpDivTest_b_14 ( .xin(redist24_expX_uid9_fpDivTest_b_12_outputreg_q), .xout(redist25_expX_uid9_fpDivTest_b_14_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // expXIsMax_uid24_fpDivTest(LOGICAL,23)@14 + assign expXIsMax_uid24_fpDivTest_q = redist25_expX_uid9_fpDivTest_b_14_q == cstAllOWE_uid18_fpDivTest_q ? 1'b1 : 1'b0; + + // excI_x_uid27_fpDivTest(LOGICAL,26)@14 + assign excI_x_uid27_fpDivTest_q = expXIsMax_uid24_fpDivTest_q & fracXIsZero_uid25_fpDivTest_q; + + // excXIYI_uid130_fpDivTest(LOGICAL,129)@14 + assign excXIYI_uid130_fpDivTest_q = excI_x_uid27_fpDivTest_q & excI_y_uid41_fpDivTest_q; + + // fracXIsNotZero_uid40_fpDivTest(LOGICAL,39)@14 + assign fracXIsNotZero_uid40_fpDivTest_q = ~ (fracXIsZero_uid39_fpDivTest_q); + + // excN_y_uid42_fpDivTest(LOGICAL,41)@14 + assign excN_y_uid42_fpDivTest_q = expXIsMax_uid38_fpDivTest_q & fracXIsNotZero_uid40_fpDivTest_q; + + // fracXIsNotZero_uid26_fpDivTest(LOGICAL,25)@14 + assign fracXIsNotZero_uid26_fpDivTest_q = ~ (fracXIsZero_uid25_fpDivTest_q); + + // excN_x_uid28_fpDivTest(LOGICAL,27)@14 + assign excN_x_uid28_fpDivTest_q = expXIsMax_uid24_fpDivTest_q & fracXIsNotZero_uid26_fpDivTest_q; + + // cstAllZWE_uid20_fpDivTest(CONSTANT,19) + assign cstAllZWE_uid20_fpDivTest_q = 8'b00000000; + + // excZ_y_uid37_fpDivTest(LOGICAL,36)@14 + assign excZ_y_uid37_fpDivTest_q = redist20_expY_uid12_fpDivTest_b_14_q == cstAllZWE_uid20_fpDivTest_q ? 1'b1 : 1'b0; + + // excZ_x_uid23_fpDivTest(LOGICAL,22)@14 + assign excZ_x_uid23_fpDivTest_q = redist25_expX_uid9_fpDivTest_b_14_q == cstAllZWE_uid20_fpDivTest_q ? 1'b1 : 1'b0; + + // excXZYZ_uid129_fpDivTest(LOGICAL,128)@14 + assign excXZYZ_uid129_fpDivTest_q = excZ_x_uid23_fpDivTest_q & excZ_y_uid37_fpDivTest_q; + + // excRNaN_uid131_fpDivTest(LOGICAL,130)@14 + 1 + assign excRNaN_uid131_fpDivTest_qi = excXZYZ_uid129_fpDivTest_q | excN_x_uid28_fpDivTest_q | excN_y_uid42_fpDivTest_q | excXIYI_uid130_fpDivTest_q; + dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") ) + excRNaN_uid131_fpDivTest_delay ( .xin(excRNaN_uid131_fpDivTest_qi), .xout(excRNaN_uid131_fpDivTest_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // invExcRNaN_uid142_fpDivTest(LOGICAL,141)@15 + assign invExcRNaN_uid142_fpDivTest_q = ~ (excRNaN_uid131_fpDivTest_q); + + // signY_uid14_fpDivTest(BITSELECT,13)@0 + assign signY_uid14_fpDivTest_b = b[31:31]; + + // signX_uid11_fpDivTest(BITSELECT,10)@0 + assign signX_uid11_fpDivTest_b = a[31:31]; + + // signR_uid46_fpDivTest(LOGICAL,45)@0 + 1 + assign signR_uid46_fpDivTest_qi = signX_uid11_fpDivTest_b ^ signY_uid14_fpDivTest_b; + dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") ) + signR_uid46_fpDivTest_delay ( .xin(signR_uid46_fpDivTest_qi), .xout(signR_uid46_fpDivTest_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // redist16_signR_uid46_fpDivTest_q_15(DELAY,202) + dspba_delay_ver #( .width(1), .depth(14), .reset_kind("ASYNC") ) + redist16_signR_uid46_fpDivTest_q_15 ( .xin(signR_uid46_fpDivTest_q), .xout(redist16_signR_uid46_fpDivTest_q_15_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // sRPostExc_uid143_fpDivTest(LOGICAL,142)@15 + 1 + assign sRPostExc_uid143_fpDivTest_qi = redist16_signR_uid46_fpDivTest_q_15_q & invExcRNaN_uid142_fpDivTest_q; + dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") ) + sRPostExc_uid143_fpDivTest_delay ( .xin(sRPostExc_uid143_fpDivTest_qi), .xout(sRPostExc_uid143_fpDivTest_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // redist1_sRPostExc_uid143_fpDivTest_q_5(DELAY,187) + dspba_delay_ver #( .width(1), .depth(4), .reset_kind("ASYNC") ) + redist1_sRPostExc_uid143_fpDivTest_q_5 ( .xin(sRPostExc_uid143_fpDivTest_q), .xout(redist1_sRPostExc_uid143_fpDivTest_q_5_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // redist8_fracPostRndF_uid80_fpDivTest_q_5_notEnable(LOGICAL,233) + assign redist8_fracPostRndF_uid80_fpDivTest_q_5_notEnable_q = ~ (en); + + // redist8_fracPostRndF_uid80_fpDivTest_q_5_nor(LOGICAL,234) + assign redist8_fracPostRndF_uid80_fpDivTest_q_5_nor_q = ~ (redist8_fracPostRndF_uid80_fpDivTest_q_5_notEnable_q | redist8_fracPostRndF_uid80_fpDivTest_q_5_sticky_ena_q); + + // redist8_fracPostRndF_uid80_fpDivTest_q_5_mem_last(CONSTANT,230) + assign redist8_fracPostRndF_uid80_fpDivTest_q_5_mem_last_q = 2'b01; + + // redist8_fracPostRndF_uid80_fpDivTest_q_5_cmp(LOGICAL,231) + assign redist8_fracPostRndF_uid80_fpDivTest_q_5_cmp_q = redist8_fracPostRndF_uid80_fpDivTest_q_5_mem_last_q == redist8_fracPostRndF_uid80_fpDivTest_q_5_rdmux_q ? 1'b1 : 1'b0; + + // redist8_fracPostRndF_uid80_fpDivTest_q_5_cmpReg(REG,232) + always @ (posedge clk or posedge areset) + begin + if (areset) + begin + redist8_fracPostRndF_uid80_fpDivTest_q_5_cmpReg_q <= 1'b0; + end + else if (en == 1'b1) + begin + redist8_fracPostRndF_uid80_fpDivTest_q_5_cmpReg_q <= redist8_fracPostRndF_uid80_fpDivTest_q_5_cmp_q; + end + end + + // redist8_fracPostRndF_uid80_fpDivTest_q_5_sticky_ena(REG,235) + always @ (posedge clk or posedge areset) + begin + if (areset) + begin + redist8_fracPostRndF_uid80_fpDivTest_q_5_sticky_ena_q <= 1'b0; + end + else if (redist8_fracPostRndF_uid80_fpDivTest_q_5_nor_q == 1'b1) + begin + redist8_fracPostRndF_uid80_fpDivTest_q_5_sticky_ena_q <= redist8_fracPostRndF_uid80_fpDivTest_q_5_cmpReg_q; + end + end + + // redist8_fracPostRndF_uid80_fpDivTest_q_5_enaAnd(LOGICAL,236) + assign redist8_fracPostRndF_uid80_fpDivTest_q_5_enaAnd_q = redist8_fracPostRndF_uid80_fpDivTest_q_5_sticky_ena_q & en; + + // redist8_fracPostRndF_uid80_fpDivTest_q_5_rdcnt(COUNTER,227) + // low=0, high=2, step=1, init=0 + always @ (posedge clk or posedge areset) + begin + if (areset) + begin + redist8_fracPostRndF_uid80_fpDivTest_q_5_rdcnt_i <= 2'd0; + redist8_fracPostRndF_uid80_fpDivTest_q_5_rdcnt_eq <= 1'b0; + end + else if (en == 1'b1) + begin + if (redist8_fracPostRndF_uid80_fpDivTest_q_5_rdcnt_i == 2'd1) + begin + redist8_fracPostRndF_uid80_fpDivTest_q_5_rdcnt_eq <= 1'b1; + end + else + begin + redist8_fracPostRndF_uid80_fpDivTest_q_5_rdcnt_eq <= 1'b0; + end + if (redist8_fracPostRndF_uid80_fpDivTest_q_5_rdcnt_eq == 1'b1) + begin + redist8_fracPostRndF_uid80_fpDivTest_q_5_rdcnt_i <= $unsigned(redist8_fracPostRndF_uid80_fpDivTest_q_5_rdcnt_i) + $unsigned(2'd2); + end + else + begin + redist8_fracPostRndF_uid80_fpDivTest_q_5_rdcnt_i <= $unsigned(redist8_fracPostRndF_uid80_fpDivTest_q_5_rdcnt_i) + $unsigned(2'd1); + end + end + end + assign redist8_fracPostRndF_uid80_fpDivTest_q_5_rdcnt_q = redist8_fracPostRndF_uid80_fpDivTest_q_5_rdcnt_i[1:0]; + + // redist8_fracPostRndF_uid80_fpDivTest_q_5_rdmux(MUX,228) + assign redist8_fracPostRndF_uid80_fpDivTest_q_5_rdmux_s = en; + always @(redist8_fracPostRndF_uid80_fpDivTest_q_5_rdmux_s or redist8_fracPostRndF_uid80_fpDivTest_q_5_wraddr_q or redist8_fracPostRndF_uid80_fpDivTest_q_5_rdcnt_q) + begin + unique case (redist8_fracPostRndF_uid80_fpDivTest_q_5_rdmux_s) + 1'b0 : redist8_fracPostRndF_uid80_fpDivTest_q_5_rdmux_q = redist8_fracPostRndF_uid80_fpDivTest_q_5_wraddr_q; + 1'b1 : redist8_fracPostRndF_uid80_fpDivTest_q_5_rdmux_q = redist8_fracPostRndF_uid80_fpDivTest_q_5_rdcnt_q; + default : redist8_fracPostRndF_uid80_fpDivTest_q_5_rdmux_q = 2'b0; + endcase + end + + // GND(CONSTANT,0) + assign GND_q = 1'b0; + + // fracXExt_uid77_fpDivTest(BITJOIN,76)@14 + assign fracXExt_uid77_fpDivTest_q = {redist22_fracX_uid10_fpDivTest_b_14_q, GND_q}; + + // lOAdded_uid57_fpDivTest(BITJOIN,56)@10 + assign lOAdded_uid57_fpDivTest_q = {VCC_q, redist21_fracX_uid10_fpDivTest_b_10_outputreg_q}; + + // redist9_lOAdded_uid57_fpDivTest_q_3(DELAY,195) + dspba_delay_ver #( .width(24), .depth(3), .reset_kind("ASYNC") ) + redist9_lOAdded_uid57_fpDivTest_q_3 ( .xin(lOAdded_uid57_fpDivTest_q), .xout(redist9_lOAdded_uid57_fpDivTest_q_3_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // z4_uid60_fpDivTest(CONSTANT,59) + assign z4_uid60_fpDivTest_q = 4'b0000; + + // oFracXZ4_uid61_fpDivTest(BITJOIN,60)@13 + assign oFracXZ4_uid61_fpDivTest_q = {redist9_lOAdded_uid57_fpDivTest_q_3_q, z4_uid60_fpDivTest_q}; + + // yAddr_uid51_fpDivTest(BITSELECT,50)@0 + assign yAddr_uid51_fpDivTest_b = fracY_uid13_fpDivTest_b[22:14]; + + // memoryC2_uid152_invTables_lutmem(DUALMEM,181)@0 + 2 + // in j@20000000 + assign memoryC2_uid152_invTables_lutmem_aa = yAddr_uid51_fpDivTest_b; + assign memoryC2_uid152_invTables_lutmem_reset0 = areset; + altera_syncram #( + .ram_block_type("M20K"), + .operation_mode("ROM"), + .width_a(13), + .widthad_a(9), + .numwords_a(512), + .lpm_type("altera_syncram"), + .width_byteena_a(1), + .outdata_reg_a("CLOCK0"), + .outdata_aclr_a("CLEAR0"), + .clock_enable_input_a("NORMAL"), + .power_up_uninitialized("FALSE"), + .init_file("acl_fdiv_memoryC2_uid152_invTables_lutmem.hex"), + .init_file_layout("PORT_A"), + .intended_device_family("Arria 10") + ) memoryC2_uid152_invTables_lutmem_dmem ( + .clocken0(en[0]), + .aclr0(memoryC2_uid152_invTables_lutmem_reset0), + .clock0(clk), + .address_a(memoryC2_uid152_invTables_lutmem_aa), + .q_a(memoryC2_uid152_invTables_lutmem_ir), + .wren_a(), + .wren_b(), + .rden_a(), + .rden_b(), + .data_a(), + .data_b(), + .address_b(), + .clock1(), + .clocken1(), + .clocken2(), + .clocken3(), + .aclr1(), + .addressstall_a(), + .addressstall_b(), + .byteena_a(), + .byteena_b(), + .eccencbypass(), + .eccencparity(), + .sclr(), + .address2_a(), + .address2_b(), + .q_b(), + .eccstatus() + ); + assign memoryC2_uid152_invTables_lutmem_r = memoryC2_uid152_invTables_lutmem_ir[12:0]; + + // yPE_uid52_fpDivTest(BITSELECT,51)@0 + assign yPE_uid52_fpDivTest_b = b[13:0]; + + // redist12_yPE_uid52_fpDivTest_b_2(DELAY,198) + dspba_delay_ver #( .width(14), .depth(2), .reset_kind("ASYNC") ) + redist12_yPE_uid52_fpDivTest_b_2 ( .xin(yPE_uid52_fpDivTest_b), .xout(redist12_yPE_uid52_fpDivTest_b_2_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // yT1_uid158_invPolyEval(BITSELECT,157)@2 + assign yT1_uid158_invPolyEval_b = redist12_yPE_uid52_fpDivTest_b_2_q[13:1]; + + // prodXY_uid174_pT1_uid159_invPolyEval_cma(CHAINMULTADD,184)@2 + 3 + assign prodXY_uid174_pT1_uid159_invPolyEval_cma_reset = areset; + assign prodXY_uid174_pT1_uid159_invPolyEval_cma_ena0 = en[0]; + assign prodXY_uid174_pT1_uid159_invPolyEval_cma_ena1 = prodXY_uid174_pT1_uid159_invPolyEval_cma_ena0; + assign prodXY_uid174_pT1_uid159_invPolyEval_cma_ena2 = prodXY_uid174_pT1_uid159_invPolyEval_cma_ena0; + assign prodXY_uid174_pT1_uid159_invPolyEval_cma_l[0] = $signed({1'b0, prodXY_uid174_pT1_uid159_invPolyEval_cma_a1[0][12:0]}); + assign prodXY_uid174_pT1_uid159_invPolyEval_cma_p[0] = prodXY_uid174_pT1_uid159_invPolyEval_cma_l[0] * prodXY_uid174_pT1_uid159_invPolyEval_cma_c1[0]; + assign prodXY_uid174_pT1_uid159_invPolyEval_cma_u[0] = prodXY_uid174_pT1_uid159_invPolyEval_cma_p[0][26:0]; + assign prodXY_uid174_pT1_uid159_invPolyEval_cma_w[0] = prodXY_uid174_pT1_uid159_invPolyEval_cma_u[0]; + assign prodXY_uid174_pT1_uid159_invPolyEval_cma_x[0] = prodXY_uid174_pT1_uid159_invPolyEval_cma_w[0]; + assign prodXY_uid174_pT1_uid159_invPolyEval_cma_y[0] = prodXY_uid174_pT1_uid159_invPolyEval_cma_x[0]; + always @ (posedge clk or posedge areset) + begin + if (areset) + begin + prodXY_uid174_pT1_uid159_invPolyEval_cma_a0 <= '{default: '0}; + prodXY_uid174_pT1_uid159_invPolyEval_cma_c0 <= '{default: '0}; + end + else + begin + if (prodXY_uid174_pT1_uid159_invPolyEval_cma_ena0 == 1'b1) + begin + prodXY_uid174_pT1_uid159_invPolyEval_cma_a0[0] <= yT1_uid158_invPolyEval_b; + prodXY_uid174_pT1_uid159_invPolyEval_cma_c0[0] <= memoryC2_uid152_invTables_lutmem_r; + end + end + end + always @ (posedge clk or posedge areset) + begin + if (areset) + begin + prodXY_uid174_pT1_uid159_invPolyEval_cma_a1 <= '{default: '0}; + prodXY_uid174_pT1_uid159_invPolyEval_cma_c1 <= '{default: '0}; + end + else + begin + if (prodXY_uid174_pT1_uid159_invPolyEval_cma_ena2 == 1'b1) + begin + prodXY_uid174_pT1_uid159_invPolyEval_cma_a1 <= prodXY_uid174_pT1_uid159_invPolyEval_cma_a0; + prodXY_uid174_pT1_uid159_invPolyEval_cma_c1 <= prodXY_uid174_pT1_uid159_invPolyEval_cma_c0; + end + end + end + always @ (posedge clk or posedge areset) + begin + if (areset) + begin + prodXY_uid174_pT1_uid159_invPolyEval_cma_s <= '{default: '0}; + end + else + begin + if (prodXY_uid174_pT1_uid159_invPolyEval_cma_ena1 == 1'b1) + begin + prodXY_uid174_pT1_uid159_invPolyEval_cma_s[0] <= prodXY_uid174_pT1_uid159_invPolyEval_cma_y[0]; + end + end + end + dspba_delay_ver #( .width(26), .depth(0), .reset_kind("ASYNC") ) + prodXY_uid174_pT1_uid159_invPolyEval_cma_delay ( .xin(prodXY_uid174_pT1_uid159_invPolyEval_cma_s[0][25:0]), .xout(prodXY_uid174_pT1_uid159_invPolyEval_cma_qq), .ena(en[0]), .clk(clk), .aclr(areset) ); + assign prodXY_uid174_pT1_uid159_invPolyEval_cma_q = prodXY_uid174_pT1_uid159_invPolyEval_cma_qq[25:0]; + + // osig_uid175_pT1_uid159_invPolyEval(BITSELECT,174)@5 + assign osig_uid175_pT1_uid159_invPolyEval_b = prodXY_uid174_pT1_uid159_invPolyEval_cma_q[25:12]; + + // highBBits_uid161_invPolyEval(BITSELECT,160)@5 + assign highBBits_uid161_invPolyEval_b = osig_uid175_pT1_uid159_invPolyEval_b[13:1]; + + // redist14_yAddr_uid51_fpDivTest_b_3(DELAY,200) + dspba_delay_ver #( .width(9), .depth(3), .reset_kind("ASYNC") ) + redist14_yAddr_uid51_fpDivTest_b_3 ( .xin(yAddr_uid51_fpDivTest_b), .xout(redist14_yAddr_uid51_fpDivTest_b_3_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // memoryC1_uid149_invTables_lutmem(DUALMEM,180)@3 + 2 + // in j@20000000 + assign memoryC1_uid149_invTables_lutmem_aa = redist14_yAddr_uid51_fpDivTest_b_3_q; + assign memoryC1_uid149_invTables_lutmem_reset0 = areset; + altera_syncram #( + .ram_block_type("M20K"), + .operation_mode("ROM"), + .width_a(22), + .widthad_a(9), + .numwords_a(512), + .lpm_type("altera_syncram"), + .width_byteena_a(1), + .outdata_reg_a("CLOCK0"), + .outdata_aclr_a("CLEAR0"), + .clock_enable_input_a("NORMAL"), + .power_up_uninitialized("FALSE"), + .init_file("acl_fdiv_memoryC1_uid149_invTables_lutmem.hex"), + .init_file_layout("PORT_A"), + .intended_device_family("Arria 10") + ) memoryC1_uid149_invTables_lutmem_dmem ( + .clocken0(en[0]), + .aclr0(memoryC1_uid149_invTables_lutmem_reset0), + .clock0(clk), + .address_a(memoryC1_uid149_invTables_lutmem_aa), + .q_a(memoryC1_uid149_invTables_lutmem_ir), + .wren_a(), + .wren_b(), + .rden_a(), + .rden_b(), + .data_a(), + .data_b(), + .address_b(), + .clock1(), + .clocken1(), + .clocken2(), + .clocken3(), + .aclr1(), + .addressstall_a(), + .addressstall_b(), + .byteena_a(), + .byteena_b(), + .eccencbypass(), + .eccencparity(), + .sclr(), + .address2_a(), + .address2_b(), + .q_b(), + .eccstatus() + ); + assign memoryC1_uid149_invTables_lutmem_r = memoryC1_uid149_invTables_lutmem_ir[21:0]; + + // s1sumAHighB_uid162_invPolyEval(ADD,161)@5 + 1 + assign s1sumAHighB_uid162_invPolyEval_a = {{1{memoryC1_uid149_invTables_lutmem_r[21]}}, memoryC1_uid149_invTables_lutmem_r}; + assign s1sumAHighB_uid162_invPolyEval_b = {{10{highBBits_uid161_invPolyEval_b[12]}}, highBBits_uid161_invPolyEval_b}; + always @ (posedge clk or posedge areset) + begin + if (areset) + begin + s1sumAHighB_uid162_invPolyEval_o <= 23'b0; + end + else if (en == 1'b1) + begin + s1sumAHighB_uid162_invPolyEval_o <= $signed(s1sumAHighB_uid162_invPolyEval_a) + $signed(s1sumAHighB_uid162_invPolyEval_b); + end + end + assign s1sumAHighB_uid162_invPolyEval_q = s1sumAHighB_uid162_invPolyEval_o[22:0]; + + // lowRangeB_uid160_invPolyEval(BITSELECT,159)@5 + assign lowRangeB_uid160_invPolyEval_in = osig_uid175_pT1_uid159_invPolyEval_b[0:0]; + assign lowRangeB_uid160_invPolyEval_b = lowRangeB_uid160_invPolyEval_in[0:0]; + + // redist0_lowRangeB_uid160_invPolyEval_b_1(DELAY,186) + dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") ) + redist0_lowRangeB_uid160_invPolyEval_b_1 ( .xin(lowRangeB_uid160_invPolyEval_b), .xout(redist0_lowRangeB_uid160_invPolyEval_b_1_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // s1_uid163_invPolyEval(BITJOIN,162)@6 + assign s1_uid163_invPolyEval_q = {s1sumAHighB_uid162_invPolyEval_q, redist0_lowRangeB_uid160_invPolyEval_b_1_q}; + + // redist13_yPE_uid52_fpDivTest_b_6_notEnable(LOGICAL,244) + assign redist13_yPE_uid52_fpDivTest_b_6_notEnable_q = ~ (en); + + // redist13_yPE_uid52_fpDivTest_b_6_nor(LOGICAL,245) + assign redist13_yPE_uid52_fpDivTest_b_6_nor_q = ~ (redist13_yPE_uid52_fpDivTest_b_6_notEnable_q | redist13_yPE_uid52_fpDivTest_b_6_sticky_ena_q); + + // redist13_yPE_uid52_fpDivTest_b_6_mem_last(CONSTANT,241) + assign redist13_yPE_uid52_fpDivTest_b_6_mem_last_q = 2'b01; + + // redist13_yPE_uid52_fpDivTest_b_6_cmp(LOGICAL,242) + assign redist13_yPE_uid52_fpDivTest_b_6_cmp_q = redist13_yPE_uid52_fpDivTest_b_6_mem_last_q == redist13_yPE_uid52_fpDivTest_b_6_rdmux_q ? 1'b1 : 1'b0; + + // redist13_yPE_uid52_fpDivTest_b_6_cmpReg(REG,243) + always @ (posedge clk or posedge areset) + begin + if (areset) + begin + redist13_yPE_uid52_fpDivTest_b_6_cmpReg_q <= 1'b0; + end + else if (en == 1'b1) + begin + redist13_yPE_uid52_fpDivTest_b_6_cmpReg_q <= redist13_yPE_uid52_fpDivTest_b_6_cmp_q; + end + end + + // redist13_yPE_uid52_fpDivTest_b_6_sticky_ena(REG,246) + always @ (posedge clk or posedge areset) + begin + if (areset) + begin + redist13_yPE_uid52_fpDivTest_b_6_sticky_ena_q <= 1'b0; + end + else if (redist13_yPE_uid52_fpDivTest_b_6_nor_q == 1'b1) + begin + redist13_yPE_uid52_fpDivTest_b_6_sticky_ena_q <= redist13_yPE_uid52_fpDivTest_b_6_cmpReg_q; + end + end + + // redist13_yPE_uid52_fpDivTest_b_6_enaAnd(LOGICAL,247) + assign redist13_yPE_uid52_fpDivTest_b_6_enaAnd_q = redist13_yPE_uid52_fpDivTest_b_6_sticky_ena_q & en; + + // redist13_yPE_uid52_fpDivTest_b_6_rdcnt(COUNTER,238) + // low=0, high=2, step=1, init=0 + always @ (posedge clk or posedge areset) + begin + if (areset) + begin + redist13_yPE_uid52_fpDivTest_b_6_rdcnt_i <= 2'd0; + redist13_yPE_uid52_fpDivTest_b_6_rdcnt_eq <= 1'b0; + end + else if (en == 1'b1) + begin + if (redist13_yPE_uid52_fpDivTest_b_6_rdcnt_i == 2'd1) + begin + redist13_yPE_uid52_fpDivTest_b_6_rdcnt_eq <= 1'b1; + end + else + begin + redist13_yPE_uid52_fpDivTest_b_6_rdcnt_eq <= 1'b0; + end + if (redist13_yPE_uid52_fpDivTest_b_6_rdcnt_eq == 1'b1) + begin + redist13_yPE_uid52_fpDivTest_b_6_rdcnt_i <= $unsigned(redist13_yPE_uid52_fpDivTest_b_6_rdcnt_i) + $unsigned(2'd2); + end + else + begin + redist13_yPE_uid52_fpDivTest_b_6_rdcnt_i <= $unsigned(redist13_yPE_uid52_fpDivTest_b_6_rdcnt_i) + $unsigned(2'd1); + end + end + end + assign redist13_yPE_uid52_fpDivTest_b_6_rdcnt_q = redist13_yPE_uid52_fpDivTest_b_6_rdcnt_i[1:0]; + + // redist13_yPE_uid52_fpDivTest_b_6_rdmux(MUX,239) + assign redist13_yPE_uid52_fpDivTest_b_6_rdmux_s = en; + always @(redist13_yPE_uid52_fpDivTest_b_6_rdmux_s or redist13_yPE_uid52_fpDivTest_b_6_wraddr_q or redist13_yPE_uid52_fpDivTest_b_6_rdcnt_q) + begin + unique case (redist13_yPE_uid52_fpDivTest_b_6_rdmux_s) + 1'b0 : redist13_yPE_uid52_fpDivTest_b_6_rdmux_q = redist13_yPE_uid52_fpDivTest_b_6_wraddr_q; + 1'b1 : redist13_yPE_uid52_fpDivTest_b_6_rdmux_q = redist13_yPE_uid52_fpDivTest_b_6_rdcnt_q; + default : redist13_yPE_uid52_fpDivTest_b_6_rdmux_q = 2'b0; + endcase + end + + // redist13_yPE_uid52_fpDivTest_b_6_wraddr(REG,240) + always @ (posedge clk or posedge areset) + begin + if (areset) + begin + redist13_yPE_uid52_fpDivTest_b_6_wraddr_q <= 2'b10; + end + else + begin + redist13_yPE_uid52_fpDivTest_b_6_wraddr_q <= redist13_yPE_uid52_fpDivTest_b_6_rdmux_q; + end + end + + // redist13_yPE_uid52_fpDivTest_b_6_mem(DUALMEM,237) + assign redist13_yPE_uid52_fpDivTest_b_6_mem_ia = redist12_yPE_uid52_fpDivTest_b_2_q; + assign redist13_yPE_uid52_fpDivTest_b_6_mem_aa = redist13_yPE_uid52_fpDivTest_b_6_wraddr_q; + assign redist13_yPE_uid52_fpDivTest_b_6_mem_ab = redist13_yPE_uid52_fpDivTest_b_6_rdmux_q; + assign redist13_yPE_uid52_fpDivTest_b_6_mem_reset0 = areset; + altera_syncram #( + .ram_block_type("MLAB"), + .operation_mode("DUAL_PORT"), + .width_a(14), + .widthad_a(2), + .numwords_a(3), + .width_b(14), + .widthad_b(2), + .numwords_b(3), + .lpm_type("altera_syncram"), + .width_byteena_a(1), + .address_reg_b("CLOCK0"), + .indata_reg_b("CLOCK0"), + .rdcontrol_reg_b("CLOCK0"), + .byteena_reg_b("CLOCK0"), + .outdata_reg_b("CLOCK1"), + .outdata_aclr_b("CLEAR1"), + .clock_enable_input_a("NORMAL"), + .clock_enable_input_b("NORMAL"), + .clock_enable_output_b("NORMAL"), + .read_during_write_mode_mixed_ports("DONT_CARE"), + .power_up_uninitialized("TRUE"), + .intended_device_family("Arria 10") + ) redist13_yPE_uid52_fpDivTest_b_6_mem_dmem ( + .clocken1(redist13_yPE_uid52_fpDivTest_b_6_enaAnd_q[0]), + .clocken0(VCC_q[0]), + .clock0(clk), + .aclr1(redist13_yPE_uid52_fpDivTest_b_6_mem_reset0), + .clock1(clk), + .address_a(redist13_yPE_uid52_fpDivTest_b_6_mem_aa), + .data_a(redist13_yPE_uid52_fpDivTest_b_6_mem_ia), + .wren_a(en[0]), + .address_b(redist13_yPE_uid52_fpDivTest_b_6_mem_ab), + .q_b(redist13_yPE_uid52_fpDivTest_b_6_mem_iq), + .wren_b(), + .rden_a(), + .rden_b(), + .data_b(), + .clocken2(), + .clocken3(), + .aclr0(), + .addressstall_a(), + .addressstall_b(), + .byteena_a(), + .byteena_b(), + .eccencbypass(), + .eccencparity(), + .sclr(), + .address2_a(), + .address2_b(), + .q_a(), + .eccstatus() + ); + assign redist13_yPE_uid52_fpDivTest_b_6_mem_q = redist13_yPE_uid52_fpDivTest_b_6_mem_iq[13:0]; + + // prodXY_uid177_pT2_uid165_invPolyEval_cma(CHAINMULTADD,185)@6 + 3 + assign prodXY_uid177_pT2_uid165_invPolyEval_cma_reset = areset; + assign prodXY_uid177_pT2_uid165_invPolyEval_cma_ena0 = en[0]; + assign prodXY_uid177_pT2_uid165_invPolyEval_cma_ena1 = prodXY_uid177_pT2_uid165_invPolyEval_cma_ena0; + assign prodXY_uid177_pT2_uid165_invPolyEval_cma_ena2 = prodXY_uid177_pT2_uid165_invPolyEval_cma_ena0; + assign prodXY_uid177_pT2_uid165_invPolyEval_cma_l[0] = $signed({1'b0, prodXY_uid177_pT2_uid165_invPolyEval_cma_a1[0][13:0]}); + assign prodXY_uid177_pT2_uid165_invPolyEval_cma_p[0] = prodXY_uid177_pT2_uid165_invPolyEval_cma_l[0] * prodXY_uid177_pT2_uid165_invPolyEval_cma_c1[0]; + assign prodXY_uid177_pT2_uid165_invPolyEval_cma_u[0] = prodXY_uid177_pT2_uid165_invPolyEval_cma_p[0][38:0]; + assign prodXY_uid177_pT2_uid165_invPolyEval_cma_w[0] = prodXY_uid177_pT2_uid165_invPolyEval_cma_u[0]; + assign prodXY_uid177_pT2_uid165_invPolyEval_cma_x[0] = prodXY_uid177_pT2_uid165_invPolyEval_cma_w[0]; + assign prodXY_uid177_pT2_uid165_invPolyEval_cma_y[0] = prodXY_uid177_pT2_uid165_invPolyEval_cma_x[0]; + always @ (posedge clk or posedge areset) + begin + if (areset) + begin + prodXY_uid177_pT2_uid165_invPolyEval_cma_a0 <= '{default: '0}; + prodXY_uid177_pT2_uid165_invPolyEval_cma_c0 <= '{default: '0}; + end + else + begin + if (prodXY_uid177_pT2_uid165_invPolyEval_cma_ena0 == 1'b1) + begin + prodXY_uid177_pT2_uid165_invPolyEval_cma_a0[0] <= redist13_yPE_uid52_fpDivTest_b_6_mem_q; + prodXY_uid177_pT2_uid165_invPolyEval_cma_c0[0] <= s1_uid163_invPolyEval_q; + end + end + end + always @ (posedge clk or posedge areset) + begin + if (areset) + begin + prodXY_uid177_pT2_uid165_invPolyEval_cma_a1 <= '{default: '0}; + prodXY_uid177_pT2_uid165_invPolyEval_cma_c1 <= '{default: '0}; + end + else + begin + if (prodXY_uid177_pT2_uid165_invPolyEval_cma_ena2 == 1'b1) + begin + prodXY_uid177_pT2_uid165_invPolyEval_cma_a1 <= prodXY_uid177_pT2_uid165_invPolyEval_cma_a0; + prodXY_uid177_pT2_uid165_invPolyEval_cma_c1 <= prodXY_uid177_pT2_uid165_invPolyEval_cma_c0; + end + end + end + always @ (posedge clk or posedge areset) + begin + if (areset) + begin + prodXY_uid177_pT2_uid165_invPolyEval_cma_s <= '{default: '0}; + end + else + begin + if (prodXY_uid177_pT2_uid165_invPolyEval_cma_ena1 == 1'b1) + begin + prodXY_uid177_pT2_uid165_invPolyEval_cma_s[0] <= prodXY_uid177_pT2_uid165_invPolyEval_cma_y[0]; + end + end + end + dspba_delay_ver #( .width(38), .depth(0), .reset_kind("ASYNC") ) + prodXY_uid177_pT2_uid165_invPolyEval_cma_delay ( .xin(prodXY_uid177_pT2_uid165_invPolyEval_cma_s[0][37:0]), .xout(prodXY_uid177_pT2_uid165_invPolyEval_cma_qq), .ena(en[0]), .clk(clk), .aclr(areset) ); + assign prodXY_uid177_pT2_uid165_invPolyEval_cma_q = prodXY_uid177_pT2_uid165_invPolyEval_cma_qq[37:0]; + + // osig_uid178_pT2_uid165_invPolyEval(BITSELECT,177)@9 + assign osig_uid178_pT2_uid165_invPolyEval_b = prodXY_uid177_pT2_uid165_invPolyEval_cma_q[37:13]; + + // highBBits_uid167_invPolyEval(BITSELECT,166)@9 + assign highBBits_uid167_invPolyEval_b = osig_uid178_pT2_uid165_invPolyEval_b[24:2]; + + // redist15_yAddr_uid51_fpDivTest_b_7(DELAY,201) + dspba_delay_ver #( .width(9), .depth(4), .reset_kind("ASYNC") ) + redist15_yAddr_uid51_fpDivTest_b_7 ( .xin(redist14_yAddr_uid51_fpDivTest_b_3_q), .xout(redist15_yAddr_uid51_fpDivTest_b_7_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // memoryC0_uid146_invTables_lutmem(DUALMEM,179)@7 + 2 + // in j@20000000 + assign memoryC0_uid146_invTables_lutmem_aa = redist15_yAddr_uid51_fpDivTest_b_7_q; + assign memoryC0_uid146_invTables_lutmem_reset0 = areset; + altera_syncram #( + .ram_block_type("M20K"), + .operation_mode("ROM"), + .width_a(32), + .widthad_a(9), + .numwords_a(512), + .lpm_type("altera_syncram"), + .width_byteena_a(1), + .outdata_reg_a("CLOCK0"), + .outdata_aclr_a("CLEAR0"), + .clock_enable_input_a("NORMAL"), + .power_up_uninitialized("FALSE"), + .init_file("acl_fdiv_memoryC0_uid146_invTables_lutmem.hex"), + .init_file_layout("PORT_A"), + .intended_device_family("Arria 10") + ) memoryC0_uid146_invTables_lutmem_dmem ( + .clocken0(en[0]), + .aclr0(memoryC0_uid146_invTables_lutmem_reset0), + .clock0(clk), + .address_a(memoryC0_uid146_invTables_lutmem_aa), + .q_a(memoryC0_uid146_invTables_lutmem_ir), + .wren_a(), + .wren_b(), + .rden_a(), + .rden_b(), + .data_a(), + .data_b(), + .address_b(), + .clock1(), + .clocken1(), + .clocken2(), + .clocken3(), + .aclr1(), + .addressstall_a(), + .addressstall_b(), + .byteena_a(), + .byteena_b(), + .eccencbypass(), + .eccencparity(), + .sclr(), + .address2_a(), + .address2_b(), + .q_b(), + .eccstatus() + ); + assign memoryC0_uid146_invTables_lutmem_r = memoryC0_uid146_invTables_lutmem_ir[31:0]; + + // s2sumAHighB_uid168_invPolyEval(ADD,167)@9 + assign s2sumAHighB_uid168_invPolyEval_a = {{1{memoryC0_uid146_invTables_lutmem_r[31]}}, memoryC0_uid146_invTables_lutmem_r}; + assign s2sumAHighB_uid168_invPolyEval_b = {{10{highBBits_uid167_invPolyEval_b[22]}}, highBBits_uid167_invPolyEval_b}; + assign s2sumAHighB_uid168_invPolyEval_o = $signed(s2sumAHighB_uid168_invPolyEval_a) + $signed(s2sumAHighB_uid168_invPolyEval_b); + assign s2sumAHighB_uid168_invPolyEval_q = s2sumAHighB_uid168_invPolyEval_o[32:0]; + + // lowRangeB_uid166_invPolyEval(BITSELECT,165)@9 + assign lowRangeB_uid166_invPolyEval_in = osig_uid178_pT2_uid165_invPolyEval_b[1:0]; + assign lowRangeB_uid166_invPolyEval_b = lowRangeB_uid166_invPolyEval_in[1:0]; + + // s2_uid169_invPolyEval(BITJOIN,168)@9 + assign s2_uid169_invPolyEval_q = {s2sumAHighB_uid168_invPolyEval_q, lowRangeB_uid166_invPolyEval_b}; + + // invY_uid54_fpDivTest(BITSELECT,53)@9 + assign invY_uid54_fpDivTest_in = s2_uid169_invPolyEval_q[31:0]; + assign invY_uid54_fpDivTest_b = invY_uid54_fpDivTest_in[31:5]; + + // redist11_invY_uid54_fpDivTest_b_1(DELAY,197) + dspba_delay_ver #( .width(27), .depth(1), .reset_kind("ASYNC") ) + redist11_invY_uid54_fpDivTest_b_1 ( .xin(invY_uid54_fpDivTest_b), .xout(redist11_invY_uid54_fpDivTest_b_1_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // prodXY_uid171_divValPreNorm_uid59_fpDivTest_cma(CHAINMULTADD,183)@10 + 3 + assign prodXY_uid171_divValPreNorm_uid59_fpDivTest_cma_reset = areset; + assign prodXY_uid171_divValPreNorm_uid59_fpDivTest_cma_ena0 = en[0]; + assign prodXY_uid171_divValPreNorm_uid59_fpDivTest_cma_ena1 = prodXY_uid171_divValPreNorm_uid59_fpDivTest_cma_ena0; + assign prodXY_uid171_divValPreNorm_uid59_fpDivTest_cma_ena2 = prodXY_uid171_divValPreNorm_uid59_fpDivTest_cma_ena0; + assign prodXY_uid171_divValPreNorm_uid59_fpDivTest_cma_p[0] = prodXY_uid171_divValPreNorm_uid59_fpDivTest_cma_a1[0] * prodXY_uid171_divValPreNorm_uid59_fpDivTest_cma_c1[0]; + assign prodXY_uid171_divValPreNorm_uid59_fpDivTest_cma_u[0] = prodXY_uid171_divValPreNorm_uid59_fpDivTest_cma_p[0][50:0]; + assign prodXY_uid171_divValPreNorm_uid59_fpDivTest_cma_w[0] = prodXY_uid171_divValPreNorm_uid59_fpDivTest_cma_u[0]; + assign prodXY_uid171_divValPreNorm_uid59_fpDivTest_cma_x[0] = prodXY_uid171_divValPreNorm_uid59_fpDivTest_cma_w[0]; + assign prodXY_uid171_divValPreNorm_uid59_fpDivTest_cma_y[0] = prodXY_uid171_divValPreNorm_uid59_fpDivTest_cma_x[0]; + always @ (posedge clk or posedge areset) + begin + if (areset) + begin + prodXY_uid171_divValPreNorm_uid59_fpDivTest_cma_a0 <= '{default: '0}; + prodXY_uid171_divValPreNorm_uid59_fpDivTest_cma_c0 <= '{default: '0}; + end + else + begin + if (prodXY_uid171_divValPreNorm_uid59_fpDivTest_cma_ena0 == 1'b1) + begin + prodXY_uid171_divValPreNorm_uid59_fpDivTest_cma_a0[0] <= redist11_invY_uid54_fpDivTest_b_1_q; + prodXY_uid171_divValPreNorm_uid59_fpDivTest_cma_c0[0] <= lOAdded_uid57_fpDivTest_q; + end + end + end + always @ (posedge clk or posedge areset) + begin + if (areset) + begin + prodXY_uid171_divValPreNorm_uid59_fpDivTest_cma_a1 <= '{default: '0}; + prodXY_uid171_divValPreNorm_uid59_fpDivTest_cma_c1 <= '{default: '0}; + end + else + begin + if (prodXY_uid171_divValPreNorm_uid59_fpDivTest_cma_ena2 == 1'b1) + begin + prodXY_uid171_divValPreNorm_uid59_fpDivTest_cma_a1 <= prodXY_uid171_divValPreNorm_uid59_fpDivTest_cma_a0; + prodXY_uid171_divValPreNorm_uid59_fpDivTest_cma_c1 <= prodXY_uid171_divValPreNorm_uid59_fpDivTest_cma_c0; + end + end + end + always @ (posedge clk or posedge areset) + begin + if (areset) + begin + prodXY_uid171_divValPreNorm_uid59_fpDivTest_cma_s <= '{default: '0}; + end + else + begin + if (prodXY_uid171_divValPreNorm_uid59_fpDivTest_cma_ena1 == 1'b1) + begin + prodXY_uid171_divValPreNorm_uid59_fpDivTest_cma_s[0] <= prodXY_uid171_divValPreNorm_uid59_fpDivTest_cma_y[0]; + end + end + end + dspba_delay_ver #( .width(51), .depth(0), .reset_kind("ASYNC") ) + prodXY_uid171_divValPreNorm_uid59_fpDivTest_cma_delay ( .xin(prodXY_uid171_divValPreNorm_uid59_fpDivTest_cma_s[0][50:0]), .xout(prodXY_uid171_divValPreNorm_uid59_fpDivTest_cma_qq), .ena(en[0]), .clk(clk), .aclr(areset) ); + assign prodXY_uid171_divValPreNorm_uid59_fpDivTest_cma_q = prodXY_uid171_divValPreNorm_uid59_fpDivTest_cma_qq[50:0]; + + // osig_uid172_divValPreNorm_uid59_fpDivTest(BITSELECT,171)@13 + assign osig_uid172_divValPreNorm_uid59_fpDivTest_b = prodXY_uid171_divValPreNorm_uid59_fpDivTest_cma_q[50:23]; + + // updatedY_uid16_fpDivTest(BITJOIN,15)@12 + assign updatedY_uid16_fpDivTest_q = {GND_q, paddingY_uid15_fpDivTest_q}; + + // fracYZero_uid15_fpDivTest(LOGICAL,16)@12 + 1 + assign fracYZero_uid15_fpDivTest_a = {1'b0, redist17_fracY_uid13_fpDivTest_b_12_outputreg_q}; + assign fracYZero_uid15_fpDivTest_qi = fracYZero_uid15_fpDivTest_a == updatedY_uid16_fpDivTest_q ? 1'b1 : 1'b0; + dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") ) + fracYZero_uid15_fpDivTest_delay ( .xin(fracYZero_uid15_fpDivTest_qi), .xout(fracYZero_uid15_fpDivTest_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // divValPreNormYPow2Exc_uid63_fpDivTest(MUX,62)@13 + assign divValPreNormYPow2Exc_uid63_fpDivTest_s = fracYZero_uid15_fpDivTest_q; + always @(divValPreNormYPow2Exc_uid63_fpDivTest_s or en or osig_uid172_divValPreNorm_uid59_fpDivTest_b or oFracXZ4_uid61_fpDivTest_q) + begin + unique case (divValPreNormYPow2Exc_uid63_fpDivTest_s) + 1'b0 : divValPreNormYPow2Exc_uid63_fpDivTest_q = osig_uid172_divValPreNorm_uid59_fpDivTest_b; + 1'b1 : divValPreNormYPow2Exc_uid63_fpDivTest_q = oFracXZ4_uid61_fpDivTest_q; + default : divValPreNormYPow2Exc_uid63_fpDivTest_q = 28'b0; + endcase + end + + // norm_uid64_fpDivTest(BITSELECT,63)@13 + assign norm_uid64_fpDivTest_b = divValPreNormYPow2Exc_uid63_fpDivTest_q[27:27]; + + // zeroPaddingInAddition_uid74_fpDivTest(CONSTANT,73) + assign zeroPaddingInAddition_uid74_fpDivTest_q = 24'b000000000000000000000000; + + // expFracPostRnd_uid75_fpDivTest(BITJOIN,74)@13 + assign expFracPostRnd_uid75_fpDivTest_q = {norm_uid64_fpDivTest_b, zeroPaddingInAddition_uid74_fpDivTest_q, VCC_q}; + + // cstBiasM1_uid6_fpDivTest(CONSTANT,5) + assign cstBiasM1_uid6_fpDivTest_q = 8'b01111110; + + // expXmY_uid47_fpDivTest(SUB,46)@12 + 1 + assign expXmY_uid47_fpDivTest_a = {1'b0, redist24_expX_uid9_fpDivTest_b_12_outputreg_q}; + assign expXmY_uid47_fpDivTest_b = {1'b0, redist19_expY_uid12_fpDivTest_b_12_outputreg_q}; + always @ (posedge clk or posedge areset) + begin + if (areset) + begin + expXmY_uid47_fpDivTest_o <= 9'b0; + end + else if (en == 1'b1) + begin + expXmY_uid47_fpDivTest_o <= $unsigned(expXmY_uid47_fpDivTest_a) - $unsigned(expXmY_uid47_fpDivTest_b); + end + end + assign expXmY_uid47_fpDivTest_q = expXmY_uid47_fpDivTest_o[8:0]; + + // expR_uid48_fpDivTest(ADD,47)@13 + assign expR_uid48_fpDivTest_a = {{2{expXmY_uid47_fpDivTest_q[8]}}, expXmY_uid47_fpDivTest_q}; + assign expR_uid48_fpDivTest_b = {3'b000, cstBiasM1_uid6_fpDivTest_q}; + assign expR_uid48_fpDivTest_o = $signed(expR_uid48_fpDivTest_a) + $signed(expR_uid48_fpDivTest_b); + assign expR_uid48_fpDivTest_q = expR_uid48_fpDivTest_o[9:0]; + + // divValPreNormHigh_uid65_fpDivTest(BITSELECT,64)@13 + assign divValPreNormHigh_uid65_fpDivTest_in = divValPreNormYPow2Exc_uid63_fpDivTest_q[26:0]; + assign divValPreNormHigh_uid65_fpDivTest_b = divValPreNormHigh_uid65_fpDivTest_in[26:2]; + + // divValPreNormLow_uid66_fpDivTest(BITSELECT,65)@13 + assign divValPreNormLow_uid66_fpDivTest_in = divValPreNormYPow2Exc_uid63_fpDivTest_q[25:0]; + assign divValPreNormLow_uid66_fpDivTest_b = divValPreNormLow_uid66_fpDivTest_in[25:1]; + + // normFracRnd_uid67_fpDivTest(MUX,66)@13 + assign normFracRnd_uid67_fpDivTest_s = norm_uid64_fpDivTest_b; + always @(normFracRnd_uid67_fpDivTest_s or en or divValPreNormLow_uid66_fpDivTest_b or divValPreNormHigh_uid65_fpDivTest_b) + begin + unique case (normFracRnd_uid67_fpDivTest_s) + 1'b0 : normFracRnd_uid67_fpDivTest_q = divValPreNormLow_uid66_fpDivTest_b; + 1'b1 : normFracRnd_uid67_fpDivTest_q = divValPreNormHigh_uid65_fpDivTest_b; + default : normFracRnd_uid67_fpDivTest_q = 25'b0; + endcase + end + + // expFracRnd_uid68_fpDivTest(BITJOIN,67)@13 + assign expFracRnd_uid68_fpDivTest_q = {expR_uid48_fpDivTest_q, normFracRnd_uid67_fpDivTest_q}; + + // expFracPostRnd_uid76_fpDivTest(ADD,75)@13 + 1 + assign expFracPostRnd_uid76_fpDivTest_a = {{2{expFracRnd_uid68_fpDivTest_q[34]}}, expFracRnd_uid68_fpDivTest_q}; + assign expFracPostRnd_uid76_fpDivTest_b = {11'b00000000000, expFracPostRnd_uid75_fpDivTest_q}; + always @ (posedge clk or posedge areset) + begin + if (areset) + begin + expFracPostRnd_uid76_fpDivTest_o <= 37'b0; + end + else if (en == 1'b1) + begin + expFracPostRnd_uid76_fpDivTest_o <= $signed(expFracPostRnd_uid76_fpDivTest_a) + $signed(expFracPostRnd_uid76_fpDivTest_b); + end + end + assign expFracPostRnd_uid76_fpDivTest_q = expFracPostRnd_uid76_fpDivTest_o[35:0]; + + // fracPostRndF_uid79_fpDivTest(BITSELECT,78)@14 + assign fracPostRndF_uid79_fpDivTest_in = expFracPostRnd_uid76_fpDivTest_q[24:0]; + assign fracPostRndF_uid79_fpDivTest_b = fracPostRndF_uid79_fpDivTest_in[24:1]; + + // invYO_uid55_fpDivTest(BITSELECT,54)@9 + assign invYO_uid55_fpDivTest_in = s2_uid169_invPolyEval_q[32:0]; + assign invYO_uid55_fpDivTest_b = invYO_uid55_fpDivTest_in[32:32]; + + // redist10_invYO_uid55_fpDivTest_b_5(DELAY,196) + dspba_delay_ver #( .width(1), .depth(5), .reset_kind("ASYNC") ) + redist10_invYO_uid55_fpDivTest_b_5 ( .xin(invYO_uid55_fpDivTest_b), .xout(redist10_invYO_uid55_fpDivTest_b_5_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // fracPostRndF_uid80_fpDivTest(MUX,79)@14 + assign fracPostRndF_uid80_fpDivTest_s = redist10_invYO_uid55_fpDivTest_b_5_q; + always @(fracPostRndF_uid80_fpDivTest_s or en or fracPostRndF_uid79_fpDivTest_b or fracXExt_uid77_fpDivTest_q) + begin + unique case (fracPostRndF_uid80_fpDivTest_s) + 1'b0 : fracPostRndF_uid80_fpDivTest_q = fracPostRndF_uid79_fpDivTest_b; + 1'b1 : fracPostRndF_uid80_fpDivTest_q = fracXExt_uid77_fpDivTest_q; + default : fracPostRndF_uid80_fpDivTest_q = 24'b0; + endcase + end + + // redist8_fracPostRndF_uid80_fpDivTest_q_5_wraddr(REG,229) + always @ (posedge clk or posedge areset) + begin + if (areset) + begin + redist8_fracPostRndF_uid80_fpDivTest_q_5_wraddr_q <= 2'b10; + end + else + begin + redist8_fracPostRndF_uid80_fpDivTest_q_5_wraddr_q <= redist8_fracPostRndF_uid80_fpDivTest_q_5_rdmux_q; + end + end + + // redist8_fracPostRndF_uid80_fpDivTest_q_5_mem(DUALMEM,226) + assign redist8_fracPostRndF_uid80_fpDivTest_q_5_mem_ia = fracPostRndF_uid80_fpDivTest_q; + assign redist8_fracPostRndF_uid80_fpDivTest_q_5_mem_aa = redist8_fracPostRndF_uid80_fpDivTest_q_5_wraddr_q; + assign redist8_fracPostRndF_uid80_fpDivTest_q_5_mem_ab = redist8_fracPostRndF_uid80_fpDivTest_q_5_rdmux_q; + assign redist8_fracPostRndF_uid80_fpDivTest_q_5_mem_reset0 = areset; + altera_syncram #( + .ram_block_type("MLAB"), + .operation_mode("DUAL_PORT"), + .width_a(24), + .widthad_a(2), + .numwords_a(3), + .width_b(24), + .widthad_b(2), + .numwords_b(3), + .lpm_type("altera_syncram"), + .width_byteena_a(1), + .address_reg_b("CLOCK0"), + .indata_reg_b("CLOCK0"), + .rdcontrol_reg_b("CLOCK0"), + .byteena_reg_b("CLOCK0"), + .outdata_reg_b("CLOCK1"), + .outdata_aclr_b("CLEAR1"), + .clock_enable_input_a("NORMAL"), + .clock_enable_input_b("NORMAL"), + .clock_enable_output_b("NORMAL"), + .read_during_write_mode_mixed_ports("DONT_CARE"), + .power_up_uninitialized("TRUE"), + .intended_device_family("Arria 10") + ) redist8_fracPostRndF_uid80_fpDivTest_q_5_mem_dmem ( + .clocken1(redist8_fracPostRndF_uid80_fpDivTest_q_5_enaAnd_q[0]), + .clocken0(VCC_q[0]), + .clock0(clk), + .aclr1(redist8_fracPostRndF_uid80_fpDivTest_q_5_mem_reset0), + .clock1(clk), + .address_a(redist8_fracPostRndF_uid80_fpDivTest_q_5_mem_aa), + .data_a(redist8_fracPostRndF_uid80_fpDivTest_q_5_mem_ia), + .wren_a(en[0]), + .address_b(redist8_fracPostRndF_uid80_fpDivTest_q_5_mem_ab), + .q_b(redist8_fracPostRndF_uid80_fpDivTest_q_5_mem_iq), + .wren_b(), + .rden_a(), + .rden_b(), + .data_b(), + .clocken2(), + .clocken3(), + .aclr0(), + .addressstall_a(), + .addressstall_b(), + .byteena_a(), + .byteena_b(), + .eccencbypass(), + .eccencparity(), + .sclr(), + .address2_a(), + .address2_b(), + .q_a(), + .eccstatus() + ); + assign redist8_fracPostRndF_uid80_fpDivTest_q_5_mem_q = redist8_fracPostRndF_uid80_fpDivTest_q_5_mem_iq[23:0]; + + // redist8_fracPostRndF_uid80_fpDivTest_q_5_outputreg(DELAY,225) + dspba_delay_ver #( .width(24), .depth(1), .reset_kind("ASYNC") ) + redist8_fracPostRndF_uid80_fpDivTest_q_5_outputreg ( .xin(redist8_fracPostRndF_uid80_fpDivTest_q_5_mem_q), .xout(redist8_fracPostRndF_uid80_fpDivTest_q_5_outputreg_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // betweenFPwF_uid102_fpDivTest(BITSELECT,101)@19 + assign betweenFPwF_uid102_fpDivTest_in = redist8_fracPostRndF_uid80_fpDivTest_q_5_outputreg_q[0:0]; + assign betweenFPwF_uid102_fpDivTest_b = betweenFPwF_uid102_fpDivTest_in[0:0]; + + // redist26_expX_uid9_fpDivTest_b_18(DELAY,212) + dspba_delay_ver #( .width(8), .depth(4), .reset_kind("ASYNC") ) + redist26_expX_uid9_fpDivTest_b_18 ( .xin(redist25_expX_uid9_fpDivTest_b_14_q), .xout(redist26_expX_uid9_fpDivTest_b_18_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // redist23_fracX_uid10_fpDivTest_b_18_inputreg(DELAY,285) + dspba_delay_ver #( .width(23), .depth(1), .reset_kind("ASYNC") ) + redist23_fracX_uid10_fpDivTest_b_18_inputreg ( .xin(redist22_fracX_uid10_fpDivTest_b_14_q), .xout(redist23_fracX_uid10_fpDivTest_b_18_inputreg_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // redist23_fracX_uid10_fpDivTest_b_18(DELAY,209) + dspba_delay_ver #( .width(23), .depth(3), .reset_kind("ASYNC") ) + redist23_fracX_uid10_fpDivTest_b_18 ( .xin(redist23_fracX_uid10_fpDivTest_b_18_inputreg_q), .xout(redist23_fracX_uid10_fpDivTest_b_18_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // qDivProdLTX_opB_uid100_fpDivTest(BITJOIN,99)@18 + assign qDivProdLTX_opB_uid100_fpDivTest_q = {redist26_expX_uid9_fpDivTest_b_18_q, redist23_fracX_uid10_fpDivTest_b_18_q}; + + // lOAdded_uid87_fpDivTest(BITJOIN,86)@14 + assign lOAdded_uid87_fpDivTest_q = {VCC_q, redist18_fracY_uid13_fpDivTest_b_14_q}; + + // lOAdded_uid84_fpDivTest(BITJOIN,83)@14 + assign lOAdded_uid84_fpDivTest_q = {VCC_q, fracPostRndF_uid80_fpDivTest_q}; + + // qDivProd_uid89_fpDivTest_cma(CHAINMULTADD,182)@14 + 3 + assign qDivProd_uid89_fpDivTest_cma_reset = areset; + assign qDivProd_uid89_fpDivTest_cma_ena0 = en[0]; + assign qDivProd_uid89_fpDivTest_cma_ena1 = qDivProd_uid89_fpDivTest_cma_ena0; + assign qDivProd_uid89_fpDivTest_cma_ena2 = qDivProd_uid89_fpDivTest_cma_ena0; + assign qDivProd_uid89_fpDivTest_cma_p[0] = qDivProd_uid89_fpDivTest_cma_a1[0] * qDivProd_uid89_fpDivTest_cma_c1[0]; + assign qDivProd_uid89_fpDivTest_cma_u[0] = qDivProd_uid89_fpDivTest_cma_p[0][48:0]; + assign qDivProd_uid89_fpDivTest_cma_w[0] = qDivProd_uid89_fpDivTest_cma_u[0]; + assign qDivProd_uid89_fpDivTest_cma_x[0] = qDivProd_uid89_fpDivTest_cma_w[0]; + assign qDivProd_uid89_fpDivTest_cma_y[0] = qDivProd_uid89_fpDivTest_cma_x[0]; + always @ (posedge clk or posedge areset) + begin + if (areset) + begin + qDivProd_uid89_fpDivTest_cma_a0 <= '{default: '0}; + qDivProd_uid89_fpDivTest_cma_c0 <= '{default: '0}; + end + else + begin + if (qDivProd_uid89_fpDivTest_cma_ena0 == 1'b1) + begin + qDivProd_uid89_fpDivTest_cma_a0[0] <= lOAdded_uid84_fpDivTest_q; + qDivProd_uid89_fpDivTest_cma_c0[0] <= lOAdded_uid87_fpDivTest_q; + end + end + end + always @ (posedge clk or posedge areset) + begin + if (areset) + begin + qDivProd_uid89_fpDivTest_cma_a1 <= '{default: '0}; + qDivProd_uid89_fpDivTest_cma_c1 <= '{default: '0}; + end + else + begin + if (qDivProd_uid89_fpDivTest_cma_ena2 == 1'b1) + begin + qDivProd_uid89_fpDivTest_cma_a1 <= qDivProd_uid89_fpDivTest_cma_a0; + qDivProd_uid89_fpDivTest_cma_c1 <= qDivProd_uid89_fpDivTest_cma_c0; + end + end + end + always @ (posedge clk or posedge areset) + begin + if (areset) + begin + qDivProd_uid89_fpDivTest_cma_s <= '{default: '0}; + end + else + begin + if (qDivProd_uid89_fpDivTest_cma_ena1 == 1'b1) + begin + qDivProd_uid89_fpDivTest_cma_s[0] <= qDivProd_uid89_fpDivTest_cma_y[0]; + end + end + end + dspba_delay_ver #( .width(49), .depth(0), .reset_kind("ASYNC") ) + qDivProd_uid89_fpDivTest_cma_delay ( .xin(qDivProd_uid89_fpDivTest_cma_s[0][48:0]), .xout(qDivProd_uid89_fpDivTest_cma_qq), .ena(en[0]), .clk(clk), .aclr(areset) ); + assign qDivProd_uid89_fpDivTest_cma_q = qDivProd_uid89_fpDivTest_cma_qq[48:0]; + + // qDivProdNorm_uid90_fpDivTest(BITSELECT,89)@17 + assign qDivProdNorm_uid90_fpDivTest_b = qDivProd_uid89_fpDivTest_cma_q[48:48]; + + // cstBias_uid7_fpDivTest(CONSTANT,6) + assign cstBias_uid7_fpDivTest_q = 8'b01111111; + + // qDivProdExp_opBs_uid95_fpDivTest(SUB,94)@17 + 1 + assign qDivProdExp_opBs_uid95_fpDivTest_a = {1'b0, cstBias_uid7_fpDivTest_q}; + assign qDivProdExp_opBs_uid95_fpDivTest_b = {8'b00000000, qDivProdNorm_uid90_fpDivTest_b}; + always @ (posedge clk or posedge areset) + begin + if (areset) + begin + qDivProdExp_opBs_uid95_fpDivTest_o <= 9'b0; + end + else if (en == 1'b1) + begin + qDivProdExp_opBs_uid95_fpDivTest_o <= $unsigned(qDivProdExp_opBs_uid95_fpDivTest_a) - $unsigned(qDivProdExp_opBs_uid95_fpDivTest_b); + end + end + assign qDivProdExp_opBs_uid95_fpDivTest_q = qDivProdExp_opBs_uid95_fpDivTest_o[8:0]; + + // expPostRndFR_uid81_fpDivTest(BITSELECT,80)@14 + assign expPostRndFR_uid81_fpDivTest_in = expFracPostRnd_uid76_fpDivTest_q[32:0]; + assign expPostRndFR_uid81_fpDivTest_b = expPostRndFR_uid81_fpDivTest_in[32:25]; + + // expPostRndF_uid82_fpDivTest(MUX,81)@14 + assign expPostRndF_uid82_fpDivTest_s = redist10_invYO_uid55_fpDivTest_b_5_q; + always @(expPostRndF_uid82_fpDivTest_s or en or expPostRndFR_uid81_fpDivTest_b or redist25_expX_uid9_fpDivTest_b_14_q) + begin + unique case (expPostRndF_uid82_fpDivTest_s) + 1'b0 : expPostRndF_uid82_fpDivTest_q = expPostRndFR_uid81_fpDivTest_b; + 1'b1 : expPostRndF_uid82_fpDivTest_q = redist25_expX_uid9_fpDivTest_b_14_q; + default : expPostRndF_uid82_fpDivTest_q = 8'b0; + endcase + end + + // qDivProdExp_opA_uid94_fpDivTest(ADD,93)@14 + 1 + assign qDivProdExp_opA_uid94_fpDivTest_a = {1'b0, redist20_expY_uid12_fpDivTest_b_14_q}; + assign qDivProdExp_opA_uid94_fpDivTest_b = {1'b0, expPostRndF_uid82_fpDivTest_q}; + always @ (posedge clk or posedge areset) + begin + if (areset) + begin + qDivProdExp_opA_uid94_fpDivTest_o <= 9'b0; + end + else if (en == 1'b1) + begin + qDivProdExp_opA_uid94_fpDivTest_o <= $unsigned(qDivProdExp_opA_uid94_fpDivTest_a) + $unsigned(qDivProdExp_opA_uid94_fpDivTest_b); + end + end + assign qDivProdExp_opA_uid94_fpDivTest_q = qDivProdExp_opA_uid94_fpDivTest_o[8:0]; + + // redist6_qDivProdExp_opA_uid94_fpDivTest_q_4(DELAY,192) + dspba_delay_ver #( .width(9), .depth(3), .reset_kind("ASYNC") ) + redist6_qDivProdExp_opA_uid94_fpDivTest_q_4 ( .xin(qDivProdExp_opA_uid94_fpDivTest_q), .xout(redist6_qDivProdExp_opA_uid94_fpDivTest_q_4_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // qDivProdExp_uid96_fpDivTest(SUB,95)@18 + assign qDivProdExp_uid96_fpDivTest_a = {3'b000, redist6_qDivProdExp_opA_uid94_fpDivTest_q_4_q}; + assign qDivProdExp_uid96_fpDivTest_b = {{3{qDivProdExp_opBs_uid95_fpDivTest_q[8]}}, qDivProdExp_opBs_uid95_fpDivTest_q}; + assign qDivProdExp_uid96_fpDivTest_o = $signed(qDivProdExp_uid96_fpDivTest_a) - $signed(qDivProdExp_uid96_fpDivTest_b); + assign qDivProdExp_uid96_fpDivTest_q = qDivProdExp_uid96_fpDivTest_o[10:0]; + + // qDivProdLTX_opA_uid98_fpDivTest(BITSELECT,97)@18 + assign qDivProdLTX_opA_uid98_fpDivTest_in = qDivProdExp_uid96_fpDivTest_q[7:0]; + assign qDivProdLTX_opA_uid98_fpDivTest_b = qDivProdLTX_opA_uid98_fpDivTest_in[7:0]; + + // qDivProdFracHigh_uid91_fpDivTest(BITSELECT,90)@17 + assign qDivProdFracHigh_uid91_fpDivTest_in = qDivProd_uid89_fpDivTest_cma_q[47:0]; + assign qDivProdFracHigh_uid91_fpDivTest_b = qDivProdFracHigh_uid91_fpDivTest_in[47:24]; + + // qDivProdFracLow_uid92_fpDivTest(BITSELECT,91)@17 + assign qDivProdFracLow_uid92_fpDivTest_in = qDivProd_uid89_fpDivTest_cma_q[46:0]; + assign qDivProdFracLow_uid92_fpDivTest_b = qDivProdFracLow_uid92_fpDivTest_in[46:23]; + + // qDivProdFrac_uid93_fpDivTest(MUX,92)@17 + assign qDivProdFrac_uid93_fpDivTest_s = qDivProdNorm_uid90_fpDivTest_b; + always @(qDivProdFrac_uid93_fpDivTest_s or en or qDivProdFracLow_uid92_fpDivTest_b or qDivProdFracHigh_uid91_fpDivTest_b) + begin + unique case (qDivProdFrac_uid93_fpDivTest_s) + 1'b0 : qDivProdFrac_uid93_fpDivTest_q = qDivProdFracLow_uid92_fpDivTest_b; + 1'b1 : qDivProdFrac_uid93_fpDivTest_q = qDivProdFracHigh_uid91_fpDivTest_b; + default : qDivProdFrac_uid93_fpDivTest_q = 24'b0; + endcase + end + + // qDivProdFracWF_uid97_fpDivTest(BITSELECT,96)@17 + assign qDivProdFracWF_uid97_fpDivTest_b = qDivProdFrac_uid93_fpDivTest_q[23:1]; + + // redist5_qDivProdFracWF_uid97_fpDivTest_b_1(DELAY,191) + dspba_delay_ver #( .width(23), .depth(1), .reset_kind("ASYNC") ) + redist5_qDivProdFracWF_uid97_fpDivTest_b_1 ( .xin(qDivProdFracWF_uid97_fpDivTest_b), .xout(redist5_qDivProdFracWF_uid97_fpDivTest_b_1_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // qDivProdLTX_opA_uid99_fpDivTest(BITJOIN,98)@18 + assign qDivProdLTX_opA_uid99_fpDivTest_q = {qDivProdLTX_opA_uid98_fpDivTest_b, redist5_qDivProdFracWF_uid97_fpDivTest_b_1_q}; + + // qDividerProdLTX_uid101_fpDivTest(COMPARE,100)@18 + 1 + assign qDividerProdLTX_uid101_fpDivTest_a = {2'b00, qDivProdLTX_opA_uid99_fpDivTest_q}; + assign qDividerProdLTX_uid101_fpDivTest_b = {2'b00, qDivProdLTX_opB_uid100_fpDivTest_q}; + always @ (posedge clk or posedge areset) + begin + if (areset) + begin + qDividerProdLTX_uid101_fpDivTest_o <= 33'b0; + end + else if (en == 1'b1) + begin + qDividerProdLTX_uid101_fpDivTest_o <= $unsigned(qDividerProdLTX_uid101_fpDivTest_a) - $unsigned(qDividerProdLTX_uid101_fpDivTest_b); + end + end + assign qDividerProdLTX_uid101_fpDivTest_c[0] = qDividerProdLTX_uid101_fpDivTest_o[32]; + + // extraUlp_uid103_fpDivTest(LOGICAL,102)@19 + assign extraUlp_uid103_fpDivTest_q = qDividerProdLTX_uid101_fpDivTest_c & betweenFPwF_uid102_fpDivTest_b; + + // fracPostRndFT_uid104_fpDivTest(BITSELECT,103)@19 + assign fracPostRndFT_uid104_fpDivTest_b = redist8_fracPostRndF_uid80_fpDivTest_q_5_outputreg_q[23:1]; + + // fracRPreExcExt_uid105_fpDivTest(ADD,104)@19 + assign fracRPreExcExt_uid105_fpDivTest_a = {1'b0, fracPostRndFT_uid104_fpDivTest_b}; + assign fracRPreExcExt_uid105_fpDivTest_b = {23'b00000000000000000000000, extraUlp_uid103_fpDivTest_q}; + assign fracRPreExcExt_uid105_fpDivTest_o = $unsigned(fracRPreExcExt_uid105_fpDivTest_a) + $unsigned(fracRPreExcExt_uid105_fpDivTest_b); + assign fracRPreExcExt_uid105_fpDivTest_q = fracRPreExcExt_uid105_fpDivTest_o[23:0]; + + // ovfIncRnd_uid109_fpDivTest(BITSELECT,108)@19 + assign ovfIncRnd_uid109_fpDivTest_b = fracRPreExcExt_uid105_fpDivTest_q[23:23]; + + // redist3_ovfIncRnd_uid109_fpDivTest_b_1(DELAY,189) + dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") ) + redist3_ovfIncRnd_uid109_fpDivTest_b_1 ( .xin(ovfIncRnd_uid109_fpDivTest_b), .xout(redist3_ovfIncRnd_uid109_fpDivTest_b_1_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // expFracPostRndInc_uid110_fpDivTest(ADD,109)@20 + assign expFracPostRndInc_uid110_fpDivTest_a = {1'b0, redist7_expPostRndFR_uid81_fpDivTest_b_6_outputreg_q}; + assign expFracPostRndInc_uid110_fpDivTest_b = {8'b00000000, redist3_ovfIncRnd_uid109_fpDivTest_b_1_q}; + assign expFracPostRndInc_uid110_fpDivTest_o = $unsigned(expFracPostRndInc_uid110_fpDivTest_a) + $unsigned(expFracPostRndInc_uid110_fpDivTest_b); + assign expFracPostRndInc_uid110_fpDivTest_q = expFracPostRndInc_uid110_fpDivTest_o[8:0]; + + // expFracPostRndR_uid111_fpDivTest(BITSELECT,110)@20 + assign expFracPostRndR_uid111_fpDivTest_in = expFracPostRndInc_uid110_fpDivTest_q[7:0]; + assign expFracPostRndR_uid111_fpDivTest_b = expFracPostRndR_uid111_fpDivTest_in[7:0]; + + // redist7_expPostRndFR_uid81_fpDivTest_b_6_notEnable(LOGICAL,221) + assign redist7_expPostRndFR_uid81_fpDivTest_b_6_notEnable_q = ~ (en); + + // redist7_expPostRndFR_uid81_fpDivTest_b_6_nor(LOGICAL,222) + assign redist7_expPostRndFR_uid81_fpDivTest_b_6_nor_q = ~ (redist7_expPostRndFR_uid81_fpDivTest_b_6_notEnable_q | redist7_expPostRndFR_uid81_fpDivTest_b_6_sticky_ena_q); + + // redist7_expPostRndFR_uid81_fpDivTest_b_6_mem_last(CONSTANT,218) + assign redist7_expPostRndFR_uid81_fpDivTest_b_6_mem_last_q = 3'b010; + + // redist7_expPostRndFR_uid81_fpDivTest_b_6_cmp(LOGICAL,219) + assign redist7_expPostRndFR_uid81_fpDivTest_b_6_cmp_b = {1'b0, redist7_expPostRndFR_uid81_fpDivTest_b_6_rdmux_q}; + assign redist7_expPostRndFR_uid81_fpDivTest_b_6_cmp_q = redist7_expPostRndFR_uid81_fpDivTest_b_6_mem_last_q == redist7_expPostRndFR_uid81_fpDivTest_b_6_cmp_b ? 1'b1 : 1'b0; + + // redist7_expPostRndFR_uid81_fpDivTest_b_6_cmpReg(REG,220) + always @ (posedge clk or posedge areset) + begin + if (areset) + begin + redist7_expPostRndFR_uid81_fpDivTest_b_6_cmpReg_q <= 1'b0; + end + else if (en == 1'b1) + begin + redist7_expPostRndFR_uid81_fpDivTest_b_6_cmpReg_q <= redist7_expPostRndFR_uid81_fpDivTest_b_6_cmp_q; + end + end + + // redist7_expPostRndFR_uid81_fpDivTest_b_6_sticky_ena(REG,223) + always @ (posedge clk or posedge areset) + begin + if (areset) + begin + redist7_expPostRndFR_uid81_fpDivTest_b_6_sticky_ena_q <= 1'b0; + end + else if (redist7_expPostRndFR_uid81_fpDivTest_b_6_nor_q == 1'b1) + begin + redist7_expPostRndFR_uid81_fpDivTest_b_6_sticky_ena_q <= redist7_expPostRndFR_uid81_fpDivTest_b_6_cmpReg_q; + end + end + + // redist7_expPostRndFR_uid81_fpDivTest_b_6_enaAnd(LOGICAL,224) + assign redist7_expPostRndFR_uid81_fpDivTest_b_6_enaAnd_q = redist7_expPostRndFR_uid81_fpDivTest_b_6_sticky_ena_q & en; + + // redist7_expPostRndFR_uid81_fpDivTest_b_6_rdcnt(COUNTER,215) + // low=0, high=3, step=1, init=0 + always @ (posedge clk or posedge areset) + begin + if (areset) + begin + redist7_expPostRndFR_uid81_fpDivTest_b_6_rdcnt_i <= 2'd0; + end + else if (en == 1'b1) + begin + redist7_expPostRndFR_uid81_fpDivTest_b_6_rdcnt_i <= $unsigned(redist7_expPostRndFR_uid81_fpDivTest_b_6_rdcnt_i) + $unsigned(2'd1); + end + end + assign redist7_expPostRndFR_uid81_fpDivTest_b_6_rdcnt_q = redist7_expPostRndFR_uid81_fpDivTest_b_6_rdcnt_i[1:0]; + + // redist7_expPostRndFR_uid81_fpDivTest_b_6_rdmux(MUX,216) + assign redist7_expPostRndFR_uid81_fpDivTest_b_6_rdmux_s = en; + always @(redist7_expPostRndFR_uid81_fpDivTest_b_6_rdmux_s or redist7_expPostRndFR_uid81_fpDivTest_b_6_wraddr_q or redist7_expPostRndFR_uid81_fpDivTest_b_6_rdcnt_q) + begin + unique case (redist7_expPostRndFR_uid81_fpDivTest_b_6_rdmux_s) + 1'b0 : redist7_expPostRndFR_uid81_fpDivTest_b_6_rdmux_q = redist7_expPostRndFR_uid81_fpDivTest_b_6_wraddr_q; + 1'b1 : redist7_expPostRndFR_uid81_fpDivTest_b_6_rdmux_q = redist7_expPostRndFR_uid81_fpDivTest_b_6_rdcnt_q; + default : redist7_expPostRndFR_uid81_fpDivTest_b_6_rdmux_q = 2'b0; + endcase + end + + // redist7_expPostRndFR_uid81_fpDivTest_b_6_wraddr(REG,217) + always @ (posedge clk or posedge areset) + begin + if (areset) + begin + redist7_expPostRndFR_uid81_fpDivTest_b_6_wraddr_q <= 2'b11; + end + else + begin + redist7_expPostRndFR_uid81_fpDivTest_b_6_wraddr_q <= redist7_expPostRndFR_uid81_fpDivTest_b_6_rdmux_q; + end + end + + // redist7_expPostRndFR_uid81_fpDivTest_b_6_mem(DUALMEM,214) + assign redist7_expPostRndFR_uid81_fpDivTest_b_6_mem_ia = expPostRndFR_uid81_fpDivTest_b; + assign redist7_expPostRndFR_uid81_fpDivTest_b_6_mem_aa = redist7_expPostRndFR_uid81_fpDivTest_b_6_wraddr_q; + assign redist7_expPostRndFR_uid81_fpDivTest_b_6_mem_ab = redist7_expPostRndFR_uid81_fpDivTest_b_6_rdmux_q; + assign redist7_expPostRndFR_uid81_fpDivTest_b_6_mem_reset0 = areset; + altera_syncram #( + .ram_block_type("MLAB"), + .operation_mode("DUAL_PORT"), + .width_a(8), + .widthad_a(2), + .numwords_a(4), + .width_b(8), + .widthad_b(2), + .numwords_b(4), + .lpm_type("altera_syncram"), + .width_byteena_a(1), + .address_reg_b("CLOCK0"), + .indata_reg_b("CLOCK0"), + .rdcontrol_reg_b("CLOCK0"), + .byteena_reg_b("CLOCK0"), + .outdata_reg_b("CLOCK1"), + .outdata_aclr_b("CLEAR1"), + .clock_enable_input_a("NORMAL"), + .clock_enable_input_b("NORMAL"), + .clock_enable_output_b("NORMAL"), + .read_during_write_mode_mixed_ports("DONT_CARE"), + .power_up_uninitialized("TRUE"), + .intended_device_family("Arria 10") + ) redist7_expPostRndFR_uid81_fpDivTest_b_6_mem_dmem ( + .clocken1(redist7_expPostRndFR_uid81_fpDivTest_b_6_enaAnd_q[0]), + .clocken0(VCC_q[0]), + .clock0(clk), + .aclr1(redist7_expPostRndFR_uid81_fpDivTest_b_6_mem_reset0), + .clock1(clk), + .address_a(redist7_expPostRndFR_uid81_fpDivTest_b_6_mem_aa), + .data_a(redist7_expPostRndFR_uid81_fpDivTest_b_6_mem_ia), + .wren_a(en[0]), + .address_b(redist7_expPostRndFR_uid81_fpDivTest_b_6_mem_ab), + .q_b(redist7_expPostRndFR_uid81_fpDivTest_b_6_mem_iq), + .wren_b(), + .rden_a(), + .rden_b(), + .data_b(), + .clocken2(), + .clocken3(), + .aclr0(), + .addressstall_a(), + .addressstall_b(), + .byteena_a(), + .byteena_b(), + .eccencbypass(), + .eccencparity(), + .sclr(), + .address2_a(), + .address2_b(), + .q_a(), + .eccstatus() + ); + assign redist7_expPostRndFR_uid81_fpDivTest_b_6_mem_q = redist7_expPostRndFR_uid81_fpDivTest_b_6_mem_iq[7:0]; + + // redist7_expPostRndFR_uid81_fpDivTest_b_6_outputreg(DELAY,213) + dspba_delay_ver #( .width(8), .depth(1), .reset_kind("ASYNC") ) + redist7_expPostRndFR_uid81_fpDivTest_b_6_outputreg ( .xin(redist7_expPostRndFR_uid81_fpDivTest_b_6_mem_q), .xout(redist7_expPostRndFR_uid81_fpDivTest_b_6_outputreg_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // redist4_extraUlp_uid103_fpDivTest_q_1(DELAY,190) + dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") ) + redist4_extraUlp_uid103_fpDivTest_q_1 ( .xin(extraUlp_uid103_fpDivTest_q), .xout(redist4_extraUlp_uid103_fpDivTest_q_1_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // expRPreExc_uid112_fpDivTest(MUX,111)@20 + assign expRPreExc_uid112_fpDivTest_s = redist4_extraUlp_uid103_fpDivTest_q_1_q; + always @(expRPreExc_uid112_fpDivTest_s or en or redist7_expPostRndFR_uid81_fpDivTest_b_6_outputreg_q or expFracPostRndR_uid111_fpDivTest_b) + begin + unique case (expRPreExc_uid112_fpDivTest_s) + 1'b0 : expRPreExc_uid112_fpDivTest_q = redist7_expPostRndFR_uid81_fpDivTest_b_6_outputreg_q; + 1'b1 : expRPreExc_uid112_fpDivTest_q = expFracPostRndR_uid111_fpDivTest_b; + default : expRPreExc_uid112_fpDivTest_q = 8'b0; + endcase + end + + // invExpXIsMax_uid43_fpDivTest(LOGICAL,42)@14 + assign invExpXIsMax_uid43_fpDivTest_q = ~ (expXIsMax_uid38_fpDivTest_q); + + // InvExpXIsZero_uid44_fpDivTest(LOGICAL,43)@14 + assign InvExpXIsZero_uid44_fpDivTest_q = ~ (excZ_y_uid37_fpDivTest_q); + + // excR_y_uid45_fpDivTest(LOGICAL,44)@14 + assign excR_y_uid45_fpDivTest_q = InvExpXIsZero_uid44_fpDivTest_q & invExpXIsMax_uid43_fpDivTest_q; + + // excXIYR_uid127_fpDivTest(LOGICAL,126)@14 + assign excXIYR_uid127_fpDivTest_q = excI_x_uid27_fpDivTest_q & excR_y_uid45_fpDivTest_q; + + // excXIYZ_uid126_fpDivTest(LOGICAL,125)@14 + assign excXIYZ_uid126_fpDivTest_q = excI_x_uid27_fpDivTest_q & excZ_y_uid37_fpDivTest_q; + + // expRExt_uid114_fpDivTest(BITSELECT,113)@14 + assign expRExt_uid114_fpDivTest_b = expFracPostRnd_uid76_fpDivTest_q[35:25]; + + // expOvf_uid118_fpDivTest(COMPARE,117)@14 + assign expOvf_uid118_fpDivTest_a = {{2{expRExt_uid114_fpDivTest_b[10]}}, expRExt_uid114_fpDivTest_b}; + assign expOvf_uid118_fpDivTest_b = {5'b00000, cstAllOWE_uid18_fpDivTest_q}; + assign expOvf_uid118_fpDivTest_o = $signed(expOvf_uid118_fpDivTest_a) - $signed(expOvf_uid118_fpDivTest_b); + assign expOvf_uid118_fpDivTest_n[0] = ~ (expOvf_uid118_fpDivTest_o[12]); + + // invExpXIsMax_uid29_fpDivTest(LOGICAL,28)@14 + assign invExpXIsMax_uid29_fpDivTest_q = ~ (expXIsMax_uid24_fpDivTest_q); + + // InvExpXIsZero_uid30_fpDivTest(LOGICAL,29)@14 + assign InvExpXIsZero_uid30_fpDivTest_q = ~ (excZ_x_uid23_fpDivTest_q); + + // excR_x_uid31_fpDivTest(LOGICAL,30)@14 + assign excR_x_uid31_fpDivTest_q = InvExpXIsZero_uid30_fpDivTest_q & invExpXIsMax_uid29_fpDivTest_q; + + // excXRYROvf_uid125_fpDivTest(LOGICAL,124)@14 + assign excXRYROvf_uid125_fpDivTest_q = excR_x_uid31_fpDivTest_q & excR_y_uid45_fpDivTest_q & expOvf_uid118_fpDivTest_n; + + // excXRYZ_uid124_fpDivTest(LOGICAL,123)@14 + assign excXRYZ_uid124_fpDivTest_q = excR_x_uid31_fpDivTest_q & excZ_y_uid37_fpDivTest_q; + + // excRInf_uid128_fpDivTest(LOGICAL,127)@14 + 1 + assign excRInf_uid128_fpDivTest_qi = excXRYZ_uid124_fpDivTest_q | excXRYROvf_uid125_fpDivTest_q | excXIYZ_uid126_fpDivTest_q | excXIYR_uid127_fpDivTest_q; + dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") ) + excRInf_uid128_fpDivTest_delay ( .xin(excRInf_uid128_fpDivTest_qi), .xout(excRInf_uid128_fpDivTest_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // xRegOrZero_uid121_fpDivTest(LOGICAL,120)@14 + assign xRegOrZero_uid121_fpDivTest_q = excR_x_uid31_fpDivTest_q | excZ_x_uid23_fpDivTest_q; + + // regOrZeroOverInf_uid122_fpDivTest(LOGICAL,121)@14 + 1 + assign regOrZeroOverInf_uid122_fpDivTest_qi = xRegOrZero_uid121_fpDivTest_q & excI_y_uid41_fpDivTest_q; + dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") ) + regOrZeroOverInf_uid122_fpDivTest_delay ( .xin(regOrZeroOverInf_uid122_fpDivTest_qi), .xout(regOrZeroOverInf_uid122_fpDivTest_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // expUdf_uid115_fpDivTest(COMPARE,114)@14 + assign expUdf_uid115_fpDivTest_a = {12'b000000000000, GND_q}; + assign expUdf_uid115_fpDivTest_b = {{2{expRExt_uid114_fpDivTest_b[10]}}, expRExt_uid114_fpDivTest_b}; + assign expUdf_uid115_fpDivTest_o = $signed(expUdf_uid115_fpDivTest_a) - $signed(expUdf_uid115_fpDivTest_b); + assign expUdf_uid115_fpDivTest_n[0] = ~ (expUdf_uid115_fpDivTest_o[12]); + + // regOverRegWithUf_uid120_fpDivTest(LOGICAL,119)@14 + 1 + assign regOverRegWithUf_uid120_fpDivTest_qi = expUdf_uid115_fpDivTest_n & excR_x_uid31_fpDivTest_q & excR_y_uid45_fpDivTest_q; + dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") ) + regOverRegWithUf_uid120_fpDivTest_delay ( .xin(regOverRegWithUf_uid120_fpDivTest_qi), .xout(regOverRegWithUf_uid120_fpDivTest_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // zeroOverReg_uid119_fpDivTest(LOGICAL,118)@14 + 1 + assign zeroOverReg_uid119_fpDivTest_qi = excZ_x_uid23_fpDivTest_q & excR_y_uid45_fpDivTest_q; + dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") ) + zeroOverReg_uid119_fpDivTest_delay ( .xin(zeroOverReg_uid119_fpDivTest_qi), .xout(zeroOverReg_uid119_fpDivTest_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // excRZero_uid123_fpDivTest(LOGICAL,122)@15 + assign excRZero_uid123_fpDivTest_q = zeroOverReg_uid119_fpDivTest_q | regOverRegWithUf_uid120_fpDivTest_q | regOrZeroOverInf_uid122_fpDivTest_q; + + // concExc_uid132_fpDivTest(BITJOIN,131)@15 + assign concExc_uid132_fpDivTest_q = {excRNaN_uid131_fpDivTest_q, excRInf_uid128_fpDivTest_q, excRZero_uid123_fpDivTest_q}; + + // excREnc_uid133_fpDivTest(LOOKUP,132)@15 + 1 + always @ (posedge clk or posedge areset) + begin + if (areset) + begin + excREnc_uid133_fpDivTest_q <= 2'b01; + end + else if (en == 1'b1) + begin + unique case (concExc_uid132_fpDivTest_q) + 3'b000 : excREnc_uid133_fpDivTest_q <= 2'b01; + 3'b001 : excREnc_uid133_fpDivTest_q <= 2'b00; + 3'b010 : excREnc_uid133_fpDivTest_q <= 2'b10; + 3'b011 : excREnc_uid133_fpDivTest_q <= 2'b00; + 3'b100 : excREnc_uid133_fpDivTest_q <= 2'b11; + 3'b101 : excREnc_uid133_fpDivTest_q <= 2'b00; + 3'b110 : excREnc_uid133_fpDivTest_q <= 2'b00; + 3'b111 : excREnc_uid133_fpDivTest_q <= 2'b00; + default : begin + // unreachable + excREnc_uid133_fpDivTest_q <= 2'bxx; + end + endcase + end + end + + // redist2_excREnc_uid133_fpDivTest_q_5(DELAY,188) + dspba_delay_ver #( .width(2), .depth(4), .reset_kind("ASYNC") ) + redist2_excREnc_uid133_fpDivTest_q_5 ( .xin(excREnc_uid133_fpDivTest_q), .xout(redist2_excREnc_uid133_fpDivTest_q_5_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // expRPostExc_uid141_fpDivTest(MUX,140)@20 + assign expRPostExc_uid141_fpDivTest_s = redist2_excREnc_uid133_fpDivTest_q_5_q; + always @(expRPostExc_uid141_fpDivTest_s or en or cstAllZWE_uid20_fpDivTest_q or expRPreExc_uid112_fpDivTest_q or cstAllOWE_uid18_fpDivTest_q) + begin + unique case (expRPostExc_uid141_fpDivTest_s) + 2'b00 : expRPostExc_uid141_fpDivTest_q = cstAllZWE_uid20_fpDivTest_q; + 2'b01 : expRPostExc_uid141_fpDivTest_q = expRPreExc_uid112_fpDivTest_q; + 2'b10 : expRPostExc_uid141_fpDivTest_q = cstAllOWE_uid18_fpDivTest_q; + 2'b11 : expRPostExc_uid141_fpDivTest_q = cstAllOWE_uid18_fpDivTest_q; + default : expRPostExc_uid141_fpDivTest_q = 8'b0; + endcase + end + + // oneFracRPostExc2_uid134_fpDivTest(CONSTANT,133) + assign oneFracRPostExc2_uid134_fpDivTest_q = 23'b00000000000000000000001; + + // fracPostRndFPostUlp_uid106_fpDivTest(BITSELECT,105)@19 + assign fracPostRndFPostUlp_uid106_fpDivTest_in = fracRPreExcExt_uid105_fpDivTest_q[22:0]; + assign fracPostRndFPostUlp_uid106_fpDivTest_b = fracPostRndFPostUlp_uid106_fpDivTest_in[22:0]; + + // fracRPreExc_uid107_fpDivTest(MUX,106)@19 + 1 + assign fracRPreExc_uid107_fpDivTest_s = extraUlp_uid103_fpDivTest_q; + always @ (posedge clk or posedge areset) + begin + if (areset) + begin + fracRPreExc_uid107_fpDivTest_q <= 23'b0; + end + else if (en == 1'b1) + begin + unique case (fracRPreExc_uid107_fpDivTest_s) + 1'b0 : fracRPreExc_uid107_fpDivTest_q <= fracPostRndFT_uid104_fpDivTest_b; + 1'b1 : fracRPreExc_uid107_fpDivTest_q <= fracPostRndFPostUlp_uid106_fpDivTest_b; + default : fracRPreExc_uid107_fpDivTest_q <= 23'b0; + endcase + end + end + + // fracRPostExc_uid137_fpDivTest(MUX,136)@20 + assign fracRPostExc_uid137_fpDivTest_s = redist2_excREnc_uid133_fpDivTest_q_5_q; + always @(fracRPostExc_uid137_fpDivTest_s or en or paddingY_uid15_fpDivTest_q or fracRPreExc_uid107_fpDivTest_q or oneFracRPostExc2_uid134_fpDivTest_q) + begin + unique case (fracRPostExc_uid137_fpDivTest_s) + 2'b00 : fracRPostExc_uid137_fpDivTest_q = paddingY_uid15_fpDivTest_q; + 2'b01 : fracRPostExc_uid137_fpDivTest_q = fracRPreExc_uid107_fpDivTest_q; + 2'b10 : fracRPostExc_uid137_fpDivTest_q = paddingY_uid15_fpDivTest_q; + 2'b11 : fracRPostExc_uid137_fpDivTest_q = oneFracRPostExc2_uid134_fpDivTest_q; + default : fracRPostExc_uid137_fpDivTest_q = 23'b0; + endcase + end + + // divR_uid144_fpDivTest(BITJOIN,143)@20 + assign divR_uid144_fpDivTest_q = {redist1_sRPostExc_uid143_fpDivTest_q_5_q, expRPostExc_uid141_fpDivTest_q, fracRPostExc_uid137_fpDivTest_q}; + + // xOut(GPOUT,4)@20 + assign q = divR_uid144_fpDivTest_q; + +endmodule diff --git a/hw/rtl/fp_cores/altera/arria10/acl_fdiv_memoryC0_uid146_invTables_lutmem.hex b/hw/rtl/fp_cores/altera/arria10/acl_fdiv_memoryC0_uid146_invTables_lutmem.hex new file mode 100644 index 00000000..915d30cb --- /dev/null +++ b/hw/rtl/fp_cores/altera/arria10/acl_fdiv_memoryC0_uid146_invTables_lutmem.hex @@ -0,0 +1,514 @@ +:020000040000FA +:0400000040000004B8 +:040001003FE00FFCD1 +:040002003FC03FC4F8 +:040003003FA08F2D5E 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+:0201F600020FF6 +:0201F700020EF6 +:0201F800020CF7 +:0201F900020CF6 +:0201FA00020AF7 +:0201FB000207F9 +:0201FC000206F9 +:0201FD000205F9 +:0201FE000204F9 +:0201FF0001FFFE +:00000001ff diff --git a/hw/rtl/fp_cores/altera/arria10/acl_fmadd.sv b/hw/rtl/fp_cores/altera/arria10/acl_fmadd.sv new file mode 100644 index 00000000..9ebb18ab --- /dev/null +++ b/hw/rtl/fp_cores/altera/arria10/acl_fmadd.sv @@ -0,0 +1,74 @@ +// ------------------------------------------------------------------------- +// High Level Design Compiler for Intel(R) FPGAs Version 17.1 (Release Build #273) +// Quartus Prime development tool and MATLAB/Simulink Interface +// +// Legal Notice: Copyright 2017 Intel Corporation. All rights reserved. +// Your use of Intel Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly +// subject to the terms and conditions of the Intel FPGA Software License +// Agreement, Intel MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for +// the sole purpose of programming logic devices manufactured by Intel +// and sold by Intel or its authorized distributors. Please refer to the +// applicable agreement for further details. +// --------------------------------------------------------------------------- + +// SystemVerilog created from acl_fmadd +// SystemVerilog created on Sun Dec 27 09:47:20 2020 + + +(* altera_attribute = "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410; -name MESSAGE_DISABLE 113007; -name MESSAGE_DISABLE 10958" *) +module acl_fmadd ( + input wire [31:0] a, + input wire [31:0] b, + input wire [31:0] c, + input wire [0:0] en, + output wire [31:0] q, + input wire clk, + input wire areset + ); + + wire [31:0] fpMultAddTest_impl_ax0; + wire [31:0] fpMultAddTest_impl_ay0; + wire [31:0] fpMultAddTest_impl_az0; + wire [31:0] fpMultAddTest_impl_q0; + wire fpMultAddTest_impl_reset0; + wire fpMultAddTest_impl_fpMultAddTest_impl_ena0; + + + // fpMultAddTest_impl(FPCOLUMN,5)@0 + // out q0@4 + assign fpMultAddTest_impl_ax0 = c; + assign fpMultAddTest_impl_ay0 = b; + assign fpMultAddTest_impl_az0 = a; + assign fpMultAddTest_impl_reset0 = areset; + assign fpMultAddTest_impl_fpMultAddTest_impl_ena0 = en[0]; + twentynm_fp_mac #( + .operation_mode("sp_mult_add"), + .use_chainin("false"), + .ax_clock("0"), + .ay_clock("0"), + .az_clock("0"), + .mult_pipeline_clock("0"), + .adder_input_clock("0"), + .ax_chainin_pl_clock("0"), + .output_clock("0") + ) fpMultAddTest_impl_DSP0 ( + .aclr({ fpMultAddTest_impl_reset0, fpMultAddTest_impl_reset0 }), + .clk({1'b0,1'b0,clk}), + .ena({ 1'b0, 1'b0, fpMultAddTest_impl_fpMultAddTest_impl_ena0 }), + .ax(fpMultAddTest_impl_ax0), + .ay(fpMultAddTest_impl_ay0), + .az(fpMultAddTest_impl_az0), + .resulta(fpMultAddTest_impl_q0), + .accumulate(), + .chainin(), + .chainout() + ); + + // xOut(GPOUT,4)@4 + assign q = fpMultAddTest_impl_q0; + +endmodule diff --git a/hw/rtl/fp_cores/altera/arria10/acl_fmsub.sv b/hw/rtl/fp_cores/altera/arria10/acl_fmsub.sv new file mode 100644 index 00000000..48406b3b --- /dev/null +++ b/hw/rtl/fp_cores/altera/arria10/acl_fmsub.sv @@ -0,0 +1,75 @@ +// ------------------------------------------------------------------------- +// High Level Design Compiler for Intel(R) FPGAs Version 17.1 (Release Build #273) +// Quartus Prime development tool and MATLAB/Simulink Interface +// +// Legal Notice: Copyright 2017 Intel Corporation. All rights reserved. +// Your use of Intel Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly +// subject to the terms and conditions of the Intel FPGA Software License +// Agreement, Intel MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for +// the sole purpose of programming logic devices manufactured by Intel +// and sold by Intel or its authorized distributors. Please refer to the +// applicable agreement for further details. +// --------------------------------------------------------------------------- + +// SystemVerilog created from acl_fmsub +// SystemVerilog created on Sun Dec 27 07:07:02 2020 + + +(* altera_attribute = "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410; -name MESSAGE_DISABLE 113007; -name MESSAGE_DISABLE 10958" *) +module acl_fmsub ( + input wire [31:0] a, + input wire [31:0] b, + input wire [31:0] c, + input wire [0:0] en, + output wire [31:0] q, + input wire clk, + input wire areset + ); + + wire [31:0] fpMultAddTest_impl_ax0; + wire [31:0] fpMultAddTest_impl_ay0; + wire [31:0] fpMultAddTest_impl_az0; + wire [31:0] fpMultAddTest_impl_q0; + wire fpMultAddTest_impl_reset0; + wire fpMultAddTest_impl_fpMultAddTest_impl_ena0; + + + // fpMultAddTest_impl(FPCOLUMN,5)@0 + // out q0@4 + assign fpMultAddTest_impl_ax0 = c; + assign fpMultAddTest_impl_ay0 = b; + assign fpMultAddTest_impl_az0 = a; + assign fpMultAddTest_impl_reset0 = areset; + assign fpMultAddTest_impl_fpMultAddTest_impl_ena0 = en[0]; + twentynm_fp_mac #( + .operation_mode("sp_mult_add"), + .adder_subtract("true"), + .use_chainin("false"), + .ax_clock("0"), + .ay_clock("0"), + .az_clock("0"), + .mult_pipeline_clock("0"), + .adder_input_clock("0"), + .ax_chainin_pl_clock("0"), + .output_clock("0") + ) fpMultAddTest_impl_DSP0 ( + .aclr({ fpMultAddTest_impl_reset0, fpMultAddTest_impl_reset0 }), + .clk({1'b0,1'b0,clk}), + .ena({ 1'b0, 1'b0, fpMultAddTest_impl_fpMultAddTest_impl_ena0 }), + .ax(fpMultAddTest_impl_ax0), + .ay(fpMultAddTest_impl_ay0), + .az(fpMultAddTest_impl_az0), + .resulta(fpMultAddTest_impl_q0), + .accumulate(), + .chainin(), + .chainout() + ); + + // xOut(GPOUT,4)@4 + assign q = fpMultAddTest_impl_q0; + +endmodule diff --git a/hw/rtl/fp_cores/altera/arria10/acl_fmul.sv b/hw/rtl/fp_cores/altera/arria10/acl_fmul.sv new file mode 100644 index 00000000..46615d62 --- /dev/null +++ b/hw/rtl/fp_cores/altera/arria10/acl_fmul.sv @@ -0,0 +1,67 @@ +// ------------------------------------------------------------------------- +// High Level Design Compiler for Intel(R) FPGAs Version 17.1 (Release Build #273) +// Quartus Prime development tool and MATLAB/Simulink Interface +// +// Legal Notice: Copyright 2017 Intel Corporation. All rights reserved. +// Your use of Intel Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly +// subject to the terms and conditions of the Intel FPGA Software License +// Agreement, Intel MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for +// the sole purpose of programming logic devices manufactured by Intel +// and sold by Intel or its authorized distributors. Please refer to the +// applicable agreement for further details. +// --------------------------------------------------------------------------- + +// SystemVerilog created from acl_fmul +// SystemVerilog created on Sun Dec 27 09:47:20 2020 + + +(* altera_attribute = "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410; -name MESSAGE_DISABLE 113007; -name MESSAGE_DISABLE 10958" *) +module acl_fmul ( + input wire [31:0] a, + input wire [31:0] b, + input wire [0:0] en, + output wire [31:0] q, + input wire clk, + input wire areset + ); + + wire [31:0] fpMulTest_impl_ay0; + wire [31:0] fpMulTest_impl_az0; + wire [31:0] fpMulTest_impl_q0; + wire fpMulTest_impl_reset0; + wire fpMulTest_impl_fpMulTest_impl_ena0; + + + // fpMulTest_impl(FPCOLUMN,5)@0 + // out q0@3 + assign fpMulTest_impl_ay0 = b; + assign fpMulTest_impl_az0 = a; + assign fpMulTest_impl_reset0 = areset; + assign fpMulTest_impl_fpMulTest_impl_ena0 = en[0]; + twentynm_fp_mac #( + .operation_mode("sp_mult"), + .ay_clock("0"), + .az_clock("0"), + .mult_pipeline_clock("0"), + .output_clock("0") + ) fpMulTest_impl_DSP0 ( + .aclr({ fpMulTest_impl_reset0, fpMulTest_impl_reset0 }), + .clk({1'b0,1'b0,clk}), + .ena({ 1'b0, 1'b0, fpMulTest_impl_fpMulTest_impl_ena0 }), + .ay(fpMulTest_impl_ay0), + .az(fpMulTest_impl_az0), + .resulta(fpMulTest_impl_q0), + .accumulate(), + .ax(), + .chainin(), + .chainout() + ); + + // xOut(GPOUT,4)@3 + assign q = fpMulTest_impl_q0; + +endmodule diff --git a/hw/rtl/fp_cores/altera/arria10/acl_fsqrt.sv b/hw/rtl/fp_cores/altera/arria10/acl_fsqrt.sv new file mode 100644 index 00000000..e0c54e61 --- /dev/null +++ b/hw/rtl/fp_cores/altera/arria10/acl_fsqrt.sv @@ -0,0 +1,1491 @@ +// ------------------------------------------------------------------------- +// High Level Design Compiler for Intel(R) FPGAs Version 17.1 (Release Build #273) +// Quartus Prime development tool and MATLAB/Simulink Interface +// +// Legal Notice: Copyright 2017 Intel Corporation. All rights reserved. +// Your use of Intel Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly +// subject to the terms and conditions of the Intel FPGA Software License +// Agreement, Intel MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for +// the sole purpose of programming logic devices manufactured by Intel +// and sold by Intel or its authorized distributors. Please refer to the +// applicable agreement for further details. +// --------------------------------------------------------------------------- + +// SystemVerilog created from acl_fsqrt +// SystemVerilog created on Sun Dec 27 09:47:21 2020 + + +(* altera_attribute = "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410; -name MESSAGE_DISABLE 113007; -name MESSAGE_DISABLE 10958" *) +module acl_fsqrt ( + input wire [31:0] a, + input wire [0:0] en, + output wire [31:0] q, + input wire clk, + input wire areset + ); + + wire [0:0] GND_q; + wire [0:0] VCC_q; + wire [7:0] expX_uid6_fpSqrtTest_b; + wire [0:0] signX_uid7_fpSqrtTest_b; + wire [7:0] cstAllOWE_uid8_fpSqrtTest_q; + wire [22:0] cstZeroWF_uid9_fpSqrtTest_q; + wire [7:0] cstAllZWE_uid10_fpSqrtTest_q; + wire [22:0] frac_x_uid12_fpSqrtTest_b; + wire [0:0] excZ_x_uid13_fpSqrtTest_qi; + reg [0:0] excZ_x_uid13_fpSqrtTest_q; + wire [0:0] expXIsMax_uid14_fpSqrtTest_qi; + reg [0:0] expXIsMax_uid14_fpSqrtTest_q; + wire [0:0] fracXIsZero_uid15_fpSqrtTest_qi; + reg [0:0] fracXIsZero_uid15_fpSqrtTest_q; + wire [0:0] fracXIsNotZero_uid16_fpSqrtTest_q; + wire [0:0] excI_x_uid17_fpSqrtTest_q; + wire [0:0] excN_x_uid18_fpSqrtTest_q; + wire [0:0] invExpXIsMax_uid19_fpSqrtTest_q; + wire [0:0] InvExpXIsZero_uid20_fpSqrtTest_q; + wire [0:0] excR_x_uid21_fpSqrtTest_q; + wire [7:0] sBias_uid22_fpSqrtTest_q; + wire [8:0] expEvenSig_uid24_fpSqrtTest_a; + wire [8:0] expEvenSig_uid24_fpSqrtTest_b; + logic [8:0] expEvenSig_uid24_fpSqrtTest_o; + wire [8:0] expEvenSig_uid24_fpSqrtTest_q; + wire [7:0] expREven_uid25_fpSqrtTest_b; + wire [7:0] sBiasM1_uid26_fpSqrtTest_q; + wire [8:0] expOddSig_uid27_fpSqrtTest_a; + wire [8:0] expOddSig_uid27_fpSqrtTest_b; + logic [8:0] expOddSig_uid27_fpSqrtTest_o; + wire [8:0] expOddSig_uid27_fpSqrtTest_q; + wire [7:0] expROdd_uid28_fpSqrtTest_b; + wire [0:0] expX0PS_uid29_fpSqrtTest_in; + wire [0:0] expX0PS_uid29_fpSqrtTest_b; + wire [0:0] expOddSelect_uid30_fpSqrtTest_q; + wire [0:0] expRMux_uid31_fpSqrtTest_s; + reg [7:0] expRMux_uid31_fpSqrtTest_q; + wire [23:0] addrFull_uid33_fpSqrtTest_q; + wire [7:0] yAddr_uid35_fpSqrtTest_b; + wire [15:0] yForPe_uid36_fpSqrtTest_in; + wire [15:0] yForPe_uid36_fpSqrtTest_b; + wire [30:0] expIncPEOnly_uid38_fpSqrtTest_in; + wire [0:0] expIncPEOnly_uid38_fpSqrtTest_b; + wire [28:0] fracRPreCR_uid39_fpSqrtTest_in; + wire [23:0] fracRPreCR_uid39_fpSqrtTest_b; + wire [24:0] fracPaddingOne_uid41_fpSqrtTest_q; + wire [23:0] oFracX_uid44_fpSqrtTest_q; + wire [24:0] oFracXZ_mergedSignalTM_uid47_fpSqrtTest_q; + wire [24:0] oFracXSignExt_mergedSignalTM_uid52_fpSqrtTest_q; + wire [0:0] normalizedXForComp_uid54_fpSqrtTest_s; + reg [24:0] normalizedXForComp_uid54_fpSqrtTest_q; + wire [24:0] paddingY_uid55_fpSqrtTest_q; + wire [49:0] updatedY_uid56_fpSqrtTest_q; + wire [51:0] squaredResultGTEIn_uid55_fpSqrtTest_a; + wire [51:0] squaredResultGTEIn_uid55_fpSqrtTest_b; + logic [51:0] squaredResultGTEIn_uid55_fpSqrtTest_o; + wire [0:0] squaredResultGTEIn_uid55_fpSqrtTest_n; + wire [0:0] pLTOne_uid58_fpSqrtTest_q; + wire [24:0] fxpSqrtResPostUpdateE_uid60_fpSqrtTest_a; + wire [24:0] fxpSqrtResPostUpdateE_uid60_fpSqrtTest_b; + logic [24:0] fxpSqrtResPostUpdateE_uid60_fpSqrtTest_o; + wire [24:0] fxpSqrtResPostUpdateE_uid60_fpSqrtTest_q; + wire [0:0] fracPENotOne_uid62_fpSqrtTest_q; + wire [0:0] fracPENotOneAndCRRoundsExp_uid63_fpSqrtTest_q; + wire [0:0] expInc_uid64_fpSqrtTest_qi; + reg [0:0] expInc_uid64_fpSqrtTest_q; + wire [8:0] expR_uid66_fpSqrtTest_a; + wire [8:0] expR_uid66_fpSqrtTest_b; + logic [8:0] expR_uid66_fpSqrtTest_o; + wire [8:0] expR_uid66_fpSqrtTest_q; + wire [0:0] invSignX_uid67_fpSqrtTest_q; + wire [0:0] inInfAndNotNeg_uid68_fpSqrtTest_q; + wire [0:0] minReg_uid69_fpSqrtTest_q; + wire [0:0] minInf_uid70_fpSqrtTest_q; + wire [0:0] excRNaN_uid71_fpSqrtTest_q; + wire [2:0] excConc_uid72_fpSqrtTest_q; + wire [3:0] fracSelIn_uid73_fpSqrtTest_q; + reg [1:0] fracSel_uid74_fpSqrtTest_q; + wire [7:0] expRR_uid77_fpSqrtTest_in; + wire [7:0] expRR_uid77_fpSqrtTest_b; + wire [1:0] expRPostExc_uid79_fpSqrtTest_s; + reg [7:0] expRPostExc_uid79_fpSqrtTest_q; + wire [22:0] fracNaN_uid80_fpSqrtTest_q; + wire [1:0] fracRPostExc_uid84_fpSqrtTest_s; + reg [22:0] fracRPostExc_uid84_fpSqrtTest_q; + wire [0:0] negZero_uid85_fpSqrtTest_qi; + reg [0:0] negZero_uid85_fpSqrtTest_q; + wire [31:0] RSqrt_uid86_fpSqrtTest_q; + wire [11:0] yT1_uid100_invPolyEval_b; + wire [0:0] lowRangeB_uid102_invPolyEval_in; + wire [0:0] lowRangeB_uid102_invPolyEval_b; + wire [11:0] highBBits_uid103_invPolyEval_b; + wire [21:0] s1sumAHighB_uid104_invPolyEval_a; + wire [21:0] s1sumAHighB_uid104_invPolyEval_b; + logic [21:0] s1sumAHighB_uid104_invPolyEval_o; + wire [21:0] s1sumAHighB_uid104_invPolyEval_q; + wire [22:0] s1_uid105_invPolyEval_q; + wire [1:0] lowRangeB_uid108_invPolyEval_in; + wire [1:0] lowRangeB_uid108_invPolyEval_b; + wire [21:0] highBBits_uid109_invPolyEval_b; + wire [29:0] s2sumAHighB_uid110_invPolyEval_a; + wire [29:0] s2sumAHighB_uid110_invPolyEval_b; + logic [29:0] s2sumAHighB_uid110_invPolyEval_o; + wire [29:0] s2sumAHighB_uid110_invPolyEval_q; + wire [31:0] s2_uid111_invPolyEval_q; + wire [12:0] osig_uid114_pT1_uid101_invPolyEval_b; + wire [23:0] osig_uid117_pT2_uid107_invPolyEval_b; + wire memoryC0_uid88_sqrtTables_lutmem_reset0; + wire [28:0] memoryC0_uid88_sqrtTables_lutmem_ia; + wire [7:0] memoryC0_uid88_sqrtTables_lutmem_aa; + wire [7:0] memoryC0_uid88_sqrtTables_lutmem_ab; + wire [28:0] memoryC0_uid88_sqrtTables_lutmem_ir; + wire [28:0] memoryC0_uid88_sqrtTables_lutmem_r; + wire memoryC1_uid91_sqrtTables_lutmem_reset0; + wire [20:0] memoryC1_uid91_sqrtTables_lutmem_ia; + wire [7:0] memoryC1_uid91_sqrtTables_lutmem_aa; + wire [7:0] memoryC1_uid91_sqrtTables_lutmem_ab; + wire [20:0] memoryC1_uid91_sqrtTables_lutmem_ir; + wire [20:0] memoryC1_uid91_sqrtTables_lutmem_r; + wire memoryC2_uid94_sqrtTables_lutmem_reset0; + wire [11:0] memoryC2_uid94_sqrtTables_lutmem_ia; + wire [7:0] memoryC2_uid94_sqrtTables_lutmem_aa; + wire [7:0] memoryC2_uid94_sqrtTables_lutmem_ab; + wire [11:0] memoryC2_uid94_sqrtTables_lutmem_ir; + wire [11:0] memoryC2_uid94_sqrtTables_lutmem_r; + wire squaredResult_uid42_fpSqrtTest_cma_reset; + (* preserve, altera_attribute = "-name allow_synch_ctrl_usage off" *) reg [24:0] squaredResult_uid42_fpSqrtTest_cma_a0 [0:0]; + (* preserve, altera_attribute = "-name allow_synch_ctrl_usage off" *) reg [24:0] squaredResult_uid42_fpSqrtTest_cma_a1 [0:0]; + (* preserve, altera_attribute = "-name allow_synch_ctrl_usage off" *) reg [24:0] squaredResult_uid42_fpSqrtTest_cma_c0 [0:0]; + (* preserve, altera_attribute = "-name allow_synch_ctrl_usage off" *) reg [24:0] squaredResult_uid42_fpSqrtTest_cma_c1 [0:0]; + wire [49:0] squaredResult_uid42_fpSqrtTest_cma_p [0:0]; + wire [49:0] squaredResult_uid42_fpSqrtTest_cma_u [0:0]; + wire [49:0] squaredResult_uid42_fpSqrtTest_cma_w [0:0]; + wire [49:0] squaredResult_uid42_fpSqrtTest_cma_x [0:0]; + wire [49:0] squaredResult_uid42_fpSqrtTest_cma_y [0:0]; + reg [49:0] squaredResult_uid42_fpSqrtTest_cma_s [0:0]; + wire [49:0] squaredResult_uid42_fpSqrtTest_cma_qq; + wire [49:0] squaredResult_uid42_fpSqrtTest_cma_q; + wire squaredResult_uid42_fpSqrtTest_cma_ena0; + wire squaredResult_uid42_fpSqrtTest_cma_ena1; + wire squaredResult_uid42_fpSqrtTest_cma_ena2; + wire prodXY_uid113_pT1_uid101_invPolyEval_cma_reset; + (* preserve, altera_attribute = "-name allow_synch_ctrl_usage off" *) reg [11:0] prodXY_uid113_pT1_uid101_invPolyEval_cma_a0 [0:0]; + (* preserve, altera_attribute = "-name allow_synch_ctrl_usage off" *) reg [11:0] prodXY_uid113_pT1_uid101_invPolyEval_cma_a1 [0:0]; + (* preserve, altera_attribute = "-name allow_synch_ctrl_usage off" *) reg signed [11:0] prodXY_uid113_pT1_uid101_invPolyEval_cma_c0 [0:0]; + (* preserve, altera_attribute = "-name allow_synch_ctrl_usage off" *) reg signed [11:0] prodXY_uid113_pT1_uid101_invPolyEval_cma_c1 [0:0]; + wire signed [12:0] prodXY_uid113_pT1_uid101_invPolyEval_cma_l [0:0]; + wire signed [24:0] prodXY_uid113_pT1_uid101_invPolyEval_cma_p [0:0]; + wire signed [24:0] prodXY_uid113_pT1_uid101_invPolyEval_cma_u [0:0]; + wire signed [24:0] prodXY_uid113_pT1_uid101_invPolyEval_cma_w [0:0]; + wire signed [24:0] prodXY_uid113_pT1_uid101_invPolyEval_cma_x [0:0]; + wire signed [24:0] prodXY_uid113_pT1_uid101_invPolyEval_cma_y [0:0]; + reg signed [24:0] prodXY_uid113_pT1_uid101_invPolyEval_cma_s [0:0]; + wire [23:0] prodXY_uid113_pT1_uid101_invPolyEval_cma_qq; + wire [23:0] prodXY_uid113_pT1_uid101_invPolyEval_cma_q; + wire prodXY_uid113_pT1_uid101_invPolyEval_cma_ena0; + wire prodXY_uid113_pT1_uid101_invPolyEval_cma_ena1; + wire prodXY_uid113_pT1_uid101_invPolyEval_cma_ena2; + wire prodXY_uid116_pT2_uid107_invPolyEval_cma_reset; + (* preserve, altera_attribute = "-name allow_synch_ctrl_usage off" *) reg [15:0] prodXY_uid116_pT2_uid107_invPolyEval_cma_a0 [0:0]; + (* preserve, altera_attribute = "-name allow_synch_ctrl_usage off" *) reg [15:0] prodXY_uid116_pT2_uid107_invPolyEval_cma_a1 [0:0]; + (* preserve, altera_attribute = "-name allow_synch_ctrl_usage off" *) reg signed [22:0] prodXY_uid116_pT2_uid107_invPolyEval_cma_c0 [0:0]; + (* preserve, altera_attribute = "-name allow_synch_ctrl_usage off" *) reg signed [22:0] prodXY_uid116_pT2_uid107_invPolyEval_cma_c1 [0:0]; + wire signed [16:0] prodXY_uid116_pT2_uid107_invPolyEval_cma_l [0:0]; + wire signed [39:0] prodXY_uid116_pT2_uid107_invPolyEval_cma_p [0:0]; + wire signed [39:0] prodXY_uid116_pT2_uid107_invPolyEval_cma_u [0:0]; + wire signed [39:0] prodXY_uid116_pT2_uid107_invPolyEval_cma_w [0:0]; + wire signed [39:0] prodXY_uid116_pT2_uid107_invPolyEval_cma_x [0:0]; + wire signed [39:0] prodXY_uid116_pT2_uid107_invPolyEval_cma_y [0:0]; + reg signed [39:0] prodXY_uid116_pT2_uid107_invPolyEval_cma_s [0:0]; + wire [38:0] prodXY_uid116_pT2_uid107_invPolyEval_cma_qq; + wire [38:0] prodXY_uid116_pT2_uid107_invPolyEval_cma_q; + wire prodXY_uid116_pT2_uid107_invPolyEval_cma_ena0; + wire prodXY_uid116_pT2_uid107_invPolyEval_cma_ena1; + wire prodXY_uid116_pT2_uid107_invPolyEval_cma_ena2; + wire [0:0] expUpdateCRU_uid61_fpSqrtTest_merged_bit_select_b; + wire [22:0] expUpdateCRU_uid61_fpSqrtTest_merged_bit_select_c; + reg [22:0] redist0_expUpdateCRU_uid61_fpSqrtTest_merged_bit_select_c_1_q; + reg [0:0] redist1_lowRangeB_uid102_invPolyEval_b_1_q; + reg [23:0] redist2_fracRPreCR_uid39_fpSqrtTest_b_1_q; + reg [23:0] redist3_fracRPreCR_uid39_fpSqrtTest_b_5_q; + reg [0:0] redist4_expIncPEOnly_uid38_fpSqrtTest_b_5_q; + reg [7:0] redist6_yAddr_uid35_fpSqrtTest_b_3_q; + reg [7:0] redist7_yAddr_uid35_fpSqrtTest_b_7_q; + reg [7:0] redist8_expRMux_uid31_fpSqrtTest_q_2_q; + reg [0:0] redist9_expOddSelect_uid30_fpSqrtTest_q_13_q; + reg [22:0] redist10_frac_x_uid12_fpSqrtTest_b_2_q; + reg [0:0] redist12_signX_uid7_fpSqrtTest_b_14_q; + reg [23:0] redist3_fracRPreCR_uid39_fpSqrtTest_b_5_inputreg_q; + wire redist5_yForPe_uid36_fpSqrtTest_b_4_mem_reset0; + wire [15:0] redist5_yForPe_uid36_fpSqrtTest_b_4_mem_ia; + wire [1:0] redist5_yForPe_uid36_fpSqrtTest_b_4_mem_aa; + wire [1:0] redist5_yForPe_uid36_fpSqrtTest_b_4_mem_ab; + wire [15:0] redist5_yForPe_uid36_fpSqrtTest_b_4_mem_iq; + wire [15:0] redist5_yForPe_uid36_fpSqrtTest_b_4_mem_q; + wire [1:0] redist5_yForPe_uid36_fpSqrtTest_b_4_rdcnt_q; + (* preserve *) reg [1:0] redist5_yForPe_uid36_fpSqrtTest_b_4_rdcnt_i; + (* preserve *) reg redist5_yForPe_uid36_fpSqrtTest_b_4_rdcnt_eq; + wire [0:0] redist5_yForPe_uid36_fpSqrtTest_b_4_rdmux_s; + reg [1:0] redist5_yForPe_uid36_fpSqrtTest_b_4_rdmux_q; + reg [1:0] redist5_yForPe_uid36_fpSqrtTest_b_4_wraddr_q; + wire [1:0] redist5_yForPe_uid36_fpSqrtTest_b_4_mem_last_q; + wire [0:0] redist5_yForPe_uid36_fpSqrtTest_b_4_cmp_q; + reg [0:0] redist5_yForPe_uid36_fpSqrtTest_b_4_cmpReg_q; + wire [0:0] redist5_yForPe_uid36_fpSqrtTest_b_4_notEnable_q; + wire [0:0] redist5_yForPe_uid36_fpSqrtTest_b_4_nor_q; + (* preserve_syn_only *) reg [0:0] redist5_yForPe_uid36_fpSqrtTest_b_4_sticky_ena_q; + wire [0:0] redist5_yForPe_uid36_fpSqrtTest_b_4_enaAnd_q; + reg [22:0] redist11_frac_x_uid12_fpSqrtTest_b_13_outputreg_q; + wire redist11_frac_x_uid12_fpSqrtTest_b_13_mem_reset0; + wire [22:0] redist11_frac_x_uid12_fpSqrtTest_b_13_mem_ia; + wire [3:0] redist11_frac_x_uid12_fpSqrtTest_b_13_mem_aa; + wire [3:0] redist11_frac_x_uid12_fpSqrtTest_b_13_mem_ab; + wire [22:0] redist11_frac_x_uid12_fpSqrtTest_b_13_mem_iq; + wire [22:0] redist11_frac_x_uid12_fpSqrtTest_b_13_mem_q; + wire [3:0] redist11_frac_x_uid12_fpSqrtTest_b_13_rdcnt_q; + (* preserve *) reg [3:0] redist11_frac_x_uid12_fpSqrtTest_b_13_rdcnt_i; + (* preserve *) reg redist11_frac_x_uid12_fpSqrtTest_b_13_rdcnt_eq; + wire [0:0] redist11_frac_x_uid12_fpSqrtTest_b_13_rdmux_s; + reg [3:0] redist11_frac_x_uid12_fpSqrtTest_b_13_rdmux_q; + reg [3:0] redist11_frac_x_uid12_fpSqrtTest_b_13_wraddr_q; + wire [3:0] redist11_frac_x_uid12_fpSqrtTest_b_13_mem_last_q; + wire [0:0] redist11_frac_x_uid12_fpSqrtTest_b_13_cmp_q; + reg [0:0] redist11_frac_x_uid12_fpSqrtTest_b_13_cmpReg_q; + wire [0:0] redist11_frac_x_uid12_fpSqrtTest_b_13_notEnable_q; + wire [0:0] redist11_frac_x_uid12_fpSqrtTest_b_13_nor_q; + (* preserve_syn_only *) reg [0:0] redist11_frac_x_uid12_fpSqrtTest_b_13_sticky_ena_q; + wire [0:0] redist11_frac_x_uid12_fpSqrtTest_b_13_enaAnd_q; + reg [7:0] redist13_expX_uid6_fpSqrtTest_b_13_outputreg_q; + wire redist13_expX_uid6_fpSqrtTest_b_13_mem_reset0; + wire [7:0] redist13_expX_uid6_fpSqrtTest_b_13_mem_ia; + wire [3:0] redist13_expX_uid6_fpSqrtTest_b_13_mem_aa; + wire [3:0] redist13_expX_uid6_fpSqrtTest_b_13_mem_ab; + wire [7:0] redist13_expX_uid6_fpSqrtTest_b_13_mem_iq; + wire [7:0] redist13_expX_uid6_fpSqrtTest_b_13_mem_q; + wire [3:0] redist13_expX_uid6_fpSqrtTest_b_13_rdcnt_q; + (* preserve *) reg [3:0] redist13_expX_uid6_fpSqrtTest_b_13_rdcnt_i; + (* preserve *) reg redist13_expX_uid6_fpSqrtTest_b_13_rdcnt_eq; + wire [0:0] redist13_expX_uid6_fpSqrtTest_b_13_rdmux_s; + reg [3:0] redist13_expX_uid6_fpSqrtTest_b_13_rdmux_q; + reg [3:0] redist13_expX_uid6_fpSqrtTest_b_13_wraddr_q; + wire [4:0] redist13_expX_uid6_fpSqrtTest_b_13_mem_last_q; + wire [4:0] redist13_expX_uid6_fpSqrtTest_b_13_cmp_b; + wire [0:0] redist13_expX_uid6_fpSqrtTest_b_13_cmp_q; + reg [0:0] redist13_expX_uid6_fpSqrtTest_b_13_cmpReg_q; + wire [0:0] redist13_expX_uid6_fpSqrtTest_b_13_notEnable_q; + wire [0:0] redist13_expX_uid6_fpSqrtTest_b_13_nor_q; + (* preserve_syn_only *) reg [0:0] redist13_expX_uid6_fpSqrtTest_b_13_sticky_ena_q; + wire [0:0] redist13_expX_uid6_fpSqrtTest_b_13_enaAnd_q; + + + // signX_uid7_fpSqrtTest(BITSELECT,6)@0 + assign signX_uid7_fpSqrtTest_b = a[31:31]; + + // redist12_signX_uid7_fpSqrtTest_b_14(DELAY,137) + dspba_delay_ver #( .width(1), .depth(14), .reset_kind("ASYNC") ) + redist12_signX_uid7_fpSqrtTest_b_14 ( .xin(signX_uid7_fpSqrtTest_b), .xout(redist12_signX_uid7_fpSqrtTest_b_14_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // cstAllZWE_uid10_fpSqrtTest(CONSTANT,9) + assign cstAllZWE_uid10_fpSqrtTest_q = 8'b00000000; + + // redist13_expX_uid6_fpSqrtTest_b_13_notEnable(LOGICAL,171) + assign redist13_expX_uid6_fpSqrtTest_b_13_notEnable_q = ~ (en); + + // redist13_expX_uid6_fpSqrtTest_b_13_nor(LOGICAL,172) + assign redist13_expX_uid6_fpSqrtTest_b_13_nor_q = ~ (redist13_expX_uid6_fpSqrtTest_b_13_notEnable_q | redist13_expX_uid6_fpSqrtTest_b_13_sticky_ena_q); + + // redist13_expX_uid6_fpSqrtTest_b_13_mem_last(CONSTANT,168) + assign redist13_expX_uid6_fpSqrtTest_b_13_mem_last_q = 5'b01001; + + // redist13_expX_uid6_fpSqrtTest_b_13_cmp(LOGICAL,169) + assign redist13_expX_uid6_fpSqrtTest_b_13_cmp_b = {1'b0, redist13_expX_uid6_fpSqrtTest_b_13_rdmux_q}; + assign redist13_expX_uid6_fpSqrtTest_b_13_cmp_q = redist13_expX_uid6_fpSqrtTest_b_13_mem_last_q == redist13_expX_uid6_fpSqrtTest_b_13_cmp_b ? 1'b1 : 1'b0; + + // redist13_expX_uid6_fpSqrtTest_b_13_cmpReg(REG,170) + always @ (posedge clk or posedge areset) + begin + if (areset) + begin + redist13_expX_uid6_fpSqrtTest_b_13_cmpReg_q <= 1'b0; + end + else if (en == 1'b1) + begin + redist13_expX_uid6_fpSqrtTest_b_13_cmpReg_q <= redist13_expX_uid6_fpSqrtTest_b_13_cmp_q; + end + end + + // redist13_expX_uid6_fpSqrtTest_b_13_sticky_ena(REG,173) + always @ (posedge clk or posedge areset) + begin + if (areset) + begin + redist13_expX_uid6_fpSqrtTest_b_13_sticky_ena_q <= 1'b0; + end + else if (redist13_expX_uid6_fpSqrtTest_b_13_nor_q == 1'b1) + begin + redist13_expX_uid6_fpSqrtTest_b_13_sticky_ena_q <= redist13_expX_uid6_fpSqrtTest_b_13_cmpReg_q; + end + end + + // redist13_expX_uid6_fpSqrtTest_b_13_enaAnd(LOGICAL,174) + assign redist13_expX_uid6_fpSqrtTest_b_13_enaAnd_q = redist13_expX_uid6_fpSqrtTest_b_13_sticky_ena_q & en; + + // redist13_expX_uid6_fpSqrtTest_b_13_rdcnt(COUNTER,165) + // low=0, high=10, step=1, init=0 + always @ (posedge clk or posedge areset) + begin + if (areset) + begin + redist13_expX_uid6_fpSqrtTest_b_13_rdcnt_i <= 4'd0; + redist13_expX_uid6_fpSqrtTest_b_13_rdcnt_eq <= 1'b0; + end + else if (en == 1'b1) + begin + if (redist13_expX_uid6_fpSqrtTest_b_13_rdcnt_i == 4'd9) + begin + redist13_expX_uid6_fpSqrtTest_b_13_rdcnt_eq <= 1'b1; + end + else + begin + redist13_expX_uid6_fpSqrtTest_b_13_rdcnt_eq <= 1'b0; + end + if (redist13_expX_uid6_fpSqrtTest_b_13_rdcnt_eq == 1'b1) + begin + redist13_expX_uid6_fpSqrtTest_b_13_rdcnt_i <= $unsigned(redist13_expX_uid6_fpSqrtTest_b_13_rdcnt_i) + $unsigned(4'd6); + end + else + begin + redist13_expX_uid6_fpSqrtTest_b_13_rdcnt_i <= $unsigned(redist13_expX_uid6_fpSqrtTest_b_13_rdcnt_i) + $unsigned(4'd1); + end + end + end + assign redist13_expX_uid6_fpSqrtTest_b_13_rdcnt_q = redist13_expX_uid6_fpSqrtTest_b_13_rdcnt_i[3:0]; + + // redist13_expX_uid6_fpSqrtTest_b_13_rdmux(MUX,166) + assign redist13_expX_uid6_fpSqrtTest_b_13_rdmux_s = en; + always @(redist13_expX_uid6_fpSqrtTest_b_13_rdmux_s or redist13_expX_uid6_fpSqrtTest_b_13_wraddr_q or redist13_expX_uid6_fpSqrtTest_b_13_rdcnt_q) + begin + unique case (redist13_expX_uid6_fpSqrtTest_b_13_rdmux_s) + 1'b0 : redist13_expX_uid6_fpSqrtTest_b_13_rdmux_q = redist13_expX_uid6_fpSqrtTest_b_13_wraddr_q; + 1'b1 : redist13_expX_uid6_fpSqrtTest_b_13_rdmux_q = redist13_expX_uid6_fpSqrtTest_b_13_rdcnt_q; + default : redist13_expX_uid6_fpSqrtTest_b_13_rdmux_q = 4'b0; + endcase + end + + // VCC(CONSTANT,1) + assign VCC_q = 1'b1; + + // expX_uid6_fpSqrtTest(BITSELECT,5)@0 + assign expX_uid6_fpSqrtTest_b = a[30:23]; + + // redist13_expX_uid6_fpSqrtTest_b_13_wraddr(REG,167) + always @ (posedge clk or posedge areset) + begin + if (areset) + begin + redist13_expX_uid6_fpSqrtTest_b_13_wraddr_q <= 4'b1010; + end + else + begin + redist13_expX_uid6_fpSqrtTest_b_13_wraddr_q <= redist13_expX_uid6_fpSqrtTest_b_13_rdmux_q; + end + end + + // redist13_expX_uid6_fpSqrtTest_b_13_mem(DUALMEM,164) + assign redist13_expX_uid6_fpSqrtTest_b_13_mem_ia = expX_uid6_fpSqrtTest_b; + assign redist13_expX_uid6_fpSqrtTest_b_13_mem_aa = redist13_expX_uid6_fpSqrtTest_b_13_wraddr_q; + assign redist13_expX_uid6_fpSqrtTest_b_13_mem_ab = redist13_expX_uid6_fpSqrtTest_b_13_rdmux_q; + assign redist13_expX_uid6_fpSqrtTest_b_13_mem_reset0 = areset; + altera_syncram #( + .ram_block_type("MLAB"), + .operation_mode("DUAL_PORT"), + .width_a(8), + .widthad_a(4), + .numwords_a(11), + .width_b(8), + .widthad_b(4), + .numwords_b(11), + .lpm_type("altera_syncram"), + .width_byteena_a(1), + .address_reg_b("CLOCK0"), + .indata_reg_b("CLOCK0"), + .rdcontrol_reg_b("CLOCK0"), + .byteena_reg_b("CLOCK0"), + .outdata_reg_b("CLOCK1"), + .outdata_aclr_b("CLEAR1"), + .clock_enable_input_a("NORMAL"), + .clock_enable_input_b("NORMAL"), + .clock_enable_output_b("NORMAL"), + .read_during_write_mode_mixed_ports("DONT_CARE"), + .power_up_uninitialized("TRUE"), + .intended_device_family("Arria 10") + ) redist13_expX_uid6_fpSqrtTest_b_13_mem_dmem ( + .clocken1(redist13_expX_uid6_fpSqrtTest_b_13_enaAnd_q[0]), + .clocken0(VCC_q[0]), + .clock0(clk), + .aclr1(redist13_expX_uid6_fpSqrtTest_b_13_mem_reset0), + .clock1(clk), + .address_a(redist13_expX_uid6_fpSqrtTest_b_13_mem_aa), + .data_a(redist13_expX_uid6_fpSqrtTest_b_13_mem_ia), + .wren_a(en[0]), + .address_b(redist13_expX_uid6_fpSqrtTest_b_13_mem_ab), + .q_b(redist13_expX_uid6_fpSqrtTest_b_13_mem_iq), + .wren_b(), + .rden_a(), + .rden_b(), + .data_b(), + .clocken2(), + .clocken3(), + .aclr0(), + .addressstall_a(), + .addressstall_b(), + .byteena_a(), + .byteena_b(), + .eccencbypass(), + .eccencparity(), + .sclr(), + .address2_a(), + .address2_b(), + .q_a(), + .eccstatus() + ); + assign redist13_expX_uid6_fpSqrtTest_b_13_mem_q = redist13_expX_uid6_fpSqrtTest_b_13_mem_iq[7:0]; + + // redist13_expX_uid6_fpSqrtTest_b_13_outputreg(DELAY,163) + dspba_delay_ver #( .width(8), .depth(1), .reset_kind("ASYNC") ) + redist13_expX_uid6_fpSqrtTest_b_13_outputreg ( .xin(redist13_expX_uid6_fpSqrtTest_b_13_mem_q), .xout(redist13_expX_uid6_fpSqrtTest_b_13_outputreg_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // excZ_x_uid13_fpSqrtTest(LOGICAL,12)@13 + 1 + assign excZ_x_uid13_fpSqrtTest_qi = redist13_expX_uid6_fpSqrtTest_b_13_outputreg_q == cstAllZWE_uid10_fpSqrtTest_q ? 1'b1 : 1'b0; + dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") ) + excZ_x_uid13_fpSqrtTest_delay ( .xin(excZ_x_uid13_fpSqrtTest_qi), .xout(excZ_x_uid13_fpSqrtTest_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // negZero_uid85_fpSqrtTest(LOGICAL,84)@14 + 1 + assign negZero_uid85_fpSqrtTest_qi = excZ_x_uid13_fpSqrtTest_q & redist12_signX_uid7_fpSqrtTest_b_14_q; + dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") ) + negZero_uid85_fpSqrtTest_delay ( .xin(negZero_uid85_fpSqrtTest_qi), .xout(negZero_uid85_fpSqrtTest_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // cstAllOWE_uid8_fpSqrtTest(CONSTANT,7) + assign cstAllOWE_uid8_fpSqrtTest_q = 8'b11111111; + + // GND(CONSTANT,0) + assign GND_q = 1'b0; + + // redist11_frac_x_uid12_fpSqrtTest_b_13_notEnable(LOGICAL,159) + assign redist11_frac_x_uid12_fpSqrtTest_b_13_notEnable_q = ~ (en); + + // redist11_frac_x_uid12_fpSqrtTest_b_13_nor(LOGICAL,160) + assign redist11_frac_x_uid12_fpSqrtTest_b_13_nor_q = ~ (redist11_frac_x_uid12_fpSqrtTest_b_13_notEnable_q | redist11_frac_x_uid12_fpSqrtTest_b_13_sticky_ena_q); + + // redist11_frac_x_uid12_fpSqrtTest_b_13_mem_last(CONSTANT,156) + assign redist11_frac_x_uid12_fpSqrtTest_b_13_mem_last_q = 4'b0111; + + // redist11_frac_x_uid12_fpSqrtTest_b_13_cmp(LOGICAL,157) + assign redist11_frac_x_uid12_fpSqrtTest_b_13_cmp_q = redist11_frac_x_uid12_fpSqrtTest_b_13_mem_last_q == redist11_frac_x_uid12_fpSqrtTest_b_13_rdmux_q ? 1'b1 : 1'b0; + + // redist11_frac_x_uid12_fpSqrtTest_b_13_cmpReg(REG,158) + always @ (posedge clk or posedge areset) + begin + if (areset) + begin + redist11_frac_x_uid12_fpSqrtTest_b_13_cmpReg_q <= 1'b0; + end + else if (en == 1'b1) + begin + redist11_frac_x_uid12_fpSqrtTest_b_13_cmpReg_q <= redist11_frac_x_uid12_fpSqrtTest_b_13_cmp_q; + end + end + + // redist11_frac_x_uid12_fpSqrtTest_b_13_sticky_ena(REG,161) + always @ (posedge clk or posedge areset) + begin + if (areset) + begin + redist11_frac_x_uid12_fpSqrtTest_b_13_sticky_ena_q <= 1'b0; + end + else if (redist11_frac_x_uid12_fpSqrtTest_b_13_nor_q == 1'b1) + begin + redist11_frac_x_uid12_fpSqrtTest_b_13_sticky_ena_q <= redist11_frac_x_uid12_fpSqrtTest_b_13_cmpReg_q; + end + end + + // redist11_frac_x_uid12_fpSqrtTest_b_13_enaAnd(LOGICAL,162) + assign redist11_frac_x_uid12_fpSqrtTest_b_13_enaAnd_q = redist11_frac_x_uid12_fpSqrtTest_b_13_sticky_ena_q & en; + + // redist11_frac_x_uid12_fpSqrtTest_b_13_rdcnt(COUNTER,153) + // low=0, high=8, step=1, init=0 + always @ (posedge clk or posedge areset) + begin + if (areset) + begin + redist11_frac_x_uid12_fpSqrtTest_b_13_rdcnt_i <= 4'd0; + redist11_frac_x_uid12_fpSqrtTest_b_13_rdcnt_eq <= 1'b0; + end + else if (en == 1'b1) + begin + if (redist11_frac_x_uid12_fpSqrtTest_b_13_rdcnt_i == 4'd7) + begin + redist11_frac_x_uid12_fpSqrtTest_b_13_rdcnt_eq <= 1'b1; + end + else + begin + redist11_frac_x_uid12_fpSqrtTest_b_13_rdcnt_eq <= 1'b0; + end + if (redist11_frac_x_uid12_fpSqrtTest_b_13_rdcnt_eq == 1'b1) + begin + redist11_frac_x_uid12_fpSqrtTest_b_13_rdcnt_i <= $unsigned(redist11_frac_x_uid12_fpSqrtTest_b_13_rdcnt_i) + $unsigned(4'd8); + end + else + begin + redist11_frac_x_uid12_fpSqrtTest_b_13_rdcnt_i <= $unsigned(redist11_frac_x_uid12_fpSqrtTest_b_13_rdcnt_i) + $unsigned(4'd1); + end + end + end + assign redist11_frac_x_uid12_fpSqrtTest_b_13_rdcnt_q = redist11_frac_x_uid12_fpSqrtTest_b_13_rdcnt_i[3:0]; + + // redist11_frac_x_uid12_fpSqrtTest_b_13_rdmux(MUX,154) + assign redist11_frac_x_uid12_fpSqrtTest_b_13_rdmux_s = en; + always @(redist11_frac_x_uid12_fpSqrtTest_b_13_rdmux_s or redist11_frac_x_uid12_fpSqrtTest_b_13_wraddr_q or redist11_frac_x_uid12_fpSqrtTest_b_13_rdcnt_q) + begin + unique case (redist11_frac_x_uid12_fpSqrtTest_b_13_rdmux_s) + 1'b0 : redist11_frac_x_uid12_fpSqrtTest_b_13_rdmux_q = redist11_frac_x_uid12_fpSqrtTest_b_13_wraddr_q; + 1'b1 : redist11_frac_x_uid12_fpSqrtTest_b_13_rdmux_q = redist11_frac_x_uid12_fpSqrtTest_b_13_rdcnt_q; + default : redist11_frac_x_uid12_fpSqrtTest_b_13_rdmux_q = 4'b0; + endcase + end + + // frac_x_uid12_fpSqrtTest(BITSELECT,11)@0 + assign frac_x_uid12_fpSqrtTest_b = a[22:0]; + + // redist10_frac_x_uid12_fpSqrtTest_b_2(DELAY,135) + dspba_delay_ver #( .width(23), .depth(2), .reset_kind("ASYNC") ) + redist10_frac_x_uid12_fpSqrtTest_b_2 ( .xin(frac_x_uid12_fpSqrtTest_b), .xout(redist10_frac_x_uid12_fpSqrtTest_b_2_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // redist11_frac_x_uid12_fpSqrtTest_b_13_wraddr(REG,155) + always @ (posedge clk or posedge areset) + begin + if (areset) + begin + redist11_frac_x_uid12_fpSqrtTest_b_13_wraddr_q <= 4'b1000; + end + else + begin + redist11_frac_x_uid12_fpSqrtTest_b_13_wraddr_q <= redist11_frac_x_uid12_fpSqrtTest_b_13_rdmux_q; + end + end + + // redist11_frac_x_uid12_fpSqrtTest_b_13_mem(DUALMEM,152) + assign redist11_frac_x_uid12_fpSqrtTest_b_13_mem_ia = redist10_frac_x_uid12_fpSqrtTest_b_2_q; + assign redist11_frac_x_uid12_fpSqrtTest_b_13_mem_aa = redist11_frac_x_uid12_fpSqrtTest_b_13_wraddr_q; + assign redist11_frac_x_uid12_fpSqrtTest_b_13_mem_ab = redist11_frac_x_uid12_fpSqrtTest_b_13_rdmux_q; + assign redist11_frac_x_uid12_fpSqrtTest_b_13_mem_reset0 = areset; + altera_syncram #( + .ram_block_type("MLAB"), + .operation_mode("DUAL_PORT"), + .width_a(23), + .widthad_a(4), + .numwords_a(9), + .width_b(23), + .widthad_b(4), + .numwords_b(9), + .lpm_type("altera_syncram"), + .width_byteena_a(1), + .address_reg_b("CLOCK0"), + .indata_reg_b("CLOCK0"), + .rdcontrol_reg_b("CLOCK0"), + .byteena_reg_b("CLOCK0"), + .outdata_reg_b("CLOCK1"), + .outdata_aclr_b("CLEAR1"), + .clock_enable_input_a("NORMAL"), + .clock_enable_input_b("NORMAL"), + .clock_enable_output_b("NORMAL"), + .read_during_write_mode_mixed_ports("DONT_CARE"), + .power_up_uninitialized("TRUE"), + .intended_device_family("Arria 10") + ) redist11_frac_x_uid12_fpSqrtTest_b_13_mem_dmem ( + .clocken1(redist11_frac_x_uid12_fpSqrtTest_b_13_enaAnd_q[0]), + .clocken0(VCC_q[0]), + .clock0(clk), + .aclr1(redist11_frac_x_uid12_fpSqrtTest_b_13_mem_reset0), + .clock1(clk), + .address_a(redist11_frac_x_uid12_fpSqrtTest_b_13_mem_aa), + .data_a(redist11_frac_x_uid12_fpSqrtTest_b_13_mem_ia), + .wren_a(en[0]), + .address_b(redist11_frac_x_uid12_fpSqrtTest_b_13_mem_ab), + .q_b(redist11_frac_x_uid12_fpSqrtTest_b_13_mem_iq), + .wren_b(), + .rden_a(), + .rden_b(), + .data_b(), + .clocken2(), + .clocken3(), + .aclr0(), + .addressstall_a(), + .addressstall_b(), + .byteena_a(), + .byteena_b(), + .eccencbypass(), + .eccencparity(), + .sclr(), + .address2_a(), + .address2_b(), + .q_a(), + .eccstatus() + ); + assign redist11_frac_x_uid12_fpSqrtTest_b_13_mem_q = redist11_frac_x_uid12_fpSqrtTest_b_13_mem_iq[22:0]; + + // redist11_frac_x_uid12_fpSqrtTest_b_13_outputreg(DELAY,151) + dspba_delay_ver #( .width(23), .depth(1), .reset_kind("ASYNC") ) + redist11_frac_x_uid12_fpSqrtTest_b_13_outputreg ( .xin(redist11_frac_x_uid12_fpSqrtTest_b_13_mem_q), .xout(redist11_frac_x_uid12_fpSqrtTest_b_13_outputreg_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // oFracX_uid44_fpSqrtTest(BITJOIN,43)@13 + assign oFracX_uid44_fpSqrtTest_q = {VCC_q, redist11_frac_x_uid12_fpSqrtTest_b_13_outputreg_q}; + + // oFracXZ_mergedSignalTM_uid47_fpSqrtTest(BITJOIN,46)@13 + assign oFracXZ_mergedSignalTM_uid47_fpSqrtTest_q = {oFracX_uid44_fpSqrtTest_q, GND_q}; + + // oFracXSignExt_mergedSignalTM_uid52_fpSqrtTest(BITJOIN,51)@13 + assign oFracXSignExt_mergedSignalTM_uid52_fpSqrtTest_q = {GND_q, oFracX_uid44_fpSqrtTest_q}; + + // expX0PS_uid29_fpSqrtTest(BITSELECT,28)@0 + assign expX0PS_uid29_fpSqrtTest_in = expX_uid6_fpSqrtTest_b[0:0]; + assign expX0PS_uid29_fpSqrtTest_b = expX0PS_uid29_fpSqrtTest_in[0:0]; + + // expOddSelect_uid30_fpSqrtTest(LOGICAL,29)@0 + assign expOddSelect_uid30_fpSqrtTest_q = ~ (expX0PS_uid29_fpSqrtTest_b); + + // redist9_expOddSelect_uid30_fpSqrtTest_q_13(DELAY,134) + dspba_delay_ver #( .width(1), .depth(13), .reset_kind("ASYNC") ) + redist9_expOddSelect_uid30_fpSqrtTest_q_13 ( .xin(expOddSelect_uid30_fpSqrtTest_q), .xout(redist9_expOddSelect_uid30_fpSqrtTest_q_13_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // normalizedXForComp_uid54_fpSqrtTest(MUX,53)@13 + assign normalizedXForComp_uid54_fpSqrtTest_s = redist9_expOddSelect_uid30_fpSqrtTest_q_13_q; + always @(normalizedXForComp_uid54_fpSqrtTest_s or en or oFracXSignExt_mergedSignalTM_uid52_fpSqrtTest_q or oFracXZ_mergedSignalTM_uid47_fpSqrtTest_q) + begin + unique case (normalizedXForComp_uid54_fpSqrtTest_s) + 1'b0 : normalizedXForComp_uid54_fpSqrtTest_q = oFracXSignExt_mergedSignalTM_uid52_fpSqrtTest_q; + 1'b1 : normalizedXForComp_uid54_fpSqrtTest_q = oFracXZ_mergedSignalTM_uid47_fpSqrtTest_q; + default : normalizedXForComp_uid54_fpSqrtTest_q = 25'b0; + endcase + end + + // paddingY_uid55_fpSqrtTest(CONSTANT,54) + assign paddingY_uid55_fpSqrtTest_q = 25'b0000000000000000000000000; + + // updatedY_uid56_fpSqrtTest(BITJOIN,55)@13 + assign updatedY_uid56_fpSqrtTest_q = {normalizedXForComp_uid54_fpSqrtTest_q, paddingY_uid55_fpSqrtTest_q}; + + // addrFull_uid33_fpSqrtTest(BITJOIN,32)@0 + assign addrFull_uid33_fpSqrtTest_q = {expOddSelect_uid30_fpSqrtTest_q, frac_x_uid12_fpSqrtTest_b}; + + // yAddr_uid35_fpSqrtTest(BITSELECT,34)@0 + assign yAddr_uid35_fpSqrtTest_b = addrFull_uid33_fpSqrtTest_q[23:16]; + + // memoryC2_uid94_sqrtTables_lutmem(DUALMEM,120)@0 + 2 + // in j@20000000 + assign memoryC2_uid94_sqrtTables_lutmem_aa = yAddr_uid35_fpSqrtTest_b; + assign memoryC2_uid94_sqrtTables_lutmem_reset0 = areset; + altera_syncram #( + .ram_block_type("M20K"), + .operation_mode("ROM"), + .width_a(12), + .widthad_a(8), + .numwords_a(256), + .lpm_type("altera_syncram"), + .width_byteena_a(1), + .outdata_reg_a("CLOCK0"), + .outdata_aclr_a("CLEAR0"), + .clock_enable_input_a("NORMAL"), + .power_up_uninitialized("FALSE"), + .init_file("acl_fsqrt_memoryC2_uid94_sqrtTables_lutmem.hex"), + .init_file_layout("PORT_A"), + .intended_device_family("Arria 10") + ) memoryC2_uid94_sqrtTables_lutmem_dmem ( + .clocken0(en[0]), + .aclr0(memoryC2_uid94_sqrtTables_lutmem_reset0), + .clock0(clk), + .address_a(memoryC2_uid94_sqrtTables_lutmem_aa), + .q_a(memoryC2_uid94_sqrtTables_lutmem_ir), + .wren_a(), + .wren_b(), + .rden_a(), + .rden_b(), + .data_a(), + .data_b(), + .address_b(), + .clock1(), + .clocken1(), + .clocken2(), + .clocken3(), + .aclr1(), + .addressstall_a(), + .addressstall_b(), + .byteena_a(), + .byteena_b(), + .eccencbypass(), + .eccencparity(), + .sclr(), + .address2_a(), + .address2_b(), + .q_b(), + .eccstatus() + ); + assign memoryC2_uid94_sqrtTables_lutmem_r = memoryC2_uid94_sqrtTables_lutmem_ir[11:0]; + + // yForPe_uid36_fpSqrtTest(BITSELECT,35)@2 + assign yForPe_uid36_fpSqrtTest_in = redist10_frac_x_uid12_fpSqrtTest_b_2_q[15:0]; + assign yForPe_uid36_fpSqrtTest_b = yForPe_uid36_fpSqrtTest_in[15:0]; + + // yT1_uid100_invPolyEval(BITSELECT,99)@2 + assign yT1_uid100_invPolyEval_b = yForPe_uid36_fpSqrtTest_b[15:4]; + + // prodXY_uid113_pT1_uid101_invPolyEval_cma(CHAINMULTADD,122)@2 + 3 + assign prodXY_uid113_pT1_uid101_invPolyEval_cma_reset = areset; + assign prodXY_uid113_pT1_uid101_invPolyEval_cma_ena0 = en[0]; + assign prodXY_uid113_pT1_uid101_invPolyEval_cma_ena1 = prodXY_uid113_pT1_uid101_invPolyEval_cma_ena0; + assign prodXY_uid113_pT1_uid101_invPolyEval_cma_ena2 = prodXY_uid113_pT1_uid101_invPolyEval_cma_ena0; + assign prodXY_uid113_pT1_uid101_invPolyEval_cma_l[0] = $signed({1'b0, prodXY_uid113_pT1_uid101_invPolyEval_cma_a1[0][11:0]}); + assign prodXY_uid113_pT1_uid101_invPolyEval_cma_p[0] = prodXY_uid113_pT1_uid101_invPolyEval_cma_l[0] * prodXY_uid113_pT1_uid101_invPolyEval_cma_c1[0]; + assign prodXY_uid113_pT1_uid101_invPolyEval_cma_u[0] = prodXY_uid113_pT1_uid101_invPolyEval_cma_p[0][24:0]; + assign prodXY_uid113_pT1_uid101_invPolyEval_cma_w[0] = prodXY_uid113_pT1_uid101_invPolyEval_cma_u[0]; + assign prodXY_uid113_pT1_uid101_invPolyEval_cma_x[0] = prodXY_uid113_pT1_uid101_invPolyEval_cma_w[0]; + assign prodXY_uid113_pT1_uid101_invPolyEval_cma_y[0] = prodXY_uid113_pT1_uid101_invPolyEval_cma_x[0]; + always @ (posedge clk or posedge areset) + begin + if (areset) + begin + prodXY_uid113_pT1_uid101_invPolyEval_cma_a0 <= '{default: '0}; + prodXY_uid113_pT1_uid101_invPolyEval_cma_c0 <= '{default: '0}; + end + else + begin + if (prodXY_uid113_pT1_uid101_invPolyEval_cma_ena0 == 1'b1) + begin + prodXY_uid113_pT1_uid101_invPolyEval_cma_a0[0] <= yT1_uid100_invPolyEval_b; + prodXY_uid113_pT1_uid101_invPolyEval_cma_c0[0] <= memoryC2_uid94_sqrtTables_lutmem_r; + end + end + end + always @ (posedge clk or posedge areset) + begin + if (areset) + begin + prodXY_uid113_pT1_uid101_invPolyEval_cma_a1 <= '{default: '0}; + prodXY_uid113_pT1_uid101_invPolyEval_cma_c1 <= '{default: '0}; + end + else + begin + if (prodXY_uid113_pT1_uid101_invPolyEval_cma_ena2 == 1'b1) + begin + prodXY_uid113_pT1_uid101_invPolyEval_cma_a1 <= prodXY_uid113_pT1_uid101_invPolyEval_cma_a0; + prodXY_uid113_pT1_uid101_invPolyEval_cma_c1 <= prodXY_uid113_pT1_uid101_invPolyEval_cma_c0; + end + end + end + always @ (posedge clk or posedge areset) + begin + if (areset) + begin + prodXY_uid113_pT1_uid101_invPolyEval_cma_s <= '{default: '0}; + end + else + begin + if (prodXY_uid113_pT1_uid101_invPolyEval_cma_ena1 == 1'b1) + begin + prodXY_uid113_pT1_uid101_invPolyEval_cma_s[0] <= prodXY_uid113_pT1_uid101_invPolyEval_cma_y[0]; + end + end + end + dspba_delay_ver #( .width(24), .depth(0), .reset_kind("ASYNC") ) + prodXY_uid113_pT1_uid101_invPolyEval_cma_delay ( .xin(prodXY_uid113_pT1_uid101_invPolyEval_cma_s[0][23:0]), .xout(prodXY_uid113_pT1_uid101_invPolyEval_cma_qq), .ena(en[0]), .clk(clk), .aclr(areset) ); + assign prodXY_uid113_pT1_uid101_invPolyEval_cma_q = prodXY_uid113_pT1_uid101_invPolyEval_cma_qq[23:0]; + + // osig_uid114_pT1_uid101_invPolyEval(BITSELECT,113)@5 + assign osig_uid114_pT1_uid101_invPolyEval_b = prodXY_uid113_pT1_uid101_invPolyEval_cma_q[23:11]; + + // highBBits_uid103_invPolyEval(BITSELECT,102)@5 + assign highBBits_uid103_invPolyEval_b = osig_uid114_pT1_uid101_invPolyEval_b[12:1]; + + // redist6_yAddr_uid35_fpSqrtTest_b_3(DELAY,131) + dspba_delay_ver #( .width(8), .depth(3), .reset_kind("ASYNC") ) + redist6_yAddr_uid35_fpSqrtTest_b_3 ( .xin(yAddr_uid35_fpSqrtTest_b), .xout(redist6_yAddr_uid35_fpSqrtTest_b_3_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // memoryC1_uid91_sqrtTables_lutmem(DUALMEM,119)@3 + 2 + // in j@20000000 + assign memoryC1_uid91_sqrtTables_lutmem_aa = redist6_yAddr_uid35_fpSqrtTest_b_3_q; + assign memoryC1_uid91_sqrtTables_lutmem_reset0 = areset; + altera_syncram #( + .ram_block_type("M20K"), + .operation_mode("ROM"), + .width_a(21), + .widthad_a(8), + .numwords_a(256), + .lpm_type("altera_syncram"), + .width_byteena_a(1), + .outdata_reg_a("CLOCK0"), + .outdata_aclr_a("CLEAR0"), + .clock_enable_input_a("NORMAL"), + .power_up_uninitialized("FALSE"), + .init_file("acl_fsqrt_memoryC1_uid91_sqrtTables_lutmem.hex"), + .init_file_layout("PORT_A"), + .intended_device_family("Arria 10") + ) memoryC1_uid91_sqrtTables_lutmem_dmem ( + .clocken0(en[0]), + .aclr0(memoryC1_uid91_sqrtTables_lutmem_reset0), + .clock0(clk), + .address_a(memoryC1_uid91_sqrtTables_lutmem_aa), + .q_a(memoryC1_uid91_sqrtTables_lutmem_ir), + .wren_a(), + .wren_b(), + .rden_a(), + .rden_b(), + .data_a(), + .data_b(), + .address_b(), + .clock1(), + .clocken1(), + .clocken2(), + .clocken3(), + .aclr1(), + .addressstall_a(), + .addressstall_b(), + .byteena_a(), + .byteena_b(), + .eccencbypass(), + .eccencparity(), + .sclr(), + .address2_a(), + .address2_b(), + .q_b(), + .eccstatus() + ); + assign memoryC1_uid91_sqrtTables_lutmem_r = memoryC1_uid91_sqrtTables_lutmem_ir[20:0]; + + // s1sumAHighB_uid104_invPolyEval(ADD,103)@5 + 1 + assign s1sumAHighB_uid104_invPolyEval_a = {{1{memoryC1_uid91_sqrtTables_lutmem_r[20]}}, memoryC1_uid91_sqrtTables_lutmem_r}; + assign s1sumAHighB_uid104_invPolyEval_b = {{10{highBBits_uid103_invPolyEval_b[11]}}, highBBits_uid103_invPolyEval_b}; + always @ (posedge clk or posedge areset) + begin + if (areset) + begin + s1sumAHighB_uid104_invPolyEval_o <= 22'b0; + end + else if (en == 1'b1) + begin + s1sumAHighB_uid104_invPolyEval_o <= $signed(s1sumAHighB_uid104_invPolyEval_a) + $signed(s1sumAHighB_uid104_invPolyEval_b); + end + end + assign s1sumAHighB_uid104_invPolyEval_q = s1sumAHighB_uid104_invPolyEval_o[21:0]; + + // lowRangeB_uid102_invPolyEval(BITSELECT,101)@5 + assign lowRangeB_uid102_invPolyEval_in = osig_uid114_pT1_uid101_invPolyEval_b[0:0]; + assign lowRangeB_uid102_invPolyEval_b = lowRangeB_uid102_invPolyEval_in[0:0]; + + // redist1_lowRangeB_uid102_invPolyEval_b_1(DELAY,126) + dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") ) + redist1_lowRangeB_uid102_invPolyEval_b_1 ( .xin(lowRangeB_uid102_invPolyEval_b), .xout(redist1_lowRangeB_uid102_invPolyEval_b_1_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // s1_uid105_invPolyEval(BITJOIN,104)@6 + assign s1_uid105_invPolyEval_q = {s1sumAHighB_uid104_invPolyEval_q, redist1_lowRangeB_uid102_invPolyEval_b_1_q}; + + // redist5_yForPe_uid36_fpSqrtTest_b_4_notEnable(LOGICAL,147) + assign redist5_yForPe_uid36_fpSqrtTest_b_4_notEnable_q = ~ (en); + + // redist5_yForPe_uid36_fpSqrtTest_b_4_nor(LOGICAL,148) + assign redist5_yForPe_uid36_fpSqrtTest_b_4_nor_q = ~ (redist5_yForPe_uid36_fpSqrtTest_b_4_notEnable_q | redist5_yForPe_uid36_fpSqrtTest_b_4_sticky_ena_q); + + // redist5_yForPe_uid36_fpSqrtTest_b_4_mem_last(CONSTANT,144) + assign redist5_yForPe_uid36_fpSqrtTest_b_4_mem_last_q = 2'b01; + + // redist5_yForPe_uid36_fpSqrtTest_b_4_cmp(LOGICAL,145) + assign redist5_yForPe_uid36_fpSqrtTest_b_4_cmp_q = redist5_yForPe_uid36_fpSqrtTest_b_4_mem_last_q == redist5_yForPe_uid36_fpSqrtTest_b_4_rdmux_q ? 1'b1 : 1'b0; + + // redist5_yForPe_uid36_fpSqrtTest_b_4_cmpReg(REG,146) + always @ (posedge clk or posedge areset) + begin + if (areset) + begin + redist5_yForPe_uid36_fpSqrtTest_b_4_cmpReg_q <= 1'b0; + end + else if (en == 1'b1) + begin + redist5_yForPe_uid36_fpSqrtTest_b_4_cmpReg_q <= redist5_yForPe_uid36_fpSqrtTest_b_4_cmp_q; + end + end + + // redist5_yForPe_uid36_fpSqrtTest_b_4_sticky_ena(REG,149) + always @ (posedge clk or posedge areset) + begin + if (areset) + begin + redist5_yForPe_uid36_fpSqrtTest_b_4_sticky_ena_q <= 1'b0; + end + else if (redist5_yForPe_uid36_fpSqrtTest_b_4_nor_q == 1'b1) + begin + redist5_yForPe_uid36_fpSqrtTest_b_4_sticky_ena_q <= redist5_yForPe_uid36_fpSqrtTest_b_4_cmpReg_q; + end + end + + // redist5_yForPe_uid36_fpSqrtTest_b_4_enaAnd(LOGICAL,150) + assign redist5_yForPe_uid36_fpSqrtTest_b_4_enaAnd_q = redist5_yForPe_uid36_fpSqrtTest_b_4_sticky_ena_q & en; + + // redist5_yForPe_uid36_fpSqrtTest_b_4_rdcnt(COUNTER,141) + // low=0, high=2, step=1, init=0 + always @ (posedge clk or posedge areset) + begin + if (areset) + begin + redist5_yForPe_uid36_fpSqrtTest_b_4_rdcnt_i <= 2'd0; + redist5_yForPe_uid36_fpSqrtTest_b_4_rdcnt_eq <= 1'b0; + end + else if (en == 1'b1) + begin + if (redist5_yForPe_uid36_fpSqrtTest_b_4_rdcnt_i == 2'd1) + begin + redist5_yForPe_uid36_fpSqrtTest_b_4_rdcnt_eq <= 1'b1; + end + else + begin + redist5_yForPe_uid36_fpSqrtTest_b_4_rdcnt_eq <= 1'b0; + end + if (redist5_yForPe_uid36_fpSqrtTest_b_4_rdcnt_eq == 1'b1) + begin + redist5_yForPe_uid36_fpSqrtTest_b_4_rdcnt_i <= $unsigned(redist5_yForPe_uid36_fpSqrtTest_b_4_rdcnt_i) + $unsigned(2'd2); + end + else + begin + redist5_yForPe_uid36_fpSqrtTest_b_4_rdcnt_i <= $unsigned(redist5_yForPe_uid36_fpSqrtTest_b_4_rdcnt_i) + $unsigned(2'd1); + end + end + end + assign redist5_yForPe_uid36_fpSqrtTest_b_4_rdcnt_q = redist5_yForPe_uid36_fpSqrtTest_b_4_rdcnt_i[1:0]; + + // redist5_yForPe_uid36_fpSqrtTest_b_4_rdmux(MUX,142) + assign redist5_yForPe_uid36_fpSqrtTest_b_4_rdmux_s = en; + always @(redist5_yForPe_uid36_fpSqrtTest_b_4_rdmux_s or redist5_yForPe_uid36_fpSqrtTest_b_4_wraddr_q or redist5_yForPe_uid36_fpSqrtTest_b_4_rdcnt_q) + begin + unique case (redist5_yForPe_uid36_fpSqrtTest_b_4_rdmux_s) + 1'b0 : redist5_yForPe_uid36_fpSqrtTest_b_4_rdmux_q = redist5_yForPe_uid36_fpSqrtTest_b_4_wraddr_q; + 1'b1 : redist5_yForPe_uid36_fpSqrtTest_b_4_rdmux_q = redist5_yForPe_uid36_fpSqrtTest_b_4_rdcnt_q; + default : redist5_yForPe_uid36_fpSqrtTest_b_4_rdmux_q = 2'b0; + endcase + end + + // redist5_yForPe_uid36_fpSqrtTest_b_4_wraddr(REG,143) + always @ (posedge clk or posedge areset) + begin + if (areset) + begin + redist5_yForPe_uid36_fpSqrtTest_b_4_wraddr_q <= 2'b10; + end + else + begin + redist5_yForPe_uid36_fpSqrtTest_b_4_wraddr_q <= redist5_yForPe_uid36_fpSqrtTest_b_4_rdmux_q; + end + end + + // redist5_yForPe_uid36_fpSqrtTest_b_4_mem(DUALMEM,140) + assign redist5_yForPe_uid36_fpSqrtTest_b_4_mem_ia = yForPe_uid36_fpSqrtTest_b; + assign redist5_yForPe_uid36_fpSqrtTest_b_4_mem_aa = redist5_yForPe_uid36_fpSqrtTest_b_4_wraddr_q; + assign redist5_yForPe_uid36_fpSqrtTest_b_4_mem_ab = redist5_yForPe_uid36_fpSqrtTest_b_4_rdmux_q; + assign redist5_yForPe_uid36_fpSqrtTest_b_4_mem_reset0 = areset; + altera_syncram #( + .ram_block_type("MLAB"), + .operation_mode("DUAL_PORT"), + .width_a(16), + .widthad_a(2), + .numwords_a(3), + .width_b(16), + .widthad_b(2), + .numwords_b(3), + .lpm_type("altera_syncram"), + .width_byteena_a(1), + .address_reg_b("CLOCK0"), + .indata_reg_b("CLOCK0"), + .rdcontrol_reg_b("CLOCK0"), + .byteena_reg_b("CLOCK0"), + .outdata_reg_b("CLOCK1"), + .outdata_aclr_b("CLEAR1"), + .clock_enable_input_a("NORMAL"), + .clock_enable_input_b("NORMAL"), + .clock_enable_output_b("NORMAL"), + .read_during_write_mode_mixed_ports("DONT_CARE"), + .power_up_uninitialized("TRUE"), + .intended_device_family("Arria 10") + ) redist5_yForPe_uid36_fpSqrtTest_b_4_mem_dmem ( + .clocken1(redist5_yForPe_uid36_fpSqrtTest_b_4_enaAnd_q[0]), + .clocken0(VCC_q[0]), + .clock0(clk), + .aclr1(redist5_yForPe_uid36_fpSqrtTest_b_4_mem_reset0), + .clock1(clk), + .address_a(redist5_yForPe_uid36_fpSqrtTest_b_4_mem_aa), + .data_a(redist5_yForPe_uid36_fpSqrtTest_b_4_mem_ia), + .wren_a(en[0]), + .address_b(redist5_yForPe_uid36_fpSqrtTest_b_4_mem_ab), + .q_b(redist5_yForPe_uid36_fpSqrtTest_b_4_mem_iq), + .wren_b(), + .rden_a(), + .rden_b(), + .data_b(), + .clocken2(), + .clocken3(), + .aclr0(), + .addressstall_a(), + .addressstall_b(), + .byteena_a(), + .byteena_b(), + .eccencbypass(), + .eccencparity(), + .sclr(), + .address2_a(), + .address2_b(), + .q_a(), + .eccstatus() + ); + assign redist5_yForPe_uid36_fpSqrtTest_b_4_mem_q = redist5_yForPe_uid36_fpSqrtTest_b_4_mem_iq[15:0]; + + // prodXY_uid116_pT2_uid107_invPolyEval_cma(CHAINMULTADD,123)@6 + 3 + assign prodXY_uid116_pT2_uid107_invPolyEval_cma_reset = areset; + assign prodXY_uid116_pT2_uid107_invPolyEval_cma_ena0 = en[0]; + assign prodXY_uid116_pT2_uid107_invPolyEval_cma_ena1 = prodXY_uid116_pT2_uid107_invPolyEval_cma_ena0; + assign prodXY_uid116_pT2_uid107_invPolyEval_cma_ena2 = prodXY_uid116_pT2_uid107_invPolyEval_cma_ena0; + assign prodXY_uid116_pT2_uid107_invPolyEval_cma_l[0] = $signed({1'b0, prodXY_uid116_pT2_uid107_invPolyEval_cma_a1[0][15:0]}); + assign prodXY_uid116_pT2_uid107_invPolyEval_cma_p[0] = prodXY_uid116_pT2_uid107_invPolyEval_cma_l[0] * prodXY_uid116_pT2_uid107_invPolyEval_cma_c1[0]; + assign prodXY_uid116_pT2_uid107_invPolyEval_cma_u[0] = prodXY_uid116_pT2_uid107_invPolyEval_cma_p[0][39:0]; + assign prodXY_uid116_pT2_uid107_invPolyEval_cma_w[0] = prodXY_uid116_pT2_uid107_invPolyEval_cma_u[0]; + assign prodXY_uid116_pT2_uid107_invPolyEval_cma_x[0] = prodXY_uid116_pT2_uid107_invPolyEval_cma_w[0]; + assign prodXY_uid116_pT2_uid107_invPolyEval_cma_y[0] = prodXY_uid116_pT2_uid107_invPolyEval_cma_x[0]; + always @ (posedge clk or posedge areset) + begin + if (areset) + begin + prodXY_uid116_pT2_uid107_invPolyEval_cma_a0 <= '{default: '0}; + prodXY_uid116_pT2_uid107_invPolyEval_cma_c0 <= '{default: '0}; + end + else + begin + if (prodXY_uid116_pT2_uid107_invPolyEval_cma_ena0 == 1'b1) + begin + prodXY_uid116_pT2_uid107_invPolyEval_cma_a0[0] <= redist5_yForPe_uid36_fpSqrtTest_b_4_mem_q; + prodXY_uid116_pT2_uid107_invPolyEval_cma_c0[0] <= s1_uid105_invPolyEval_q; + end + end + end + always @ (posedge clk or posedge areset) + begin + if (areset) + begin + prodXY_uid116_pT2_uid107_invPolyEval_cma_a1 <= '{default: '0}; + prodXY_uid116_pT2_uid107_invPolyEval_cma_c1 <= '{default: '0}; + end + else + begin + if (prodXY_uid116_pT2_uid107_invPolyEval_cma_ena2 == 1'b1) + begin + prodXY_uid116_pT2_uid107_invPolyEval_cma_a1 <= prodXY_uid116_pT2_uid107_invPolyEval_cma_a0; + prodXY_uid116_pT2_uid107_invPolyEval_cma_c1 <= prodXY_uid116_pT2_uid107_invPolyEval_cma_c0; + end + end + end + always @ (posedge clk or posedge areset) + begin + if (areset) + begin + prodXY_uid116_pT2_uid107_invPolyEval_cma_s <= '{default: '0}; + end + else + begin + if (prodXY_uid116_pT2_uid107_invPolyEval_cma_ena1 == 1'b1) + begin + prodXY_uid116_pT2_uid107_invPolyEval_cma_s[0] <= prodXY_uid116_pT2_uid107_invPolyEval_cma_y[0]; + end + end + end + dspba_delay_ver #( .width(39), .depth(0), .reset_kind("ASYNC") ) + prodXY_uid116_pT2_uid107_invPolyEval_cma_delay ( .xin(prodXY_uid116_pT2_uid107_invPolyEval_cma_s[0][38:0]), .xout(prodXY_uid116_pT2_uid107_invPolyEval_cma_qq), .ena(en[0]), .clk(clk), .aclr(areset) ); + assign prodXY_uid116_pT2_uid107_invPolyEval_cma_q = prodXY_uid116_pT2_uid107_invPolyEval_cma_qq[38:0]; + + // osig_uid117_pT2_uid107_invPolyEval(BITSELECT,116)@9 + assign osig_uid117_pT2_uid107_invPolyEval_b = prodXY_uid116_pT2_uid107_invPolyEval_cma_q[38:15]; + + // highBBits_uid109_invPolyEval(BITSELECT,108)@9 + assign highBBits_uid109_invPolyEval_b = osig_uid117_pT2_uid107_invPolyEval_b[23:2]; + + // redist7_yAddr_uid35_fpSqrtTest_b_7(DELAY,132) + dspba_delay_ver #( .width(8), .depth(4), .reset_kind("ASYNC") ) + redist7_yAddr_uid35_fpSqrtTest_b_7 ( .xin(redist6_yAddr_uid35_fpSqrtTest_b_3_q), .xout(redist7_yAddr_uid35_fpSqrtTest_b_7_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // memoryC0_uid88_sqrtTables_lutmem(DUALMEM,118)@7 + 2 + // in j@20000000 + assign memoryC0_uid88_sqrtTables_lutmem_aa = redist7_yAddr_uid35_fpSqrtTest_b_7_q; + assign memoryC0_uid88_sqrtTables_lutmem_reset0 = areset; + altera_syncram #( + .ram_block_type("M20K"), + .operation_mode("ROM"), + .width_a(29), + .widthad_a(8), + .numwords_a(256), + .lpm_type("altera_syncram"), + .width_byteena_a(1), + .outdata_reg_a("CLOCK0"), + .outdata_aclr_a("CLEAR0"), + .clock_enable_input_a("NORMAL"), + .power_up_uninitialized("FALSE"), + .init_file("acl_fsqrt_memoryC0_uid88_sqrtTables_lutmem.hex"), + .init_file_layout("PORT_A"), + .intended_device_family("Arria 10") + ) memoryC0_uid88_sqrtTables_lutmem_dmem ( + .clocken0(en[0]), + .aclr0(memoryC0_uid88_sqrtTables_lutmem_reset0), + .clock0(clk), + .address_a(memoryC0_uid88_sqrtTables_lutmem_aa), + .q_a(memoryC0_uid88_sqrtTables_lutmem_ir), + .wren_a(), + .wren_b(), + .rden_a(), + .rden_b(), + .data_a(), + .data_b(), + .address_b(), + .clock1(), + .clocken1(), + .clocken2(), + .clocken3(), + .aclr1(), + .addressstall_a(), + .addressstall_b(), + .byteena_a(), + .byteena_b(), + .eccencbypass(), + .eccencparity(), + .sclr(), + .address2_a(), + .address2_b(), + .q_b(), + .eccstatus() + ); + assign memoryC0_uid88_sqrtTables_lutmem_r = memoryC0_uid88_sqrtTables_lutmem_ir[28:0]; + + // s2sumAHighB_uid110_invPolyEval(ADD,109)@9 + assign s2sumAHighB_uid110_invPolyEval_a = {{1{memoryC0_uid88_sqrtTables_lutmem_r[28]}}, memoryC0_uid88_sqrtTables_lutmem_r}; + assign s2sumAHighB_uid110_invPolyEval_b = {{8{highBBits_uid109_invPolyEval_b[21]}}, highBBits_uid109_invPolyEval_b}; + assign s2sumAHighB_uid110_invPolyEval_o = $signed(s2sumAHighB_uid110_invPolyEval_a) + $signed(s2sumAHighB_uid110_invPolyEval_b); + assign s2sumAHighB_uid110_invPolyEval_q = s2sumAHighB_uid110_invPolyEval_o[29:0]; + + // lowRangeB_uid108_invPolyEval(BITSELECT,107)@9 + assign lowRangeB_uid108_invPolyEval_in = osig_uid117_pT2_uid107_invPolyEval_b[1:0]; + assign lowRangeB_uid108_invPolyEval_b = lowRangeB_uid108_invPolyEval_in[1:0]; + + // s2_uid111_invPolyEval(BITJOIN,110)@9 + assign s2_uid111_invPolyEval_q = {s2sumAHighB_uid110_invPolyEval_q, lowRangeB_uid108_invPolyEval_b}; + + // fracRPreCR_uid39_fpSqrtTest(BITSELECT,38)@9 + assign fracRPreCR_uid39_fpSqrtTest_in = s2_uid111_invPolyEval_q[28:0]; + assign fracRPreCR_uid39_fpSqrtTest_b = fracRPreCR_uid39_fpSqrtTest_in[28:5]; + + // redist2_fracRPreCR_uid39_fpSqrtTest_b_1(DELAY,127) + dspba_delay_ver #( .width(24), .depth(1), .reset_kind("ASYNC") ) + redist2_fracRPreCR_uid39_fpSqrtTest_b_1 ( .xin(fracRPreCR_uid39_fpSqrtTest_b), .xout(redist2_fracRPreCR_uid39_fpSqrtTest_b_1_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // fracPaddingOne_uid41_fpSqrtTest(BITJOIN,40)@10 + assign fracPaddingOne_uid41_fpSqrtTest_q = {VCC_q, redist2_fracRPreCR_uid39_fpSqrtTest_b_1_q}; + + // squaredResult_uid42_fpSqrtTest_cma(CHAINMULTADD,121)@10 + 3 + assign squaredResult_uid42_fpSqrtTest_cma_reset = areset; + assign squaredResult_uid42_fpSqrtTest_cma_ena0 = en[0]; + assign squaredResult_uid42_fpSqrtTest_cma_ena1 = squaredResult_uid42_fpSqrtTest_cma_ena0; + assign squaredResult_uid42_fpSqrtTest_cma_ena2 = squaredResult_uid42_fpSqrtTest_cma_ena0; + assign squaredResult_uid42_fpSqrtTest_cma_p[0] = squaredResult_uid42_fpSqrtTest_cma_a1[0] * squaredResult_uid42_fpSqrtTest_cma_c1[0]; + assign squaredResult_uid42_fpSqrtTest_cma_u[0] = squaredResult_uid42_fpSqrtTest_cma_p[0][49:0]; + assign squaredResult_uid42_fpSqrtTest_cma_w[0] = squaredResult_uid42_fpSqrtTest_cma_u[0]; + assign squaredResult_uid42_fpSqrtTest_cma_x[0] = squaredResult_uid42_fpSqrtTest_cma_w[0]; + assign squaredResult_uid42_fpSqrtTest_cma_y[0] = squaredResult_uid42_fpSqrtTest_cma_x[0]; + always @ (posedge clk or posedge areset) + begin + if (areset) + begin + squaredResult_uid42_fpSqrtTest_cma_a0 <= '{default: '0}; + squaredResult_uid42_fpSqrtTest_cma_c0 <= '{default: '0}; + end + else + begin + if (squaredResult_uid42_fpSqrtTest_cma_ena0 == 1'b1) + begin + squaredResult_uid42_fpSqrtTest_cma_a0[0] <= fracPaddingOne_uid41_fpSqrtTest_q; + squaredResult_uid42_fpSqrtTest_cma_c0[0] <= fracPaddingOne_uid41_fpSqrtTest_q; + end + end + end + always @ (posedge clk or posedge areset) + begin + if (areset) + begin + squaredResult_uid42_fpSqrtTest_cma_a1 <= '{default: '0}; + squaredResult_uid42_fpSqrtTest_cma_c1 <= '{default: '0}; + end + else + begin + if (squaredResult_uid42_fpSqrtTest_cma_ena2 == 1'b1) + begin + squaredResult_uid42_fpSqrtTest_cma_a1 <= squaredResult_uid42_fpSqrtTest_cma_a0; + squaredResult_uid42_fpSqrtTest_cma_c1 <= squaredResult_uid42_fpSqrtTest_cma_c0; + end + end + end + always @ (posedge clk or posedge areset) + begin + if (areset) + begin + squaredResult_uid42_fpSqrtTest_cma_s <= '{default: '0}; + end + else + begin + if (squaredResult_uid42_fpSqrtTest_cma_ena1 == 1'b1) + begin + squaredResult_uid42_fpSqrtTest_cma_s[0] <= squaredResult_uid42_fpSqrtTest_cma_y[0]; + end + end + end + dspba_delay_ver #( .width(50), .depth(0), .reset_kind("ASYNC") ) + squaredResult_uid42_fpSqrtTest_cma_delay ( .xin(squaredResult_uid42_fpSqrtTest_cma_s[0][49:0]), .xout(squaredResult_uid42_fpSqrtTest_cma_qq), .ena(en[0]), .clk(clk), .aclr(areset) ); + assign squaredResult_uid42_fpSqrtTest_cma_q = squaredResult_uid42_fpSqrtTest_cma_qq[49:0]; + + // squaredResultGTEIn_uid55_fpSqrtTest(COMPARE,56)@13 + 1 + assign squaredResultGTEIn_uid55_fpSqrtTest_a = {2'b00, squaredResult_uid42_fpSqrtTest_cma_q}; + assign squaredResultGTEIn_uid55_fpSqrtTest_b = {2'b00, updatedY_uid56_fpSqrtTest_q}; + always @ (posedge clk or posedge areset) + begin + if (areset) + begin + squaredResultGTEIn_uid55_fpSqrtTest_o <= 52'b0; + end + else if (en == 1'b1) + begin + squaredResultGTEIn_uid55_fpSqrtTest_o <= $unsigned(squaredResultGTEIn_uid55_fpSqrtTest_a) - $unsigned(squaredResultGTEIn_uid55_fpSqrtTest_b); + end + end + assign squaredResultGTEIn_uid55_fpSqrtTest_n[0] = ~ (squaredResultGTEIn_uid55_fpSqrtTest_o[51]); + + // pLTOne_uid58_fpSqrtTest(LOGICAL,57)@14 + assign pLTOne_uid58_fpSqrtTest_q = ~ (squaredResultGTEIn_uid55_fpSqrtTest_n); + + // redist3_fracRPreCR_uid39_fpSqrtTest_b_5_inputreg(DELAY,139) + dspba_delay_ver #( .width(24), .depth(1), .reset_kind("ASYNC") ) + redist3_fracRPreCR_uid39_fpSqrtTest_b_5_inputreg ( .xin(redist2_fracRPreCR_uid39_fpSqrtTest_b_1_q), .xout(redist3_fracRPreCR_uid39_fpSqrtTest_b_5_inputreg_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // redist3_fracRPreCR_uid39_fpSqrtTest_b_5(DELAY,128) + dspba_delay_ver #( .width(24), .depth(3), .reset_kind("ASYNC") ) + redist3_fracRPreCR_uid39_fpSqrtTest_b_5 ( .xin(redist3_fracRPreCR_uid39_fpSqrtTest_b_5_inputreg_q), .xout(redist3_fracRPreCR_uid39_fpSqrtTest_b_5_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // fxpSqrtResPostUpdateE_uid60_fpSqrtTest(ADD,59)@14 + assign fxpSqrtResPostUpdateE_uid60_fpSqrtTest_a = {1'b0, redist3_fracRPreCR_uid39_fpSqrtTest_b_5_q}; + assign fxpSqrtResPostUpdateE_uid60_fpSqrtTest_b = {24'b000000000000000000000000, pLTOne_uid58_fpSqrtTest_q}; + assign fxpSqrtResPostUpdateE_uid60_fpSqrtTest_o = $unsigned(fxpSqrtResPostUpdateE_uid60_fpSqrtTest_a) + $unsigned(fxpSqrtResPostUpdateE_uid60_fpSqrtTest_b); + assign fxpSqrtResPostUpdateE_uid60_fpSqrtTest_q = fxpSqrtResPostUpdateE_uid60_fpSqrtTest_o[24:0]; + + // expUpdateCRU_uid61_fpSqrtTest_merged_bit_select(BITSELECT,124)@14 + assign expUpdateCRU_uid61_fpSqrtTest_merged_bit_select_b = fxpSqrtResPostUpdateE_uid60_fpSqrtTest_q[24:24]; + assign expUpdateCRU_uid61_fpSqrtTest_merged_bit_select_c = fxpSqrtResPostUpdateE_uid60_fpSqrtTest_q[23:1]; + + // fracPENotOne_uid62_fpSqrtTest(LOGICAL,61)@14 + assign fracPENotOne_uid62_fpSqrtTest_q = ~ (redist4_expIncPEOnly_uid38_fpSqrtTest_b_5_q); + + // fracPENotOneAndCRRoundsExp_uid63_fpSqrtTest(LOGICAL,62)@14 + assign fracPENotOneAndCRRoundsExp_uid63_fpSqrtTest_q = fracPENotOne_uid62_fpSqrtTest_q & expUpdateCRU_uid61_fpSqrtTest_merged_bit_select_b; + + // expIncPEOnly_uid38_fpSqrtTest(BITSELECT,37)@9 + assign expIncPEOnly_uid38_fpSqrtTest_in = s2_uid111_invPolyEval_q[30:0]; + assign expIncPEOnly_uid38_fpSqrtTest_b = expIncPEOnly_uid38_fpSqrtTest_in[30:30]; + + // redist4_expIncPEOnly_uid38_fpSqrtTest_b_5(DELAY,129) + dspba_delay_ver #( .width(1), .depth(5), .reset_kind("ASYNC") ) + redist4_expIncPEOnly_uid38_fpSqrtTest_b_5 ( .xin(expIncPEOnly_uid38_fpSqrtTest_b), .xout(redist4_expIncPEOnly_uid38_fpSqrtTest_b_5_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // expInc_uid64_fpSqrtTest(LOGICAL,63)@14 + 1 + assign expInc_uid64_fpSqrtTest_qi = redist4_expIncPEOnly_uid38_fpSqrtTest_b_5_q | fracPENotOneAndCRRoundsExp_uid63_fpSqrtTest_q; + dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") ) + expInc_uid64_fpSqrtTest_delay ( .xin(expInc_uid64_fpSqrtTest_qi), .xout(expInc_uid64_fpSqrtTest_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // sBiasM1_uid26_fpSqrtTest(CONSTANT,25) + assign sBiasM1_uid26_fpSqrtTest_q = 8'b01111110; + + // expOddSig_uid27_fpSqrtTest(ADD,26)@13 + assign expOddSig_uid27_fpSqrtTest_a = {1'b0, redist13_expX_uid6_fpSqrtTest_b_13_outputreg_q}; + assign expOddSig_uid27_fpSqrtTest_b = {1'b0, sBiasM1_uid26_fpSqrtTest_q}; + assign expOddSig_uid27_fpSqrtTest_o = $unsigned(expOddSig_uid27_fpSqrtTest_a) + $unsigned(expOddSig_uid27_fpSqrtTest_b); + assign expOddSig_uid27_fpSqrtTest_q = expOddSig_uid27_fpSqrtTest_o[8:0]; + + // expROdd_uid28_fpSqrtTest(BITSELECT,27)@13 + assign expROdd_uid28_fpSqrtTest_b = expOddSig_uid27_fpSqrtTest_q[8:1]; + + // sBias_uid22_fpSqrtTest(CONSTANT,21) + assign sBias_uid22_fpSqrtTest_q = 8'b01111111; + + // expEvenSig_uid24_fpSqrtTest(ADD,23)@13 + assign expEvenSig_uid24_fpSqrtTest_a = {1'b0, redist13_expX_uid6_fpSqrtTest_b_13_outputreg_q}; + assign expEvenSig_uid24_fpSqrtTest_b = {1'b0, sBias_uid22_fpSqrtTest_q}; + assign expEvenSig_uid24_fpSqrtTest_o = $unsigned(expEvenSig_uid24_fpSqrtTest_a) + $unsigned(expEvenSig_uid24_fpSqrtTest_b); + assign expEvenSig_uid24_fpSqrtTest_q = expEvenSig_uid24_fpSqrtTest_o[8:0]; + + // expREven_uid25_fpSqrtTest(BITSELECT,24)@13 + assign expREven_uid25_fpSqrtTest_b = expEvenSig_uid24_fpSqrtTest_q[8:1]; + + // expRMux_uid31_fpSqrtTest(MUX,30)@13 + 1 + assign expRMux_uid31_fpSqrtTest_s = redist9_expOddSelect_uid30_fpSqrtTest_q_13_q; + always @ (posedge clk or posedge areset) + begin + if (areset) + begin + expRMux_uid31_fpSqrtTest_q <= 8'b0; + end + else if (en == 1'b1) + begin + unique case (expRMux_uid31_fpSqrtTest_s) + 1'b0 : expRMux_uid31_fpSqrtTest_q <= expREven_uid25_fpSqrtTest_b; + 1'b1 : expRMux_uid31_fpSqrtTest_q <= expROdd_uid28_fpSqrtTest_b; + default : expRMux_uid31_fpSqrtTest_q <= 8'b0; + endcase + end + end + + // redist8_expRMux_uid31_fpSqrtTest_q_2(DELAY,133) + dspba_delay_ver #( .width(8), .depth(1), .reset_kind("ASYNC") ) + redist8_expRMux_uid31_fpSqrtTest_q_2 ( .xin(expRMux_uid31_fpSqrtTest_q), .xout(redist8_expRMux_uid31_fpSqrtTest_q_2_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // expR_uid66_fpSqrtTest(ADD,65)@15 + assign expR_uid66_fpSqrtTest_a = {1'b0, redist8_expRMux_uid31_fpSqrtTest_q_2_q}; + assign expR_uid66_fpSqrtTest_b = {8'b00000000, expInc_uid64_fpSqrtTest_q}; + assign expR_uid66_fpSqrtTest_o = $unsigned(expR_uid66_fpSqrtTest_a) + $unsigned(expR_uid66_fpSqrtTest_b); + assign expR_uid66_fpSqrtTest_q = expR_uid66_fpSqrtTest_o[8:0]; + + // expRR_uid77_fpSqrtTest(BITSELECT,76)@15 + assign expRR_uid77_fpSqrtTest_in = expR_uid66_fpSqrtTest_q[7:0]; + assign expRR_uid77_fpSqrtTest_b = expRR_uid77_fpSqrtTest_in[7:0]; + + // expXIsMax_uid14_fpSqrtTest(LOGICAL,13)@13 + 1 + assign expXIsMax_uid14_fpSqrtTest_qi = redist13_expX_uid6_fpSqrtTest_b_13_outputreg_q == cstAllOWE_uid8_fpSqrtTest_q ? 1'b1 : 1'b0; + dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") ) + expXIsMax_uid14_fpSqrtTest_delay ( .xin(expXIsMax_uid14_fpSqrtTest_qi), .xout(expXIsMax_uid14_fpSqrtTest_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // invExpXIsMax_uid19_fpSqrtTest(LOGICAL,18)@14 + assign invExpXIsMax_uid19_fpSqrtTest_q = ~ (expXIsMax_uid14_fpSqrtTest_q); + + // InvExpXIsZero_uid20_fpSqrtTest(LOGICAL,19)@14 + assign InvExpXIsZero_uid20_fpSqrtTest_q = ~ (excZ_x_uid13_fpSqrtTest_q); + + // excR_x_uid21_fpSqrtTest(LOGICAL,20)@14 + assign excR_x_uid21_fpSqrtTest_q = InvExpXIsZero_uid20_fpSqrtTest_q & invExpXIsMax_uid19_fpSqrtTest_q; + + // minReg_uid69_fpSqrtTest(LOGICAL,68)@14 + assign minReg_uid69_fpSqrtTest_q = excR_x_uid21_fpSqrtTest_q & redist12_signX_uid7_fpSqrtTest_b_14_q; + + // cstZeroWF_uid9_fpSqrtTest(CONSTANT,8) + assign cstZeroWF_uid9_fpSqrtTest_q = 23'b00000000000000000000000; + + // fracXIsZero_uid15_fpSqrtTest(LOGICAL,14)@13 + 1 + assign fracXIsZero_uid15_fpSqrtTest_qi = cstZeroWF_uid9_fpSqrtTest_q == redist11_frac_x_uid12_fpSqrtTest_b_13_outputreg_q ? 1'b1 : 1'b0; + dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") ) + fracXIsZero_uid15_fpSqrtTest_delay ( .xin(fracXIsZero_uid15_fpSqrtTest_qi), .xout(fracXIsZero_uid15_fpSqrtTest_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // excI_x_uid17_fpSqrtTest(LOGICAL,16)@14 + assign excI_x_uid17_fpSqrtTest_q = expXIsMax_uid14_fpSqrtTest_q & fracXIsZero_uid15_fpSqrtTest_q; + + // minInf_uid70_fpSqrtTest(LOGICAL,69)@14 + assign minInf_uid70_fpSqrtTest_q = excI_x_uid17_fpSqrtTest_q & redist12_signX_uid7_fpSqrtTest_b_14_q; + + // fracXIsNotZero_uid16_fpSqrtTest(LOGICAL,15)@14 + assign fracXIsNotZero_uid16_fpSqrtTest_q = ~ (fracXIsZero_uid15_fpSqrtTest_q); + + // excN_x_uid18_fpSqrtTest(LOGICAL,17)@14 + assign excN_x_uid18_fpSqrtTest_q = expXIsMax_uid14_fpSqrtTest_q & fracXIsNotZero_uid16_fpSqrtTest_q; + + // excRNaN_uid71_fpSqrtTest(LOGICAL,70)@14 + assign excRNaN_uid71_fpSqrtTest_q = excN_x_uid18_fpSqrtTest_q | minInf_uid70_fpSqrtTest_q | minReg_uid69_fpSqrtTest_q; + + // invSignX_uid67_fpSqrtTest(LOGICAL,66)@14 + assign invSignX_uid67_fpSqrtTest_q = ~ (redist12_signX_uid7_fpSqrtTest_b_14_q); + + // inInfAndNotNeg_uid68_fpSqrtTest(LOGICAL,67)@14 + assign inInfAndNotNeg_uid68_fpSqrtTest_q = excI_x_uid17_fpSqrtTest_q & invSignX_uid67_fpSqrtTest_q; + + // excConc_uid72_fpSqrtTest(BITJOIN,71)@14 + assign excConc_uid72_fpSqrtTest_q = {excRNaN_uid71_fpSqrtTest_q, inInfAndNotNeg_uid68_fpSqrtTest_q, excZ_x_uid13_fpSqrtTest_q}; + + // fracSelIn_uid73_fpSqrtTest(BITJOIN,72)@14 + assign fracSelIn_uid73_fpSqrtTest_q = {redist12_signX_uid7_fpSqrtTest_b_14_q, excConc_uid72_fpSqrtTest_q}; + + // fracSel_uid74_fpSqrtTest(LOOKUP,73)@14 + 1 + always @ (posedge clk or posedge areset) + begin + if (areset) + begin + fracSel_uid74_fpSqrtTest_q <= 2'b01; + end + else if (en == 1'b1) + begin + unique case (fracSelIn_uid73_fpSqrtTest_q) + 4'b0000 : fracSel_uid74_fpSqrtTest_q <= 2'b01; + 4'b0001 : fracSel_uid74_fpSqrtTest_q <= 2'b00; + 4'b0010 : fracSel_uid74_fpSqrtTest_q <= 2'b10; + 4'b0011 : fracSel_uid74_fpSqrtTest_q <= 2'b00; + 4'b0100 : fracSel_uid74_fpSqrtTest_q <= 2'b11; + 4'b0101 : fracSel_uid74_fpSqrtTest_q <= 2'b00; + 4'b0110 : fracSel_uid74_fpSqrtTest_q <= 2'b10; + 4'b0111 : fracSel_uid74_fpSqrtTest_q <= 2'b00; + 4'b1000 : fracSel_uid74_fpSqrtTest_q <= 2'b11; + 4'b1001 : fracSel_uid74_fpSqrtTest_q <= 2'b00; + 4'b1010 : fracSel_uid74_fpSqrtTest_q <= 2'b11; + 4'b1011 : fracSel_uid74_fpSqrtTest_q <= 2'b11; + 4'b1100 : fracSel_uid74_fpSqrtTest_q <= 2'b11; + 4'b1101 : fracSel_uid74_fpSqrtTest_q <= 2'b11; + 4'b1110 : fracSel_uid74_fpSqrtTest_q <= 2'b11; + 4'b1111 : fracSel_uid74_fpSqrtTest_q <= 2'b11; + default : begin + // unreachable + fracSel_uid74_fpSqrtTest_q <= 2'bxx; + end + endcase + end + end + + // expRPostExc_uid79_fpSqrtTest(MUX,78)@15 + assign expRPostExc_uid79_fpSqrtTest_s = fracSel_uid74_fpSqrtTest_q; + always @(expRPostExc_uid79_fpSqrtTest_s or en or cstAllZWE_uid10_fpSqrtTest_q or expRR_uid77_fpSqrtTest_b or cstAllOWE_uid8_fpSqrtTest_q) + begin + unique case (expRPostExc_uid79_fpSqrtTest_s) + 2'b00 : expRPostExc_uid79_fpSqrtTest_q = cstAllZWE_uid10_fpSqrtTest_q; + 2'b01 : expRPostExc_uid79_fpSqrtTest_q = expRR_uid77_fpSqrtTest_b; + 2'b10 : expRPostExc_uid79_fpSqrtTest_q = cstAllOWE_uid8_fpSqrtTest_q; + 2'b11 : expRPostExc_uid79_fpSqrtTest_q = cstAllOWE_uid8_fpSqrtTest_q; + default : expRPostExc_uid79_fpSqrtTest_q = 8'b0; + endcase + end + + // fracNaN_uid80_fpSqrtTest(CONSTANT,79) + assign fracNaN_uid80_fpSqrtTest_q = 23'b00000000000000000000001; + + // redist0_expUpdateCRU_uid61_fpSqrtTest_merged_bit_select_c_1(DELAY,125) + dspba_delay_ver #( .width(23), .depth(1), .reset_kind("ASYNC") ) + redist0_expUpdateCRU_uid61_fpSqrtTest_merged_bit_select_c_1 ( .xin(expUpdateCRU_uid61_fpSqrtTest_merged_bit_select_c), .xout(redist0_expUpdateCRU_uid61_fpSqrtTest_merged_bit_select_c_1_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // fracRPostExc_uid84_fpSqrtTest(MUX,83)@15 + assign fracRPostExc_uid84_fpSqrtTest_s = fracSel_uid74_fpSqrtTest_q; + always @(fracRPostExc_uid84_fpSqrtTest_s or en or cstZeroWF_uid9_fpSqrtTest_q or redist0_expUpdateCRU_uid61_fpSqrtTest_merged_bit_select_c_1_q or fracNaN_uid80_fpSqrtTest_q) + begin + unique case (fracRPostExc_uid84_fpSqrtTest_s) + 2'b00 : fracRPostExc_uid84_fpSqrtTest_q = cstZeroWF_uid9_fpSqrtTest_q; + 2'b01 : fracRPostExc_uid84_fpSqrtTest_q = redist0_expUpdateCRU_uid61_fpSqrtTest_merged_bit_select_c_1_q; + 2'b10 : fracRPostExc_uid84_fpSqrtTest_q = cstZeroWF_uid9_fpSqrtTest_q; + 2'b11 : fracRPostExc_uid84_fpSqrtTest_q = fracNaN_uid80_fpSqrtTest_q; + default : fracRPostExc_uid84_fpSqrtTest_q = 23'b0; + endcase + end + + // RSqrt_uid86_fpSqrtTest(BITJOIN,85)@15 + assign RSqrt_uid86_fpSqrtTest_q = {negZero_uid85_fpSqrtTest_q, expRPostExc_uid79_fpSqrtTest_q, fracRPostExc_uid84_fpSqrtTest_q}; + + // xOut(GPOUT,4)@15 + assign q = RSqrt_uid86_fpSqrtTest_q; + +endmodule diff --git a/hw/rtl/fp_cores/altera/acl_fsqrt_memoryC0_uid62_sqrtTables_lutmem.hex b/hw/rtl/fp_cores/altera/arria10/acl_fsqrt_memoryC0_uid88_sqrtTables_lutmem.hex similarity index 50% rename from hw/rtl/fp_cores/altera/acl_fsqrt_memoryC0_uid62_sqrtTables_lutmem.hex rename to hw/rtl/fp_cores/altera/arria10/acl_fsqrt_memoryC0_uid88_sqrtTables_lutmem.hex index dacc8b55..dd873ae3 100644 --- a/hw/rtl/fp_cores/altera/acl_fsqrt_memoryC0_uid62_sqrtTables_lutmem.hex +++ b/hw/rtl/fp_cores/altera/arria10/acl_fsqrt_memoryC0_uid88_sqrtTables_lutmem.hex @@ -127,132 +127,132 @@ :04007D000B3F49F3F9 :04007E000B44F93AFC :04007F000B4AA5A5DE -:040080000B504F3C96 -:040081000B5B99E894 -:040082000B66D966CA -:040083000B720DD619 -:040084000B7D375861 -:040085000B88560E80 -:040086000B936A145A -:040087000B9E738ACF -:040088000BA97290BE -:040089000BB4673E0F -:04008A000BBF51B6A1 -:04008B000BCA321456 -:04008C000BD5087018 -:04008D000BDFD4EAC7 -:04008E000BEA979A48 -:04008F000BF5509C81 -:040090000C00000858 -:040091000C0AA5FAB6 -:040092000C1542887F -:040093000C1FD5CE9B -:040094000C2A5FE2F1 -:040095000C34E0DC6B -:040096000C3F58D4EF -:040097000C49C7E267 -:040098000C542E1ABC -:040099000C5E8B96D8 -:04009A000C68E068A6 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b/hw/rtl/fp_cores/altera/arria10/acl_fsqrt_memoryC1_uid91_sqrtTables_lutmem.hex similarity index 57% rename from hw/rtl/fp_cores/altera/acl_fsqrt_memoryC1_uid65_sqrtTables_lutmem.hex rename to hw/rtl/fp_cores/altera/arria10/acl_fsqrt_memoryC1_uid91_sqrtTables_lutmem.hex index 7a6961dc..8706b134 100644 --- a/hw/rtl/fp_cores/altera/acl_fsqrt_memoryC1_uid65_sqrtTables_lutmem.hex +++ b/hw/rtl/fp_cores/altera/arria10/acl_fsqrt_memoryC1_uid91_sqrtTables_lutmem.hex @@ -127,132 +127,132 @@ :03007D0005B0B714 :03007E0005ADD9F4 :03007F0005AAFED1 -:030080000B504AD8 +:030080000B504DD5 :030081000B450C20 :030082000B39EE49 -:030083000B2EF24F -:030084000B241634 -:030085000B1956FE +:030083000B2EF34E +:030084000B241238 +:030085000B1955FF :030086000B0EB8A6 -:030087000B043A2D -:030088000AF9D0A2 -:030089000AEF90EB -:03008A000AE5661E -:03008B000ADB5637 -:03008C000AD1682E +:030087000B043433 +:030088000AF9D39F +:030089000AEF8BF0 +:03008A000AE56321 +:03008B000ADB5439 +:03008C000AD16432 :03008D000AC78E11 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:0200EB000DBC4A -:0200EC000DC045 -:0200ED000DC440 -:0200EE000DC241 -:0200EF000DCA38 -:0200F0000DCC35 +:0200EC000DBF46 +:0200ED000DC143 +:0200EE000DC53E +:0200EF000DCB37 +:0200F0000DCE33 :0200F1000DD030 -:0200F2000DD22D -:0200F3000DD826 +:0200F2000DD728 +:0200F3000DDA24 :0200F4000DDC21 -:0200F5000DDC20 -:0200F6000DDE1D -:0200F7000DE416 -:0200F8000DEC0D +:0200F5000DDF1D +:0200F6000DE417 +:0200F7000DE713 +:0200F8000DE910 :0200F9000DEC0C :0200FA000DEE09 -:0200FB000DF600 -:0200FC000DF401 -:0200FD000DF6FE -:0200FE000DF8FB -:0200FF000E02EF +:0200FB000DF006 +:0200FC000DF500 +:0200FD000DF9FB +:0200FE000DFCF7 +:0200FF000DFFF3 :00000001ff diff --git a/hw/rtl/fp_cores/altera/arria10/acl_fsub.sv b/hw/rtl/fp_cores/altera/arria10/acl_fsub.sv new file mode 100644 index 00000000..1d789b85 --- /dev/null +++ b/hw/rtl/fp_cores/altera/arria10/acl_fsub.sv @@ -0,0 +1,68 @@ +// ------------------------------------------------------------------------- +// High Level Design Compiler for Intel(R) FPGAs Version 17.1 (Release Build #273) +// Quartus Prime development tool and MATLAB/Simulink Interface +// +// Legal Notice: Copyright 2017 Intel Corporation. All rights reserved. +// Your use of Intel Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly +// subject to the terms and conditions of the Intel FPGA Software License +// Agreement, Intel MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for +// the sole purpose of programming logic devices manufactured by Intel +// and sold by Intel or its authorized distributors. Please refer to the +// applicable agreement for further details. +// --------------------------------------------------------------------------- + +// SystemVerilog created from acl_fsub +// SystemVerilog created on Sun Dec 27 09:47:20 2020 + + +(* altera_attribute = "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410; -name MESSAGE_DISABLE 113007; -name MESSAGE_DISABLE 10958" *) +module acl_fsub ( + input wire [31:0] a, + input wire [31:0] b, + input wire [0:0] en, + output wire [31:0] q, + input wire clk, + input wire areset + ); + + wire [31:0] fpSubTest_impl_ax0; + wire [31:0] fpSubTest_impl_ay0; + wire [31:0] fpSubTest_impl_q0; + wire fpSubTest_impl_reset0; + wire fpSubTest_impl_fpSubTest_impl_ena0; + + + // fpSubTest_impl(FPCOLUMN,5)@0 + // out q0@3 + assign fpSubTest_impl_ax0 = b; + assign fpSubTest_impl_ay0 = a; + assign fpSubTest_impl_reset0 = areset; + assign fpSubTest_impl_fpSubTest_impl_ena0 = en[0]; + twentynm_fp_mac #( + .operation_mode("sp_add"), + .adder_subtract("true"), + .ax_clock("0"), + .ay_clock("0"), + .adder_input_clock("0"), + .output_clock("0") + ) fpSubTest_impl_DSP0 ( + .aclr({ fpSubTest_impl_reset0, fpSubTest_impl_reset0 }), + .clk({1'b0,1'b0,clk}), + .ena({ 1'b0, 1'b0, fpSubTest_impl_fpSubTest_impl_ena0 }), + .ax(fpSubTest_impl_ax0), + .ay(fpSubTest_impl_ay0), + .resulta(fpSubTest_impl_q0), + .accumulate(), + .az(), + .chainin(), + .chainout() + ); + + // xOut(GPOUT,4)@3 + assign q = fpSubTest_impl_q0; + +endmodule diff --git a/hw/rtl/fp_cores/altera/acl_ftoi.sv b/hw/rtl/fp_cores/altera/arria10/acl_ftoi.sv similarity index 99% rename from hw/rtl/fp_cores/altera/acl_ftoi.sv rename to hw/rtl/fp_cores/altera/arria10/acl_ftoi.sv index 404dba69..46140a3e 100644 --- a/hw/rtl/fp_cores/altera/acl_ftoi.sv +++ b/hw/rtl/fp_cores/altera/arria10/acl_ftoi.sv @@ -16,7 +16,7 @@ // --------------------------------------------------------------------------- // SystemVerilog created from acl_ftoi -// SystemVerilog created on Wed Dec 9 01:17:51 2020 +// SystemVerilog created on Sun Dec 27 09:47:21 2020 (* altera_attribute = "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410; -name MESSAGE_DISABLE 113007; -name MESSAGE_DISABLE 10958" *) diff --git a/hw/rtl/fp_cores/altera/acl_ftou.sv b/hw/rtl/fp_cores/altera/arria10/acl_ftou.sv similarity index 99% rename from hw/rtl/fp_cores/altera/acl_ftou.sv rename to hw/rtl/fp_cores/altera/arria10/acl_ftou.sv index b182e8e9..65a973d3 100644 --- a/hw/rtl/fp_cores/altera/acl_ftou.sv +++ b/hw/rtl/fp_cores/altera/arria10/acl_ftou.sv @@ -16,7 +16,7 @@ // --------------------------------------------------------------------------- // SystemVerilog created from acl_ftou -// SystemVerilog created on Wed Dec 9 01:17:51 2020 +// SystemVerilog created on Sun Dec 27 09:47:21 2020 (* altera_attribute = "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410; -name MESSAGE_DISABLE 113007; -name MESSAGE_DISABLE 10958" *) diff --git a/hw/rtl/fp_cores/altera/arria10/acl_gen.log b/hw/rtl/fp_cores/altera/arria10/acl_gen.log new file mode 100644 index 00000000..ce8c8447 --- /dev/null +++ b/hw/rtl/fp_cores/altera/arria10/acl_gen.log @@ -0,0 +1,296 @@ +starting execution ... +build model options ... +argc=22 +Generation context: + Will not generate valid and channel signals + HardFP is enabled enabling set to true + Correct rounding constraint detected + Will not generate valid and channel signals + The new component name is acl_fadd + Frequency 250MHz + Deployment FPGA Arria10 +Estimated resources LUTs 0, DSPs 2, RAMBits 0, RAMBlocks 0 +The pipeline depth of the block is 3 cycle(s) +@@start +@name FPAdd@ +@latency 3@ +@LUT 0@ +@DSP 2@ +@RAMBits 0@ +@RAMBlockUsage 0@ +@enable 1@ +@subnormals 0@ +@error 0.50@ +@rounding RNE@ +@method single path@ +@inPort 0 fpieee 8 23@ +@inPort 1 fpieee 8 23@ +@outPort 0 fpieee 8 23@ +@nochanvalid 1@ +@@end +starting execution ... +build model options ... +argc=22 +Generation context: + Will not generate valid and channel signals + HardFP is enabled enabling set to true + Correct rounding constraint detected + Will not generate valid and channel signals + The new component name is acl_fsub + Frequency 250MHz + Deployment FPGA Arria10 +Estimated resources LUTs 0, DSPs 2, RAMBits 0, RAMBlocks 0 +The pipeline depth of the block is 3 cycle(s) +@@start +@name FPSub@ +@latency 3@ +@LUT 0@ +@DSP 2@ +@RAMBits 0@ +@RAMBlockUsage 0@ +@enable 1@ +@subnormals 0@ +@error 0.50@ +@rounding RNE@ +@method single path@ +@inPort 0 fpieee 8 23@ +@inPort 1 fpieee 8 23@ +@outPort 0 fpieee 8 23@ +@nochanvalid 1@ +@@end +starting execution ... +build model options ... +argc=22 +Generation context: + Will not generate valid and channel signals + HardFP is enabled enabling set to true + Correct rounding constraint detected + Will not generate valid and channel signals + The new component name is acl_fmul + Frequency 250MHz + Deployment FPGA Arria10 +Estimated resources LUTs 0, DSPs 2, RAMBits 0, RAMBlocks 0 +The pipeline depth of the block is 3 cycle(s) +@@start +@name FPMul@ +@latency 3@ +@LUT 0@ +@DSP 2@ +@RAMBits 0@ +@RAMBlockUsage 0@ +@enable 1@ +@subnormals 0@ +@error 0.50@ +@rounding RNE@ +@method default@ +@inPort 0 fpieee 8 23@ +@inPort 1 fpieee 8 23@ +@outPort 0 fpieee 8 23@ +@nochanvalid 1@ +@@end +starting execution ... +build model options ... +argc=22 +Generation context: + Will not generate valid and channel signals + HardFP is enabled enabling set to true + Correct rounding constraint detected + Will not generate valid and channel signals + The new component name is acl_fmadd + Frequency 250MHz + Deployment FPGA Arria10 +Estimated resources LUTs 0, DSPs 2, RAMBits 0, RAMBlocks 0 +The pipeline depth of the block is 4 cycle(s) +@@start +@name FPMultAdd@ +@latency 4@ +@LUT 0@ +@DSP 2@ +@RAMBits 0@ +@RAMBlockUsage 0@ +@enable 1@ +@subnormals 0@ +@error 0.50@ +@rounding RNE@ +@method multadd@ +@inPort 0 fpieee 8 23@ +@inPort 1 fpieee 8 23@ +@inPort 2 fpieee 8 23@ +@outPort 0 fpieee 8 23@ +@nochanvalid 1@ +@@end +starting execution ... +build model options ... +argc=23 +Generation context: + Will not generate valid and channel signals + HardFP is enabled enabling set to true + Correct rounding constraint detected + Will not generate valid and channel signals + The new component name is acl_fdiv + Frequency 250MHz + Deployment FPGA Arria10 +Estimated resources LUTs 1067, DSPs 7, RAMBits 34304, RAMBlocks 3 +The pipeline depth of the block is 20 cycle(s) +@@start +@name FPDiv@ +@latency 20@ +@LUT 1067@ +@DSP 7@ +@RAMBits 34304@ +@RAMBlockUsage 3@ +@enable 1@ +@subnormals 0@ +@error 0.50@ +@rounding RNE@ +@method polynomial approximation@ +@inPort 0 fpieee 8 23@ +@inPort 1 fpieee 8 23@ +@outPort 0 fpieee 8 23@ +@nochanvalid 1@ +@@end +starting execution ... +build model options ... +argc=22 +Generation context: + Will not generate valid and channel signals + HardFP is enabled enabling set to true + Correct rounding constraint detected + Will not generate valid and channel signals + The new component name is acl_fsqrt + Frequency 250MHz + Deployment FPGA Arria10 +Estimated resources LUTs 518, DSPs 5, RAMBits 15872, RAMBlocks 3 +The pipeline depth of the block is 15 cycle(s) +@@start +@name FPSqrt@ +@latency 15@ +@LUT 518@ +@DSP 5@ +@RAMBits 15872@ +@RAMBlockUsage 3@ +@enable 1@ +@subnormals 0@ +@error 0.50@ +@rounding RNE@ +@method polynomial approximation@ +@inPort 0 fpieee 8 23@ +@outPort 0 fpieee 8 23@ +@nochanvalid 1@ +@@end +starting execution ... +build model options ... +argc=25 +Generation context: + Will not generate valid and channel signals + HardFP is enabled enabling set to true + Correct rounding constraint detected + Will not generate valid and channel signals + The new component name is acl_ftoi + Frequency 250MHz + Deployment FPGA Arria10 +Estimated resources LUTs 327, DSPs 0, RAMBits 0, RAMBlocks 0 +The pipeline depth of the block is 3 cycle(s) +@@start +@name FPToFXP@ +@latency 3@ +@LUT 327@ +@DSP 0@ +@RAMBits 0@ +@RAMBlockUsage 0@ +@enable 1@ +@subnormals 0@ +@error 0.50@ +@rounding RNE@ +@method default@ +@inPort 0 fpieee 8 23@ +@outPort 0 fxp 32 0 1@ +@nochanvalid 1@ +@@end +starting execution ... +build model options ... +argc=25 +Generation context: + Will not generate valid and channel signals + HardFP is enabled enabling set to true + Correct rounding constraint detected + Will not generate valid and channel signals + The new component name is acl_ftou + Frequency 250MHz + Deployment FPGA Arria10 +Estimated resources LUTs 287, DSPs 0, RAMBits 0, RAMBlocks 0 +The pipeline depth of the block is 3 cycle(s) +@@start +@name FPToFXP@ +@latency 3@ +@LUT 287@ +@DSP 0@ +@RAMBits 0@ +@RAMBlockUsage 0@ +@enable 1@ +@subnormals 0@ +@error 0.50@ +@rounding RNE@ +@method default@ +@inPort 0 fpieee 8 23@ +@outPort 0 fxp 32 0 0@ +@nochanvalid 1@ +@@end +starting execution ... +build model options ... +argc=25 +Generation context: + Will not generate valid and channel signals + HardFP is enabled enabling set to true + Correct rounding constraint detected + Will not generate valid and channel signals + The new component name is acl_itof + Frequency 250MHz + Deployment FPGA Arria10 +Estimated resources LUTs 397, DSPs 0, RAMBits 0, RAMBlocks 0 +The pipeline depth of the block is 7 cycle(s) +@@start +@name FXPToFP@ +@latency 7@ +@LUT 397@ +@DSP 0@ +@RAMBits 0@ +@RAMBlockUsage 0@ +@enable 1@ +@subnormals 0@ +@error 0.50@ +@rounding RNE@ +@method default@ +@inPort 0 fxp 32 0 1@ +@outPort 0 fpieee 8 23@ +@nochanvalid 1@ +@@end +starting execution ... +build model options ... +argc=25 +Generation context: + Will not generate valid and channel signals + HardFP is enabled enabling set to true + Correct rounding constraint detected + Will not generate valid and channel signals + The new component name is acl_utof + Frequency 300MHz + Deployment FPGA Arria10 +Estimated resources LUTs 363, DSPs 0, RAMBits 0, RAMBlocks 0 +The pipeline depth of the block is 7 cycle(s) +@@start +@name FXPToFP@ +@latency 7@ +@LUT 363@ +@DSP 0@ +@RAMBits 0@ +@RAMBlockUsage 0@ +@enable 1@ +@subnormals 0@ +@error 0.50@ +@rounding RNE@ +@method default@ +@inPort 0 fxp 32 0 0@ +@outPort 0 fpieee 8 23@ +@nochanvalid 1@ +@@end diff --git a/hw/rtl/fp_cores/altera/arria10/acl_gen.sh b/hw/rtl/fp_cores/altera/arria10/acl_gen.sh new file mode 100755 index 00000000..4aaa2ae3 --- /dev/null +++ b/hw/rtl/fp_cores/altera/arria10/acl_gen.sh @@ -0,0 +1,33 @@ +#!/bin/bash + +FAMILY=Arria10 +PREFIX=acl + +CMD_POLY_EVAL_PATH=$QUARTUS_HOME/dspba/backend/linux64 + +OPTIONS="-target $FAMILY -noChanValid -enable -enableHardFP 1 -printMachineReadable -lang verilog -correctRounding -noChanValid -enable -speedgrade 2" + +export LD_LIBRARY_PATH=$CMD_POLY_EVAL_PATH:$LD_LIBRARY_PATH + +CMD="$CMD_POLY_EVAL_PATH/cmdPolyEval $OPTIONS" + +EXP_BITS=8 +MAN_BITS=23 + +FBITS="f$(($EXP_BITS + $MAN_BITS + 1))" + +echo Generating IP cores for $FBITS +{ + $CMD -name "$PREFIX"_fadd -frequency 250 FPAdd $EXP_BITS $MAN_BITS + $CMD -name "$PREFIX"_fsub -frequency 250 FPSub $EXP_BITS $MAN_BITS + $CMD -name "$PREFIX"_fmul -frequency 250 FPMul $EXP_BITS $MAN_BITS + $CMD -name "$PREFIX"_fmadd -frequency 250 FPMultAdd $EXP_BITS $MAN_BITS + $CMD -name "$PREFIX"_fdiv -frequency 250 FPDiv $EXP_BITS $MAN_BITS 0 + $CMD -name "$PREFIX"_fsqrt -frequency 250 FPSqrt $EXP_BITS $MAN_BITS + $CMD -name "$PREFIX"_ftoi -frequency 250 FPToFXP $EXP_BITS $MAN_BITS 32 0 1 + $CMD -name "$PREFIX"_ftou -frequency 250 FPToFXP $EXP_BITS $MAN_BITS 32 0 0 + $CMD -name "$PREFIX"_itof -frequency 250 FXPToFP 32 0 1 $EXP_BITS $MAN_BITS + $CMD -name "$PREFIX"_utof -frequency 300 FXPToFP 32 0 0 $EXP_BITS $MAN_BITS +} > acl_gen.log 2>&1 + +#cp $QUARTUS_HOME/dspba/backend/Libraries/sv/base/dspba_library_ver.sv . \ No newline at end of file diff --git a/hw/rtl/fp_cores/altera/acl_itof.sv b/hw/rtl/fp_cores/altera/arria10/acl_itof.sv similarity index 99% rename from hw/rtl/fp_cores/altera/acl_itof.sv rename to hw/rtl/fp_cores/altera/arria10/acl_itof.sv index 2982444d..78316263 100644 --- a/hw/rtl/fp_cores/altera/acl_itof.sv +++ b/hw/rtl/fp_cores/altera/arria10/acl_itof.sv @@ -16,7 +16,7 @@ // --------------------------------------------------------------------------- // SystemVerilog created from acl_itof -// SystemVerilog created on Wed Dec 9 01:17:51 2020 +// SystemVerilog created on Sun Dec 27 09:47:21 2020 (* altera_attribute = "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410; -name MESSAGE_DISABLE 113007; -name MESSAGE_DISABLE 10958" *) diff --git a/hw/rtl/fp_cores/altera/acl_utof.sv b/hw/rtl/fp_cores/altera/arria10/acl_utof.sv similarity index 99% rename from hw/rtl/fp_cores/altera/acl_utof.sv rename to hw/rtl/fp_cores/altera/arria10/acl_utof.sv index 21812e1f..086bab11 100644 --- a/hw/rtl/fp_cores/altera/acl_utof.sv +++ b/hw/rtl/fp_cores/altera/arria10/acl_utof.sv @@ -16,7 +16,7 @@ // --------------------------------------------------------------------------- // SystemVerilog created from acl_utof -// SystemVerilog created on Wed Dec 9 01:17:51 2020 +// SystemVerilog created on Sun Dec 27 09:47:21 2020 (* altera_attribute = "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410; -name MESSAGE_DISABLE 113007; -name MESSAGE_DISABLE 10958" *) diff --git a/hw/rtl/fp_cores/altera/dspba_delay_ver.sv b/hw/rtl/fp_cores/altera/arria10/dspba_delay_ver.sv similarity index 100% rename from hw/rtl/fp_cores/altera/dspba_delay_ver.sv rename to hw/rtl/fp_cores/altera/arria10/dspba_delay_ver.sv diff --git a/hw/rtl/fp_cores/altera/stratix10/acl_fadd.sv b/hw/rtl/fp_cores/altera/stratix10/acl_fadd.sv new file mode 100644 index 00000000..2eeb9c7c --- /dev/null +++ b/hw/rtl/fp_cores/altera/stratix10/acl_fadd.sv @@ -0,0 +1,68 @@ +// ------------------------------------------------------------------------- +// High Level Design Compiler for Intel(R) FPGAs Version 18.1 (Release Build #277) +// Quartus Prime development tool and MATLAB/Simulink Interface +// +// Legal Notice: Copyright 2019 Intel Corporation. All rights reserved. +// Your use of Intel Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly +// subject to the terms and conditions of the Intel FPGA Software License +// Agreement, Intel MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for +// the sole purpose of programming logic devices manufactured by Intel +// and sold by Intel or its authorized distributors. Please refer to the +// applicable agreement for further details. +// --------------------------------------------------------------------------- + +// SystemVerilog created from acl_fadd +// SystemVerilog created on Sun Dec 27 09:48:57 2020 + + +(* altera_attribute = "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410; -name MESSAGE_DISABLE 113007; -name MESSAGE_DISABLE 10958" *) +module acl_fadd ( + input wire [31:0] a, + input wire [31:0] b, + input wire [0:0] en, + output wire [31:0] q, + input wire clk, + input wire areset + ); + + wire fpAddTest_impl_reset0; + wire fpAddTest_impl_ena0; + wire [31:0] fpAddTest_impl_ax0; + wire [31:0] fpAddTest_impl_ay0; + wire [31:0] fpAddTest_impl_q0; + + + // fpAddTest_impl(FPCOLUMN,5)@0 + // out q0@3 + assign fpAddTest_impl_ax0 = b; + assign fpAddTest_impl_ay0 = a; + assign fpAddTest_impl_reset0 = areset; + assign fpAddTest_impl_ena0 = en[0] | fpAddTest_impl_reset0; + fourteennm_fp_mac #( + .operation_mode("sp_add"), + .ax_clock("0"), + .ay_clock("0"), + .adder_input_clock("0"), + .output_clock("0"), + .clear_type("sclr") + ) fpAddTest_impl_DSP0 ( + .clk({1'b0,1'b0,clk}), + .ena({ 1'b0, 1'b0, fpAddTest_impl_ena0 }), + .clr({ fpAddTest_impl_reset0, fpAddTest_impl_reset0 }), + .ax(fpAddTest_impl_ax0), + .ay(fpAddTest_impl_ay0), + .resulta(fpAddTest_impl_q0), + .accumulate(), + .az(), + .chainin(), + .chainout() + ); + + // xOut(GPOUT,4)@3 + assign q = fpAddTest_impl_q0; + +endmodule diff --git a/hw/rtl/fp_cores/altera/stratix10/acl_fdiv.sv b/hw/rtl/fp_cores/altera/stratix10/acl_fdiv.sv new file mode 100644 index 00000000..8ec0f90c --- /dev/null +++ b/hw/rtl/fp_cores/altera/stratix10/acl_fdiv.sv @@ -0,0 +1,4167 @@ +// ------------------------------------------------------------------------- +// High Level Design Compiler for Intel(R) FPGAs Version 18.1 (Release Build #277) +// Quartus Prime development tool and MATLAB/Simulink Interface +// +// Legal Notice: Copyright 2019 Intel Corporation. All rights reserved. +// Your use of Intel Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly +// subject to the terms and conditions of the Intel FPGA Software License +// Agreement, Intel MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for +// the sole purpose of programming logic devices manufactured by Intel +// and sold by Intel or its authorized distributors. Please refer to the +// applicable agreement for further details. +// --------------------------------------------------------------------------- + +// SystemVerilog created from acl_fdiv +// SystemVerilog created on Sun Dec 27 09:48:58 2020 + + +(* altera_attribute = "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410; -name MESSAGE_DISABLE 113007; -name MESSAGE_DISABLE 10958" *) +module acl_fdiv ( + input wire [31:0] a, + input wire [31:0] b, + input wire [0:0] en, + output wire [31:0] q, + input wire clk, + input wire areset + ); + + wire [0:0] GND_q; + wire [0:0] VCC_q; + wire [7:0] cstBiasM1_uid6_fpDivTest_q; + wire [7:0] cstBias_uid7_fpDivTest_q; + wire [7:0] expX_uid9_fpDivTest_b; + wire [22:0] fracX_uid10_fpDivTest_b; + wire [0:0] signX_uid11_fpDivTest_b; + wire [7:0] expY_uid12_fpDivTest_b; + wire [22:0] fracY_uid13_fpDivTest_b; + wire [0:0] signY_uid14_fpDivTest_b; + wire [22:0] paddingY_uid15_fpDivTest_q; + wire [23:0] updatedY_uid16_fpDivTest_q; + wire [23:0] fracYZero_uid15_fpDivTest_a; + wire [0:0] fracYZero_uid15_fpDivTest_qi; + reg [0:0] fracYZero_uid15_fpDivTest_q; + wire [7:0] cstAllOWE_uid18_fpDivTest_q; + wire [7:0] cstAllZWE_uid20_fpDivTest_q; + wire [0:0] excZ_x_uid23_fpDivTest_q; + wire [0:0] expXIsMax_uid24_fpDivTest_q; + wire [0:0] fracXIsZero_uid25_fpDivTest_qi; + reg [0:0] fracXIsZero_uid25_fpDivTest_q; + wire [0:0] fracXIsNotZero_uid26_fpDivTest_q; + wire [0:0] excI_x_uid27_fpDivTest_q; + wire [0:0] excN_x_uid28_fpDivTest_q; + wire [0:0] invExpXIsMax_uid29_fpDivTest_q; + wire [0:0] InvExpXIsZero_uid30_fpDivTest_q; + wire [0:0] excR_x_uid31_fpDivTest_qi; + reg [0:0] excR_x_uid31_fpDivTest_q; + wire [0:0] excZ_y_uid37_fpDivTest_qi; + reg [0:0] excZ_y_uid37_fpDivTest_q; + wire [0:0] expXIsMax_uid38_fpDivTest_qi; + reg [0:0] expXIsMax_uid38_fpDivTest_q; + wire [0:0] fracXIsZero_uid39_fpDivTest_qi; + reg [0:0] fracXIsZero_uid39_fpDivTest_q; + wire [0:0] fracXIsNotZero_uid40_fpDivTest_q; + wire [0:0] excI_y_uid41_fpDivTest_q; + wire [0:0] excN_y_uid42_fpDivTest_q; + wire [0:0] invExpXIsMax_uid43_fpDivTest_q; + wire [0:0] InvExpXIsZero_uid44_fpDivTest_q; + wire [0:0] excR_y_uid45_fpDivTest_q; + wire [0:0] signR_uid46_fpDivTest_qi; + reg [0:0] signR_uid46_fpDivTest_q; + wire [8:0] expXmY_uid47_fpDivTest_a; + wire [8:0] expXmY_uid47_fpDivTest_b; + logic [8:0] expXmY_uid47_fpDivTest_o; + wire [8:0] expXmY_uid47_fpDivTest_q; + wire [10:0] expR_uid48_fpDivTest_a; + wire [10:0] expR_uid48_fpDivTest_b; + logic [10:0] expR_uid48_fpDivTest_o; + wire [9:0] expR_uid48_fpDivTest_q; + wire [8:0] yAddr_uid51_fpDivTest_b; + wire [13:0] yPE_uid52_fpDivTest_b; + wire [31:0] invY_uid54_fpDivTest_in; + wire [26:0] invY_uid54_fpDivTest_b; + wire [32:0] invYO_uid55_fpDivTest_in; + wire [0:0] invYO_uid55_fpDivTest_b; + wire [23:0] lOAdded_uid57_fpDivTest_q; + wire [3:0] z4_uid60_fpDivTest_q; + wire [27:0] oFracXZ4_uid61_fpDivTest_q; + wire [0:0] divValPreNormYPow2Exc_uid63_fpDivTest_s; + reg [27:0] divValPreNormYPow2Exc_uid63_fpDivTest_q; + wire [0:0] norm_uid64_fpDivTest_b; + wire [26:0] divValPreNormHigh_uid65_fpDivTest_in; + wire [24:0] divValPreNormHigh_uid65_fpDivTest_b; + wire [25:0] divValPreNormLow_uid66_fpDivTest_in; + wire [24:0] divValPreNormLow_uid66_fpDivTest_b; + wire [0:0] normFracRnd_uid67_fpDivTest_s; + reg [24:0] normFracRnd_uid67_fpDivTest_q; + wire [34:0] expFracRnd_uid68_fpDivTest_q; + wire [23:0] zeroPaddingInAddition_uid74_fpDivTest_q; + wire [25:0] expFracPostRnd_uid75_fpDivTest_q; + wire [36:0] expFracPostRnd_uid76_fpDivTest_a; + wire [36:0] expFracPostRnd_uid76_fpDivTest_b; + logic [36:0] expFracPostRnd_uid76_fpDivTest_o; + wire [35:0] expFracPostRnd_uid76_fpDivTest_q; + wire [23:0] fracXExt_uid77_fpDivTest_q; + wire [24:0] fracPostRndF_uid79_fpDivTest_in; + wire [23:0] fracPostRndF_uid79_fpDivTest_b; + wire [0:0] fracPostRndF_uid80_fpDivTest_s; + reg [23:0] fracPostRndF_uid80_fpDivTest_q; + wire [32:0] expPostRndFR_uid81_fpDivTest_in; + wire [7:0] expPostRndFR_uid81_fpDivTest_b; + wire [0:0] expPostRndF_uid82_fpDivTest_s; + reg [7:0] expPostRndF_uid82_fpDivTest_q; + wire [24:0] lOAdded_uid84_fpDivTest_q; + wire [23:0] lOAdded_uid87_fpDivTest_q; + wire [0:0] qDivProdNorm_uid90_fpDivTest_b; + wire [47:0] qDivProdFracHigh_uid91_fpDivTest_in; + wire [23:0] qDivProdFracHigh_uid91_fpDivTest_b; + wire [46:0] qDivProdFracLow_uid92_fpDivTest_in; + wire [23:0] qDivProdFracLow_uid92_fpDivTest_b; + wire [0:0] qDivProdFrac_uid93_fpDivTest_s; + reg [23:0] qDivProdFrac_uid93_fpDivTest_q; + wire [8:0] qDivProdExp_opA_uid94_fpDivTest_a; + wire [8:0] qDivProdExp_opA_uid94_fpDivTest_b; + logic [8:0] qDivProdExp_opA_uid94_fpDivTest_o; + wire [8:0] qDivProdExp_opA_uid94_fpDivTest_q; + wire [8:0] qDivProdExp_opBs_uid95_fpDivTest_a; + wire [8:0] qDivProdExp_opBs_uid95_fpDivTest_b; + logic [8:0] qDivProdExp_opBs_uid95_fpDivTest_o; + wire [8:0] qDivProdExp_opBs_uid95_fpDivTest_q; + wire [11:0] qDivProdExp_uid96_fpDivTest_a; + wire [11:0] qDivProdExp_uid96_fpDivTest_b; + logic [11:0] qDivProdExp_uid96_fpDivTest_o; + wire [10:0] qDivProdExp_uid96_fpDivTest_q; + wire [22:0] qDivProdFracWF_uid97_fpDivTest_b; + wire [7:0] qDivProdLTX_opA_uid98_fpDivTest_in; + wire [7:0] qDivProdLTX_opA_uid98_fpDivTest_b; + wire [30:0] qDivProdLTX_opA_uid99_fpDivTest_q; + wire [30:0] qDivProdLTX_opB_uid100_fpDivTest_q; + wire [32:0] qDividerProdLTX_uid101_fpDivTest_a; + wire [32:0] qDividerProdLTX_uid101_fpDivTest_b; + logic [32:0] qDividerProdLTX_uid101_fpDivTest_o; + wire [0:0] qDividerProdLTX_uid101_fpDivTest_c; + wire [0:0] betweenFPwF_uid102_fpDivTest_in; + wire [0:0] betweenFPwF_uid102_fpDivTest_b; + wire [0:0] extraUlp_uid103_fpDivTest_qi; + reg [0:0] extraUlp_uid103_fpDivTest_q; + wire [22:0] fracPostRndFT_uid104_fpDivTest_b; + wire [23:0] fracRPreExcExt_uid105_fpDivTest_a; + wire [23:0] fracRPreExcExt_uid105_fpDivTest_b; + logic [23:0] fracRPreExcExt_uid105_fpDivTest_o; + wire [23:0] fracRPreExcExt_uid105_fpDivTest_q; + wire [22:0] fracPostRndFPostUlp_uid106_fpDivTest_in; + wire [22:0] fracPostRndFPostUlp_uid106_fpDivTest_b; + wire [0:0] fracRPreExc_uid107_fpDivTest_s; + reg [22:0] fracRPreExc_uid107_fpDivTest_q; + wire [0:0] ovfIncRnd_uid109_fpDivTest_b; + wire [8:0] expFracPostRndInc_uid110_fpDivTest_a; + wire [8:0] expFracPostRndInc_uid110_fpDivTest_b; + logic [8:0] expFracPostRndInc_uid110_fpDivTest_o; + wire [8:0] expFracPostRndInc_uid110_fpDivTest_q; + wire [7:0] expFracPostRndR_uid111_fpDivTest_in; + wire [7:0] expFracPostRndR_uid111_fpDivTest_b; + wire [0:0] expRPreExc_uid112_fpDivTest_s; + reg [7:0] expRPreExc_uid112_fpDivTest_q; + wire [10:0] expRExt_uid114_fpDivTest_b; + wire [12:0] expUdf_uid115_fpDivTest_a; + wire [12:0] expUdf_uid115_fpDivTest_b; + logic [12:0] expUdf_uid115_fpDivTest_o; + wire [0:0] expUdf_uid115_fpDivTest_n; + wire [12:0] expOvf_uid118_fpDivTest_a; + wire [12:0] expOvf_uid118_fpDivTest_b; + logic [12:0] expOvf_uid118_fpDivTest_o; + wire [0:0] expOvf_uid118_fpDivTest_n; + wire [0:0] zeroOverReg_uid119_fpDivTest_q; + wire [0:0] regOverRegWithUf_uid120_fpDivTest_q; + wire [0:0] xRegOrZero_uid121_fpDivTest_q; + wire [0:0] regOrZeroOverInf_uid122_fpDivTest_q; + wire [0:0] excRZero_uid123_fpDivTest_q; + wire [0:0] excXRYZ_uid124_fpDivTest_q; + wire [0:0] excXRYROvf_uid125_fpDivTest_q; + wire [0:0] excXIYZ_uid126_fpDivTest_q; + wire [0:0] excXIYR_uid127_fpDivTest_q; + wire [0:0] excRInf_uid128_fpDivTest_q; + wire [0:0] excXZYZ_uid129_fpDivTest_q; + wire [0:0] excXIYI_uid130_fpDivTest_q; + wire [0:0] excRNaN_uid131_fpDivTest_q; + wire [2:0] concExc_uid132_fpDivTest_q; + reg [1:0] excREnc_uid133_fpDivTest_q; + wire [22:0] oneFracRPostExc2_uid134_fpDivTest_q; + wire [1:0] fracRPostExc_uid137_fpDivTest_s; + reg [22:0] fracRPostExc_uid137_fpDivTest_q; + wire [1:0] expRPostExc_uid141_fpDivTest_s; + reg [7:0] expRPostExc_uid141_fpDivTest_q; + wire [0:0] invExcRNaN_uid142_fpDivTest_q; + wire [0:0] sRPostExc_uid143_fpDivTest_qi; + reg [0:0] sRPostExc_uid143_fpDivTest_q; + wire [31:0] divR_uid144_fpDivTest_q; + wire [12:0] yT1_uid158_invPolyEval_b; + wire [0:0] lowRangeB_uid160_invPolyEval_in; + wire [0:0] lowRangeB_uid160_invPolyEval_b; + wire [12:0] highBBits_uid161_invPolyEval_b; + wire [22:0] s1sumAHighB_uid162_invPolyEval_a; + wire [22:0] s1sumAHighB_uid162_invPolyEval_b; + logic [22:0] s1sumAHighB_uid162_invPolyEval_o; + wire [22:0] s1sumAHighB_uid162_invPolyEval_q; + wire [23:0] s1_uid163_invPolyEval_q; + wire [1:0] lowRangeB_uid166_invPolyEval_in; + wire [1:0] lowRangeB_uid166_invPolyEval_b; + wire [22:0] highBBits_uid167_invPolyEval_b; + wire [32:0] s2sumAHighB_uid168_invPolyEval_a; + wire [32:0] s2sumAHighB_uid168_invPolyEval_b; + logic [32:0] s2sumAHighB_uid168_invPolyEval_o; + wire [32:0] s2sumAHighB_uid168_invPolyEval_q; + wire [34:0] s2_uid169_invPolyEval_q; + wire [27:0] osig_uid172_divValPreNorm_uid59_fpDivTest_b; + wire [13:0] osig_uid175_pT1_uid159_invPolyEval_b; + wire [24:0] osig_uid178_pT2_uid165_invPolyEval_b; + wire memoryC0_uid146_invTables_lutmem_reset0; + wire [31:0] memoryC0_uid146_invTables_lutmem_ia; + wire [8:0] memoryC0_uid146_invTables_lutmem_aa; + wire [8:0] memoryC0_uid146_invTables_lutmem_ab; + wire [31:0] memoryC0_uid146_invTables_lutmem_ir; + wire [31:0] memoryC0_uid146_invTables_lutmem_r; + wire memoryC0_uid146_invTables_lutmem_enaOr_rst; + wire memoryC1_uid149_invTables_lutmem_reset0; + wire [21:0] memoryC1_uid149_invTables_lutmem_ia; + wire [8:0] memoryC1_uid149_invTables_lutmem_aa; + wire [8:0] memoryC1_uid149_invTables_lutmem_ab; + wire [21:0] memoryC1_uid149_invTables_lutmem_ir; + wire [21:0] memoryC1_uid149_invTables_lutmem_r; + wire memoryC1_uid149_invTables_lutmem_enaOr_rst; + wire memoryC2_uid152_invTables_lutmem_reset0; + wire [12:0] memoryC2_uid152_invTables_lutmem_ia; + wire [8:0] memoryC2_uid152_invTables_lutmem_aa; + wire [8:0] memoryC2_uid152_invTables_lutmem_ab; + wire [12:0] memoryC2_uid152_invTables_lutmem_ir; + wire [12:0] memoryC2_uid152_invTables_lutmem_r; + wire memoryC2_uid152_invTables_lutmem_enaOr_rst; + wire qDivProd_uid89_fpDivTest_cma_reset; + (* preserve_syn_only *) reg [24:0] qDivProd_uid89_fpDivTest_cma_ah [0:0]; + (* preserve_syn_only *) reg [23:0] qDivProd_uid89_fpDivTest_cma_ch [0:0]; + wire [24:0] qDivProd_uid89_fpDivTest_cma_a0; + wire [23:0] qDivProd_uid89_fpDivTest_cma_c0; + wire [48:0] qDivProd_uid89_fpDivTest_cma_s0; + wire [48:0] qDivProd_uid89_fpDivTest_cma_qq; + reg [48:0] qDivProd_uid89_fpDivTest_cma_q; + wire qDivProd_uid89_fpDivTest_cma_ena0; + wire qDivProd_uid89_fpDivTest_cma_ena1; + wire qDivProd_uid89_fpDivTest_cma_ena2; + wire prodXY_uid171_divValPreNorm_uid59_fpDivTest_cma_reset; + (* preserve_syn_only *) reg [26:0] prodXY_uid171_divValPreNorm_uid59_fpDivTest_cma_ah [0:0]; + (* preserve_syn_only *) reg [23:0] prodXY_uid171_divValPreNorm_uid59_fpDivTest_cma_ch [0:0]; + wire [26:0] prodXY_uid171_divValPreNorm_uid59_fpDivTest_cma_a0; + wire [23:0] prodXY_uid171_divValPreNorm_uid59_fpDivTest_cma_c0; + wire [50:0] prodXY_uid171_divValPreNorm_uid59_fpDivTest_cma_s0; + wire [50:0] prodXY_uid171_divValPreNorm_uid59_fpDivTest_cma_qq; + reg [50:0] prodXY_uid171_divValPreNorm_uid59_fpDivTest_cma_q; + wire prodXY_uid171_divValPreNorm_uid59_fpDivTest_cma_ena0; + wire prodXY_uid171_divValPreNorm_uid59_fpDivTest_cma_ena1; + wire prodXY_uid171_divValPreNorm_uid59_fpDivTest_cma_ena2; + wire prodXY_uid174_pT1_uid159_invPolyEval_cma_reset; + (* preserve_syn_only *) reg [12:0] prodXY_uid174_pT1_uid159_invPolyEval_cma_ah [0:0]; + (* preserve_syn_only *) reg signed [12:0] prodXY_uid174_pT1_uid159_invPolyEval_cma_ch [0:0]; + wire [12:0] prodXY_uid174_pT1_uid159_invPolyEval_cma_a0; + wire [12:0] prodXY_uid174_pT1_uid159_invPolyEval_cma_c0; + wire [25:0] prodXY_uid174_pT1_uid159_invPolyEval_cma_s0; + wire [25:0] prodXY_uid174_pT1_uid159_invPolyEval_cma_qq; + reg [25:0] prodXY_uid174_pT1_uid159_invPolyEval_cma_q; + wire prodXY_uid174_pT1_uid159_invPolyEval_cma_ena0; + wire prodXY_uid174_pT1_uid159_invPolyEval_cma_ena1; + wire prodXY_uid174_pT1_uid159_invPolyEval_cma_ena2; + wire prodXY_uid177_pT2_uid165_invPolyEval_cma_reset; + (* preserve_syn_only *) reg [13:0] prodXY_uid177_pT2_uid165_invPolyEval_cma_ah [0:0]; + (* preserve_syn_only *) reg signed [23:0] prodXY_uid177_pT2_uid165_invPolyEval_cma_ch [0:0]; + wire [13:0] prodXY_uid177_pT2_uid165_invPolyEval_cma_a0; + wire [23:0] prodXY_uid177_pT2_uid165_invPolyEval_cma_c0; + wire [37:0] prodXY_uid177_pT2_uid165_invPolyEval_cma_s0; + wire [37:0] prodXY_uid177_pT2_uid165_invPolyEval_cma_qq; + reg [37:0] prodXY_uid177_pT2_uid165_invPolyEval_cma_q; + wire prodXY_uid177_pT2_uid165_invPolyEval_cma_ena0; + wire prodXY_uid177_pT2_uid165_invPolyEval_cma_ena1; + wire prodXY_uid177_pT2_uid165_invPolyEval_cma_ena2; + reg [12:0] redist0_memoryC2_uid152_invTables_lutmem_r_1_q; + reg [0:0] redist1_lowRangeB_uid160_invPolyEval_b_1_q; + reg [0:0] redist2_sRPostExc_uid143_fpDivTest_q_9_q; + reg [1:0] redist3_excREnc_uid133_fpDivTest_q_9_q; + reg [0:0] redist5_betweenFPwF_uid102_fpDivTest_b_7_q; + reg [7:0] redist6_qDivProdLTX_opA_uid98_fpDivTest_b_1_q; + reg [22:0] redist7_qDivProdFracWF_uid97_fpDivTest_b_1_q; + reg [7:0] redist9_expPostRndFR_uid81_fpDivTest_b_9_q; + reg [7:0] redist9_expPostRndFR_uid81_fpDivTest_b_9_delay_0; + reg [23:0] redist10_fracPostRndF_uid79_fpDivTest_b_1_q; + reg [0:0] redist11_norm_uid64_fpDivTest_b_1_q; + reg [0:0] redist13_invYO_uid55_fpDivTest_b_9_q; + reg [0:0] redist14_invYO_uid55_fpDivTest_b_15_q; + reg [26:0] redist15_invY_uid54_fpDivTest_b_1_q; + reg [13:0] redist16_yPE_uid52_fpDivTest_b_3_q; + reg [13:0] redist16_yPE_uid52_fpDivTest_b_3_delay_0; + reg [13:0] redist16_yPE_uid52_fpDivTest_b_3_delay_1; + reg [0:0] redist20_signR_uid46_fpDivTest_q_25_q; + reg [0:0] redist21_expXIsMax_uid24_fpDivTest_q_1_q; + reg [0:0] redist22_excZ_x_uid23_fpDivTest_q_1_q; + reg [22:0] redist24_fracY_uid13_fpDivTest_b_24_q; + reg [22:0] redist24_fracY_uid13_fpDivTest_b_24_delay_0; + reg [22:0] redist25_fracY_uid13_fpDivTest_b_25_q; + reg [7:0] redist27_expY_uid12_fpDivTest_b_24_q; + reg [22:0] redist31_fracX_uid10_fpDivTest_b_25_q; + reg [7:0] redist34_expX_uid9_fpDivTest_b_24_q; + reg [7:0] redist36_expX_uid9_fpDivTest_b_32_q; + wire redist4_fracPostRndFT_uid104_fpDivTest_b_8_mem_reset0; + wire [22:0] redist4_fracPostRndFT_uid104_fpDivTest_b_8_mem_ia; + wire [2:0] redist4_fracPostRndFT_uid104_fpDivTest_b_8_mem_aa; + wire [2:0] redist4_fracPostRndFT_uid104_fpDivTest_b_8_mem_ab; + wire [22:0] redist4_fracPostRndFT_uid104_fpDivTest_b_8_mem_iq; + wire [22:0] redist4_fracPostRndFT_uid104_fpDivTest_b_8_mem_q; + wire redist4_fracPostRndFT_uid104_fpDivTest_b_8_mem_enaOr_rst; + wire [2:0] redist4_fracPostRndFT_uid104_fpDivTest_b_8_rdcnt_q; + (* preserve_syn_only *) reg [2:0] redist4_fracPostRndFT_uid104_fpDivTest_b_8_rdcnt_i; + (* preserve_syn_only *) reg redist4_fracPostRndFT_uid104_fpDivTest_b_8_rdcnt_eq; + wire [0:0] redist4_fracPostRndFT_uid104_fpDivTest_b_8_rdmux_s; + reg [2:0] redist4_fracPostRndFT_uid104_fpDivTest_b_8_rdmux_q; + reg [2:0] redist4_fracPostRndFT_uid104_fpDivTest_b_8_wraddr_q; + wire [3:0] redist4_fracPostRndFT_uid104_fpDivTest_b_8_mem_last_q; + wire [3:0] redist4_fracPostRndFT_uid104_fpDivTest_b_8_cmp_b; + wire [0:0] redist4_fracPostRndFT_uid104_fpDivTest_b_8_cmp_q; + reg [0:0] redist4_fracPostRndFT_uid104_fpDivTest_b_8_cmpReg_q; + wire [0:0] redist4_fracPostRndFT_uid104_fpDivTest_b_8_notEnable_q; + wire [0:0] redist4_fracPostRndFT_uid104_fpDivTest_b_8_nor_q; + (* preserve_syn_only *) reg [0:0] redist4_fracPostRndFT_uid104_fpDivTest_b_8_sticky_ena_q; + wire [0:0] redist4_fracPostRndFT_uid104_fpDivTest_b_8_enaAnd_q; + reg [7:0] redist8_expPostRndFR_uid81_fpDivTest_b_7_outputreg0_q; + wire redist8_expPostRndFR_uid81_fpDivTest_b_7_mem_reset0; + wire [7:0] redist8_expPostRndFR_uid81_fpDivTest_b_7_mem_ia; + wire [2:0] redist8_expPostRndFR_uid81_fpDivTest_b_7_mem_aa; + wire [2:0] redist8_expPostRndFR_uid81_fpDivTest_b_7_mem_ab; + wire [7:0] redist8_expPostRndFR_uid81_fpDivTest_b_7_mem_iq; + wire [7:0] redist8_expPostRndFR_uid81_fpDivTest_b_7_mem_q; + wire redist8_expPostRndFR_uid81_fpDivTest_b_7_mem_enaOr_rst; + wire [2:0] redist8_expPostRndFR_uid81_fpDivTest_b_7_rdcnt_q; + (* preserve_syn_only *) reg [2:0] redist8_expPostRndFR_uid81_fpDivTest_b_7_rdcnt_i; + (* preserve_syn_only *) reg redist8_expPostRndFR_uid81_fpDivTest_b_7_rdcnt_eq; + wire [0:0] redist8_expPostRndFR_uid81_fpDivTest_b_7_rdmux_s; + reg [2:0] redist8_expPostRndFR_uid81_fpDivTest_b_7_rdmux_q; + reg [2:0] redist8_expPostRndFR_uid81_fpDivTest_b_7_wraddr_q; + wire [2:0] redist8_expPostRndFR_uid81_fpDivTest_b_7_mem_last_q; + wire [0:0] redist8_expPostRndFR_uid81_fpDivTest_b_7_cmp_q; + reg [0:0] redist8_expPostRndFR_uid81_fpDivTest_b_7_cmpReg_q; + wire [0:0] redist8_expPostRndFR_uid81_fpDivTest_b_7_notEnable_q; + wire [0:0] redist8_expPostRndFR_uid81_fpDivTest_b_7_nor_q; + (* preserve_syn_only *) reg [0:0] redist8_expPostRndFR_uid81_fpDivTest_b_7_sticky_ena_q; + wire [0:0] redist8_expPostRndFR_uid81_fpDivTest_b_7_enaAnd_q; + wire redist12_lOAdded_uid57_fpDivTest_q_6_mem_reset0; + wire [23:0] redist12_lOAdded_uid57_fpDivTest_q_6_mem_ia; + wire [2:0] redist12_lOAdded_uid57_fpDivTest_q_6_mem_aa; + wire [2:0] redist12_lOAdded_uid57_fpDivTest_q_6_mem_ab; + wire [23:0] redist12_lOAdded_uid57_fpDivTest_q_6_mem_iq; + wire [23:0] redist12_lOAdded_uid57_fpDivTest_q_6_mem_q; + wire redist12_lOAdded_uid57_fpDivTest_q_6_mem_enaOr_rst; + wire [2:0] redist12_lOAdded_uid57_fpDivTest_q_6_rdcnt_q; + (* preserve_syn_only *) reg [2:0] redist12_lOAdded_uid57_fpDivTest_q_6_rdcnt_i; + (* preserve_syn_only *) reg redist12_lOAdded_uid57_fpDivTest_q_6_rdcnt_eq; + wire [0:0] redist12_lOAdded_uid57_fpDivTest_q_6_rdmux_s; + reg [2:0] redist12_lOAdded_uid57_fpDivTest_q_6_rdmux_q; + reg [2:0] redist12_lOAdded_uid57_fpDivTest_q_6_wraddr_q; + wire [2:0] redist12_lOAdded_uid57_fpDivTest_q_6_mem_last_q; + wire [0:0] redist12_lOAdded_uid57_fpDivTest_q_6_cmp_q; + reg [0:0] redist12_lOAdded_uid57_fpDivTest_q_6_cmpReg_q; + wire [0:0] redist12_lOAdded_uid57_fpDivTest_q_6_notEnable_q; + wire [0:0] redist12_lOAdded_uid57_fpDivTest_q_6_nor_q; + (* preserve_syn_only *) reg [0:0] redist12_lOAdded_uid57_fpDivTest_q_6_sticky_ena_q; + wire [0:0] redist12_lOAdded_uid57_fpDivTest_q_6_enaAnd_q; + reg [13:0] redist17_yPE_uid52_fpDivTest_b_10_outputreg0_q; + wire redist17_yPE_uid52_fpDivTest_b_10_mem_reset0; + wire [13:0] redist17_yPE_uid52_fpDivTest_b_10_mem_ia; + wire [2:0] redist17_yPE_uid52_fpDivTest_b_10_mem_aa; + wire [2:0] redist17_yPE_uid52_fpDivTest_b_10_mem_ab; + wire [13:0] redist17_yPE_uid52_fpDivTest_b_10_mem_iq; + wire [13:0] redist17_yPE_uid52_fpDivTest_b_10_mem_q; + wire redist17_yPE_uid52_fpDivTest_b_10_mem_enaOr_rst; + wire [2:0] redist17_yPE_uid52_fpDivTest_b_10_rdcnt_q; + (* preserve_syn_only *) reg [2:0] redist17_yPE_uid52_fpDivTest_b_10_rdcnt_i; + (* preserve_syn_only *) reg redist17_yPE_uid52_fpDivTest_b_10_rdcnt_eq; + wire [0:0] redist17_yPE_uid52_fpDivTest_b_10_rdmux_s; + reg [2:0] redist17_yPE_uid52_fpDivTest_b_10_rdmux_q; + reg [2:0] redist17_yPE_uid52_fpDivTest_b_10_wraddr_q; + wire [2:0] redist17_yPE_uid52_fpDivTest_b_10_mem_last_q; + wire [0:0] redist17_yPE_uid52_fpDivTest_b_10_cmp_q; + reg [0:0] redist17_yPE_uid52_fpDivTest_b_10_cmpReg_q; + wire [0:0] redist17_yPE_uid52_fpDivTest_b_10_notEnable_q; + wire [0:0] redist17_yPE_uid52_fpDivTest_b_10_nor_q; + (* preserve_syn_only *) reg [0:0] redist17_yPE_uid52_fpDivTest_b_10_sticky_ena_q; + wire [0:0] redist17_yPE_uid52_fpDivTest_b_10_enaAnd_q; + reg [8:0] redist18_yAddr_uid51_fpDivTest_b_7_outputreg0_q; + wire redist18_yAddr_uid51_fpDivTest_b_7_mem_reset0; + wire [8:0] redist18_yAddr_uid51_fpDivTest_b_7_mem_ia; + wire [2:0] redist18_yAddr_uid51_fpDivTest_b_7_mem_aa; + wire [2:0] redist18_yAddr_uid51_fpDivTest_b_7_mem_ab; + wire [8:0] redist18_yAddr_uid51_fpDivTest_b_7_mem_iq; + wire [8:0] redist18_yAddr_uid51_fpDivTest_b_7_mem_q; + wire redist18_yAddr_uid51_fpDivTest_b_7_mem_enaOr_rst; + wire [2:0] redist18_yAddr_uid51_fpDivTest_b_7_rdcnt_q; + (* preserve_syn_only *) reg [2:0] redist18_yAddr_uid51_fpDivTest_b_7_rdcnt_i; + (* preserve_syn_only *) reg redist18_yAddr_uid51_fpDivTest_b_7_rdcnt_eq; + wire [0:0] redist18_yAddr_uid51_fpDivTest_b_7_rdmux_s; + reg [2:0] redist18_yAddr_uid51_fpDivTest_b_7_rdmux_q; + reg [2:0] redist18_yAddr_uid51_fpDivTest_b_7_wraddr_q; + wire [2:0] redist18_yAddr_uid51_fpDivTest_b_7_mem_last_q; + wire [0:0] redist18_yAddr_uid51_fpDivTest_b_7_cmp_q; + reg [0:0] redist18_yAddr_uid51_fpDivTest_b_7_cmpReg_q; + wire [0:0] redist18_yAddr_uid51_fpDivTest_b_7_notEnable_q; + wire [0:0] redist18_yAddr_uid51_fpDivTest_b_7_nor_q; + (* preserve_syn_only *) reg [0:0] redist18_yAddr_uid51_fpDivTest_b_7_sticky_ena_q; + wire [0:0] redist18_yAddr_uid51_fpDivTest_b_7_enaAnd_q; + reg [8:0] redist19_yAddr_uid51_fpDivTest_b_14_outputreg0_q; + wire redist19_yAddr_uid51_fpDivTest_b_14_mem_reset0; + wire [8:0] redist19_yAddr_uid51_fpDivTest_b_14_mem_ia; + wire [2:0] redist19_yAddr_uid51_fpDivTest_b_14_mem_aa; + wire [2:0] redist19_yAddr_uid51_fpDivTest_b_14_mem_ab; + wire [8:0] redist19_yAddr_uid51_fpDivTest_b_14_mem_iq; + wire [8:0] redist19_yAddr_uid51_fpDivTest_b_14_mem_q; + wire redist19_yAddr_uid51_fpDivTest_b_14_mem_enaOr_rst; + wire [2:0] redist19_yAddr_uid51_fpDivTest_b_14_rdcnt_q; + (* preserve_syn_only *) reg [2:0] redist19_yAddr_uid51_fpDivTest_b_14_rdcnt_i; + (* preserve_syn_only *) reg redist19_yAddr_uid51_fpDivTest_b_14_rdcnt_eq; + wire [0:0] redist19_yAddr_uid51_fpDivTest_b_14_rdmux_s; + reg [2:0] redist19_yAddr_uid51_fpDivTest_b_14_rdmux_q; + reg [2:0] redist19_yAddr_uid51_fpDivTest_b_14_wraddr_q; + wire [2:0] redist19_yAddr_uid51_fpDivTest_b_14_mem_last_q; + wire [0:0] redist19_yAddr_uid51_fpDivTest_b_14_cmp_q; + reg [0:0] redist19_yAddr_uid51_fpDivTest_b_14_cmpReg_q; + wire [0:0] redist19_yAddr_uid51_fpDivTest_b_14_notEnable_q; + wire [0:0] redist19_yAddr_uid51_fpDivTest_b_14_nor_q; + (* preserve_syn_only *) reg [0:0] redist19_yAddr_uid51_fpDivTest_b_14_sticky_ena_q; + wire [0:0] redist19_yAddr_uid51_fpDivTest_b_14_enaAnd_q; + wire redist23_fracY_uid13_fpDivTest_b_22_mem_reset0; + wire [22:0] redist23_fracY_uid13_fpDivTest_b_22_mem_ia; + wire [4:0] redist23_fracY_uid13_fpDivTest_b_22_mem_aa; + wire [4:0] redist23_fracY_uid13_fpDivTest_b_22_mem_ab; + wire [22:0] redist23_fracY_uid13_fpDivTest_b_22_mem_iq; + wire [22:0] redist23_fracY_uid13_fpDivTest_b_22_mem_q; + wire redist23_fracY_uid13_fpDivTest_b_22_mem_enaOr_rst; + wire [4:0] redist23_fracY_uid13_fpDivTest_b_22_rdcnt_q; + (* preserve_syn_only *) reg [4:0] redist23_fracY_uid13_fpDivTest_b_22_rdcnt_i; + (* preserve_syn_only *) reg redist23_fracY_uid13_fpDivTest_b_22_rdcnt_eq; + wire [0:0] redist23_fracY_uid13_fpDivTest_b_22_rdmux_s; + reg [4:0] redist23_fracY_uid13_fpDivTest_b_22_rdmux_q; + reg [4:0] redist23_fracY_uid13_fpDivTest_b_22_wraddr_q; + wire [5:0] redist23_fracY_uid13_fpDivTest_b_22_mem_last_q; + wire [5:0] redist23_fracY_uid13_fpDivTest_b_22_cmp_b; + wire [0:0] redist23_fracY_uid13_fpDivTest_b_22_cmp_q; + reg [0:0] redist23_fracY_uid13_fpDivTest_b_22_cmpReg_q; + wire [0:0] redist23_fracY_uid13_fpDivTest_b_22_notEnable_q; + wire [0:0] redist23_fracY_uid13_fpDivTest_b_22_nor_q; + (* preserve_syn_only *) reg [0:0] redist23_fracY_uid13_fpDivTest_b_22_sticky_ena_q; + wire [0:0] redist23_fracY_uid13_fpDivTest_b_22_enaAnd_q; + wire redist26_expY_uid12_fpDivTest_b_23_mem_reset0; + wire [7:0] redist26_expY_uid12_fpDivTest_b_23_mem_ia; + wire [4:0] redist26_expY_uid12_fpDivTest_b_23_mem_aa; + wire [4:0] redist26_expY_uid12_fpDivTest_b_23_mem_ab; + wire [7:0] redist26_expY_uid12_fpDivTest_b_23_mem_iq; + wire [7:0] redist26_expY_uid12_fpDivTest_b_23_mem_q; + wire redist26_expY_uid12_fpDivTest_b_23_mem_enaOr_rst; + wire [4:0] redist26_expY_uid12_fpDivTest_b_23_rdcnt_q; + (* preserve_syn_only *) reg [4:0] redist26_expY_uid12_fpDivTest_b_23_rdcnt_i; + (* preserve_syn_only *) reg redist26_expY_uid12_fpDivTest_b_23_rdcnt_eq; + wire [0:0] redist26_expY_uid12_fpDivTest_b_23_rdmux_s; + reg [4:0] redist26_expY_uid12_fpDivTest_b_23_rdmux_q; + reg [4:0] redist26_expY_uid12_fpDivTest_b_23_wraddr_q; + wire [5:0] redist26_expY_uid12_fpDivTest_b_23_mem_last_q; + wire [5:0] redist26_expY_uid12_fpDivTest_b_23_cmp_b; + wire [0:0] redist26_expY_uid12_fpDivTest_b_23_cmp_q; + reg [0:0] redist26_expY_uid12_fpDivTest_b_23_cmpReg_q; + wire [0:0] redist26_expY_uid12_fpDivTest_b_23_notEnable_q; + wire [0:0] redist26_expY_uid12_fpDivTest_b_23_nor_q; + (* preserve_syn_only *) reg [0:0] redist26_expY_uid12_fpDivTest_b_23_sticky_ena_q; + wire [0:0] redist26_expY_uid12_fpDivTest_b_23_enaAnd_q; + reg [7:0] redist28_expY_uid12_fpDivTest_b_31_outputreg0_q; + wire redist28_expY_uid12_fpDivTest_b_31_mem_reset0; + wire [7:0] redist28_expY_uid12_fpDivTest_b_31_mem_ia; + wire [2:0] redist28_expY_uid12_fpDivTest_b_31_mem_aa; + wire [2:0] redist28_expY_uid12_fpDivTest_b_31_mem_ab; + wire [7:0] redist28_expY_uid12_fpDivTest_b_31_mem_iq; + wire [7:0] redist28_expY_uid12_fpDivTest_b_31_mem_q; + wire redist28_expY_uid12_fpDivTest_b_31_mem_enaOr_rst; + wire [2:0] redist28_expY_uid12_fpDivTest_b_31_rdcnt_q; + (* preserve_syn_only *) reg [2:0] redist28_expY_uid12_fpDivTest_b_31_rdcnt_i; + (* preserve_syn_only *) reg redist28_expY_uid12_fpDivTest_b_31_rdcnt_eq; + wire [0:0] redist28_expY_uid12_fpDivTest_b_31_rdmux_s; + reg [2:0] redist28_expY_uid12_fpDivTest_b_31_rdmux_q; + reg [2:0] redist28_expY_uid12_fpDivTest_b_31_wraddr_q; + wire [2:0] redist28_expY_uid12_fpDivTest_b_31_mem_last_q; + wire [0:0] redist28_expY_uid12_fpDivTest_b_31_cmp_q; + reg [0:0] redist28_expY_uid12_fpDivTest_b_31_cmpReg_q; + wire [0:0] redist28_expY_uid12_fpDivTest_b_31_notEnable_q; + wire [0:0] redist28_expY_uid12_fpDivTest_b_31_nor_q; + (* preserve_syn_only *) reg [0:0] redist28_expY_uid12_fpDivTest_b_31_sticky_ena_q; + wire [0:0] redist28_expY_uid12_fpDivTest_b_31_enaAnd_q; + reg [22:0] redist29_fracX_uid10_fpDivTest_b_17_outputreg0_q; + wire redist29_fracX_uid10_fpDivTest_b_17_mem_reset0; + wire [22:0] redist29_fracX_uid10_fpDivTest_b_17_mem_ia; + wire [3:0] redist29_fracX_uid10_fpDivTest_b_17_mem_aa; + wire [3:0] redist29_fracX_uid10_fpDivTest_b_17_mem_ab; + wire [22:0] redist29_fracX_uid10_fpDivTest_b_17_mem_iq; + wire [22:0] redist29_fracX_uid10_fpDivTest_b_17_mem_q; + wire redist29_fracX_uid10_fpDivTest_b_17_mem_enaOr_rst; + wire [3:0] redist29_fracX_uid10_fpDivTest_b_17_rdcnt_q; + (* preserve_syn_only *) reg [3:0] redist29_fracX_uid10_fpDivTest_b_17_rdcnt_i; + (* preserve_syn_only *) reg redist29_fracX_uid10_fpDivTest_b_17_rdcnt_eq; + wire [0:0] redist29_fracX_uid10_fpDivTest_b_17_rdmux_s; + reg [3:0] redist29_fracX_uid10_fpDivTest_b_17_rdmux_q; + reg [3:0] redist29_fracX_uid10_fpDivTest_b_17_wraddr_q; + wire [4:0] redist29_fracX_uid10_fpDivTest_b_17_mem_last_q; + wire [4:0] redist29_fracX_uid10_fpDivTest_b_17_cmp_b; + wire [0:0] redist29_fracX_uid10_fpDivTest_b_17_cmp_q; + reg [0:0] redist29_fracX_uid10_fpDivTest_b_17_cmpReg_q; + wire [0:0] redist29_fracX_uid10_fpDivTest_b_17_notEnable_q; + wire [0:0] redist29_fracX_uid10_fpDivTest_b_17_nor_q; + (* preserve_syn_only *) reg [0:0] redist29_fracX_uid10_fpDivTest_b_17_sticky_ena_q; + wire [0:0] redist29_fracX_uid10_fpDivTest_b_17_enaAnd_q; + wire redist30_fracX_uid10_fpDivTest_b_24_mem_reset0; + wire [22:0] redist30_fracX_uid10_fpDivTest_b_24_mem_ia; + wire [2:0] redist30_fracX_uid10_fpDivTest_b_24_mem_aa; + wire [2:0] redist30_fracX_uid10_fpDivTest_b_24_mem_ab; + wire [22:0] redist30_fracX_uid10_fpDivTest_b_24_mem_iq; + wire [22:0] redist30_fracX_uid10_fpDivTest_b_24_mem_q; + wire redist30_fracX_uid10_fpDivTest_b_24_mem_enaOr_rst; + wire [2:0] redist30_fracX_uid10_fpDivTest_b_24_rdcnt_q; + (* preserve_syn_only *) reg [2:0] redist30_fracX_uid10_fpDivTest_b_24_rdcnt_i; + (* preserve_syn_only *) reg redist30_fracX_uid10_fpDivTest_b_24_rdcnt_eq; + wire [0:0] redist30_fracX_uid10_fpDivTest_b_24_rdmux_s; + reg [2:0] redist30_fracX_uid10_fpDivTest_b_24_rdmux_q; + reg [2:0] redist30_fracX_uid10_fpDivTest_b_24_wraddr_q; + wire [3:0] redist30_fracX_uid10_fpDivTest_b_24_mem_last_q; + wire [3:0] redist30_fracX_uid10_fpDivTest_b_24_cmp_b; + wire [0:0] redist30_fracX_uid10_fpDivTest_b_24_cmp_q; + reg [0:0] redist30_fracX_uid10_fpDivTest_b_24_cmpReg_q; + wire [0:0] redist30_fracX_uid10_fpDivTest_b_24_notEnable_q; + wire [0:0] redist30_fracX_uid10_fpDivTest_b_24_nor_q; + (* preserve_syn_only *) reg [0:0] redist30_fracX_uid10_fpDivTest_b_24_sticky_ena_q; + wire [0:0] redist30_fracX_uid10_fpDivTest_b_24_enaAnd_q; + wire redist32_fracX_uid10_fpDivTest_b_32_mem_reset0; + wire [22:0] redist32_fracX_uid10_fpDivTest_b_32_mem_ia; + wire [2:0] redist32_fracX_uid10_fpDivTest_b_32_mem_aa; + wire [2:0] redist32_fracX_uid10_fpDivTest_b_32_mem_ab; + wire [22:0] redist32_fracX_uid10_fpDivTest_b_32_mem_iq; + wire [22:0] redist32_fracX_uid10_fpDivTest_b_32_mem_q; + wire redist32_fracX_uid10_fpDivTest_b_32_mem_enaOr_rst; + wire [2:0] redist32_fracX_uid10_fpDivTest_b_32_rdcnt_q; + (* preserve_syn_only *) reg [2:0] redist32_fracX_uid10_fpDivTest_b_32_rdcnt_i; + (* preserve_syn_only *) reg redist32_fracX_uid10_fpDivTest_b_32_rdcnt_eq; + wire [0:0] redist32_fracX_uid10_fpDivTest_b_32_rdmux_s; + reg [2:0] redist32_fracX_uid10_fpDivTest_b_32_rdmux_q; + reg [2:0] redist32_fracX_uid10_fpDivTest_b_32_wraddr_q; + wire [3:0] redist32_fracX_uid10_fpDivTest_b_32_mem_last_q; + wire [3:0] redist32_fracX_uid10_fpDivTest_b_32_cmp_b; + wire [0:0] redist32_fracX_uid10_fpDivTest_b_32_cmp_q; + reg [0:0] redist32_fracX_uid10_fpDivTest_b_32_cmpReg_q; + wire [0:0] redist32_fracX_uid10_fpDivTest_b_32_notEnable_q; + wire [0:0] redist32_fracX_uid10_fpDivTest_b_32_nor_q; + (* preserve_syn_only *) reg [0:0] redist32_fracX_uid10_fpDivTest_b_32_sticky_ena_q; + wire [0:0] redist32_fracX_uid10_fpDivTest_b_32_enaAnd_q; + wire redist33_expX_uid9_fpDivTest_b_23_mem_reset0; + wire [7:0] redist33_expX_uid9_fpDivTest_b_23_mem_ia; + wire [4:0] redist33_expX_uid9_fpDivTest_b_23_mem_aa; + wire [4:0] redist33_expX_uid9_fpDivTest_b_23_mem_ab; + wire [7:0] redist33_expX_uid9_fpDivTest_b_23_mem_iq; + wire [7:0] redist33_expX_uid9_fpDivTest_b_23_mem_q; + wire redist33_expX_uid9_fpDivTest_b_23_mem_enaOr_rst; + wire [4:0] redist33_expX_uid9_fpDivTest_b_23_rdcnt_q; + (* preserve_syn_only *) reg [4:0] redist33_expX_uid9_fpDivTest_b_23_rdcnt_i; + (* preserve_syn_only *) reg redist33_expX_uid9_fpDivTest_b_23_rdcnt_eq; + wire [0:0] redist33_expX_uid9_fpDivTest_b_23_rdmux_s; + reg [4:0] redist33_expX_uid9_fpDivTest_b_23_rdmux_q; + reg [4:0] redist33_expX_uid9_fpDivTest_b_23_wraddr_q; + wire [5:0] redist33_expX_uid9_fpDivTest_b_23_mem_last_q; + wire [5:0] redist33_expX_uid9_fpDivTest_b_23_cmp_b; + wire [0:0] redist33_expX_uid9_fpDivTest_b_23_cmp_q; + reg [0:0] redist33_expX_uid9_fpDivTest_b_23_cmpReg_q; + wire [0:0] redist33_expX_uid9_fpDivTest_b_23_notEnable_q; + wire [0:0] redist33_expX_uid9_fpDivTest_b_23_nor_q; + (* preserve_syn_only *) reg [0:0] redist33_expX_uid9_fpDivTest_b_23_sticky_ena_q; + wire [0:0] redist33_expX_uid9_fpDivTest_b_23_enaAnd_q; + reg [7:0] redist35_expX_uid9_fpDivTest_b_31_outputreg0_q; + wire redist35_expX_uid9_fpDivTest_b_31_mem_reset0; + wire [7:0] redist35_expX_uid9_fpDivTest_b_31_mem_ia; + wire [2:0] redist35_expX_uid9_fpDivTest_b_31_mem_aa; + wire [2:0] redist35_expX_uid9_fpDivTest_b_31_mem_ab; + wire [7:0] redist35_expX_uid9_fpDivTest_b_31_mem_iq; + wire [7:0] redist35_expX_uid9_fpDivTest_b_31_mem_q; + wire redist35_expX_uid9_fpDivTest_b_31_mem_enaOr_rst; + wire [2:0] redist35_expX_uid9_fpDivTest_b_31_rdcnt_q; + (* preserve_syn_only *) reg [2:0] redist35_expX_uid9_fpDivTest_b_31_rdcnt_i; + (* preserve_syn_only *) reg redist35_expX_uid9_fpDivTest_b_31_rdcnt_eq; + wire [0:0] redist35_expX_uid9_fpDivTest_b_31_rdmux_s; + reg [2:0] redist35_expX_uid9_fpDivTest_b_31_rdmux_q; + reg [2:0] redist35_expX_uid9_fpDivTest_b_31_wraddr_q; + wire [2:0] redist35_expX_uid9_fpDivTest_b_31_mem_last_q; + wire [0:0] redist35_expX_uid9_fpDivTest_b_31_cmp_q; + reg [0:0] redist35_expX_uid9_fpDivTest_b_31_cmpReg_q; + wire [0:0] redist35_expX_uid9_fpDivTest_b_31_notEnable_q; + wire [0:0] redist35_expX_uid9_fpDivTest_b_31_nor_q; + (* preserve_syn_only *) reg [0:0] redist35_expX_uid9_fpDivTest_b_31_sticky_ena_q; + wire [0:0] redist35_expX_uid9_fpDivTest_b_31_enaAnd_q; + + + // redist23_fracY_uid13_fpDivTest_b_22_notEnable(LOGICAL,300) + assign redist23_fracY_uid13_fpDivTest_b_22_notEnable_q = ~ (en); + + // redist23_fracY_uid13_fpDivTest_b_22_nor(LOGICAL,301) + assign redist23_fracY_uid13_fpDivTest_b_22_nor_q = ~ (redist23_fracY_uid13_fpDivTest_b_22_notEnable_q | redist23_fracY_uid13_fpDivTest_b_22_sticky_ena_q); + + // redist23_fracY_uid13_fpDivTest_b_22_mem_last(CONSTANT,297) + assign redist23_fracY_uid13_fpDivTest_b_22_mem_last_q = 6'b010011; + + // redist23_fracY_uid13_fpDivTest_b_22_cmp(LOGICAL,298) + assign redist23_fracY_uid13_fpDivTest_b_22_cmp_b = {1'b0, redist23_fracY_uid13_fpDivTest_b_22_rdmux_q}; + assign redist23_fracY_uid13_fpDivTest_b_22_cmp_q = redist23_fracY_uid13_fpDivTest_b_22_mem_last_q == redist23_fracY_uid13_fpDivTest_b_22_cmp_b ? 1'b1 : 1'b0; + + // redist23_fracY_uid13_fpDivTest_b_22_cmpReg(REG,299) + always @ (posedge clk) + begin + if (areset) + begin + redist23_fracY_uid13_fpDivTest_b_22_cmpReg_q <= 1'b0; + end + else if (en == 1'b1) + begin + redist23_fracY_uid13_fpDivTest_b_22_cmpReg_q <= redist23_fracY_uid13_fpDivTest_b_22_cmp_q; + end + end + + // redist23_fracY_uid13_fpDivTest_b_22_sticky_ena(REG,302) + always @ (posedge clk) + begin + if (areset) + begin + redist23_fracY_uid13_fpDivTest_b_22_sticky_ena_q <= 1'b0; + end + else if (redist23_fracY_uid13_fpDivTest_b_22_nor_q == 1'b1) + begin + redist23_fracY_uid13_fpDivTest_b_22_sticky_ena_q <= redist23_fracY_uid13_fpDivTest_b_22_cmpReg_q; + end + end + + // redist23_fracY_uid13_fpDivTest_b_22_enaAnd(LOGICAL,303) + assign redist23_fracY_uid13_fpDivTest_b_22_enaAnd_q = redist23_fracY_uid13_fpDivTest_b_22_sticky_ena_q & en; + + // redist23_fracY_uid13_fpDivTest_b_22_rdcnt(COUNTER,294) + // low=0, high=20, step=1, init=0 + always @ (posedge clk) + begin + if (areset) + begin + redist23_fracY_uid13_fpDivTest_b_22_rdcnt_i <= 5'd0; + redist23_fracY_uid13_fpDivTest_b_22_rdcnt_eq <= 1'b0; + end + else if (en == 1'b1) + begin + if (redist23_fracY_uid13_fpDivTest_b_22_rdcnt_i == 5'd19) + begin + redist23_fracY_uid13_fpDivTest_b_22_rdcnt_eq <= 1'b1; + end + else + begin + redist23_fracY_uid13_fpDivTest_b_22_rdcnt_eq <= 1'b0; + end + if (redist23_fracY_uid13_fpDivTest_b_22_rdcnt_eq == 1'b1) + begin + redist23_fracY_uid13_fpDivTest_b_22_rdcnt_i <= $unsigned(redist23_fracY_uid13_fpDivTest_b_22_rdcnt_i) + $unsigned(5'd12); + end + else + begin + redist23_fracY_uid13_fpDivTest_b_22_rdcnt_i <= $unsigned(redist23_fracY_uid13_fpDivTest_b_22_rdcnt_i) + $unsigned(5'd1); + end + end + end + assign redist23_fracY_uid13_fpDivTest_b_22_rdcnt_q = redist23_fracY_uid13_fpDivTest_b_22_rdcnt_i[4:0]; + + // redist23_fracY_uid13_fpDivTest_b_22_rdmux(MUX,295) + assign redist23_fracY_uid13_fpDivTest_b_22_rdmux_s = en; + always @(redist23_fracY_uid13_fpDivTest_b_22_rdmux_s or redist23_fracY_uid13_fpDivTest_b_22_wraddr_q or redist23_fracY_uid13_fpDivTest_b_22_rdcnt_q) + begin + unique case (redist23_fracY_uid13_fpDivTest_b_22_rdmux_s) + 1'b0 : redist23_fracY_uid13_fpDivTest_b_22_rdmux_q = redist23_fracY_uid13_fpDivTest_b_22_wraddr_q; + 1'b1 : redist23_fracY_uid13_fpDivTest_b_22_rdmux_q = redist23_fracY_uid13_fpDivTest_b_22_rdcnt_q; + default : redist23_fracY_uid13_fpDivTest_b_22_rdmux_q = 5'b0; + endcase + end + + // VCC(CONSTANT,1) + assign VCC_q = 1'b1; + + // fracY_uid13_fpDivTest(BITSELECT,12)@0 + assign fracY_uid13_fpDivTest_b = b[22:0]; + + // redist23_fracY_uid13_fpDivTest_b_22_wraddr(REG,296) + always @ (posedge clk) + begin + if (areset) + begin + redist23_fracY_uid13_fpDivTest_b_22_wraddr_q <= 5'b10100; + end + else + begin + redist23_fracY_uid13_fpDivTest_b_22_wraddr_q <= redist23_fracY_uid13_fpDivTest_b_22_rdmux_q; + end + end + + // redist23_fracY_uid13_fpDivTest_b_22_mem(DUALMEM,293) + assign redist23_fracY_uid13_fpDivTest_b_22_mem_ia = fracY_uid13_fpDivTest_b; + assign redist23_fracY_uid13_fpDivTest_b_22_mem_aa = redist23_fracY_uid13_fpDivTest_b_22_wraddr_q; + assign redist23_fracY_uid13_fpDivTest_b_22_mem_ab = redist23_fracY_uid13_fpDivTest_b_22_rdmux_q; + assign redist23_fracY_uid13_fpDivTest_b_22_mem_reset0 = areset; + altera_syncram #( + .ram_block_type("MLAB"), + .operation_mode("DUAL_PORT"), + .width_a(23), + .widthad_a(5), + .numwords_a(21), + .width_b(23), + .widthad_b(5), + .numwords_b(21), + .lpm_type("altera_syncram"), + .width_byteena_a(1), + .address_reg_b("CLOCK0"), + .indata_reg_b("CLOCK0"), + .rdcontrol_reg_b("CLOCK0"), + .byteena_reg_b("CLOCK0"), + .outdata_reg_b("CLOCK1"), + .outdata_sclr_b("SCLEAR"), + .clock_enable_input_a("NORMAL"), + .clock_enable_input_b("NORMAL"), + .clock_enable_output_b("NORMAL"), + .read_during_write_mode_mixed_ports("DONT_CARE"), + .power_up_uninitialized("TRUE"), + .intended_device_family("Stratix 10") + ) redist23_fracY_uid13_fpDivTest_b_22_mem_dmem ( + .clocken1(redist23_fracY_uid13_fpDivTest_b_22_mem_enaOr_rst), + .clocken0(VCC_q[0]), + .clock0(clk), + .sclr(redist23_fracY_uid13_fpDivTest_b_22_mem_reset0), + .clock1(clk), + .address_a(redist23_fracY_uid13_fpDivTest_b_22_mem_aa), + .data_a(redist23_fracY_uid13_fpDivTest_b_22_mem_ia), + .wren_a(en[0]), + .address_b(redist23_fracY_uid13_fpDivTest_b_22_mem_ab), + .q_b(redist23_fracY_uid13_fpDivTest_b_22_mem_iq), + .wren_b(), + .rden_a(), + .rden_b(), + .data_b(), + .clocken2(), + .clocken3(), + .aclr0(), + .aclr1(), + .addressstall_a(), + .addressstall_b(), + .byteena_a(), + .byteena_b(), + .eccencbypass(), + .eccencparity(), + .address2_a(), + .address2_b(), + .q_a(), + .eccstatus() + ); + assign redist23_fracY_uid13_fpDivTest_b_22_mem_q = redist23_fracY_uid13_fpDivTest_b_22_mem_iq[22:0]; + assign redist23_fracY_uid13_fpDivTest_b_22_mem_enaOr_rst = redist23_fracY_uid13_fpDivTest_b_22_enaAnd_q[0] | redist23_fracY_uid13_fpDivTest_b_22_mem_reset0; + + // redist24_fracY_uid13_fpDivTest_b_24(DELAY,210) + always @ (posedge clk) + begin + if (areset) + begin + redist24_fracY_uid13_fpDivTest_b_24_delay_0 <= '0; + redist24_fracY_uid13_fpDivTest_b_24_q <= '0; + end + else if (en == 1'b1) + begin + redist24_fracY_uid13_fpDivTest_b_24_delay_0 <= redist23_fracY_uid13_fpDivTest_b_22_mem_q; + redist24_fracY_uid13_fpDivTest_b_24_q <= redist24_fracY_uid13_fpDivTest_b_24_delay_0; + end + end + + // paddingY_uid15_fpDivTest(CONSTANT,14) + assign paddingY_uid15_fpDivTest_q = 23'b00000000000000000000000; + + // fracXIsZero_uid39_fpDivTest(LOGICAL,38)@24 + 1 + assign fracXIsZero_uid39_fpDivTest_qi = paddingY_uid15_fpDivTest_q == redist24_fracY_uid13_fpDivTest_b_24_q ? 1'b1 : 1'b0; + dspba_delay_ver #( .width(1), .depth(1), .reset_kind("SYNC"), .phase(0), .modulus(1) ) + fracXIsZero_uid39_fpDivTest_delay ( .xin(fracXIsZero_uid39_fpDivTest_qi), .xout(fracXIsZero_uid39_fpDivTest_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // cstAllOWE_uid18_fpDivTest(CONSTANT,17) + assign cstAllOWE_uid18_fpDivTest_q = 8'b11111111; + + // redist26_expY_uid12_fpDivTest_b_23_notEnable(LOGICAL,311) + assign redist26_expY_uid12_fpDivTest_b_23_notEnable_q = ~ (en); + + // redist26_expY_uid12_fpDivTest_b_23_nor(LOGICAL,312) + assign redist26_expY_uid12_fpDivTest_b_23_nor_q = ~ (redist26_expY_uid12_fpDivTest_b_23_notEnable_q | redist26_expY_uid12_fpDivTest_b_23_sticky_ena_q); + + // redist26_expY_uid12_fpDivTest_b_23_mem_last(CONSTANT,308) + assign redist26_expY_uid12_fpDivTest_b_23_mem_last_q = 6'b010100; + + // redist26_expY_uid12_fpDivTest_b_23_cmp(LOGICAL,309) + assign redist26_expY_uid12_fpDivTest_b_23_cmp_b = {1'b0, redist26_expY_uid12_fpDivTest_b_23_rdmux_q}; + assign redist26_expY_uid12_fpDivTest_b_23_cmp_q = redist26_expY_uid12_fpDivTest_b_23_mem_last_q == redist26_expY_uid12_fpDivTest_b_23_cmp_b ? 1'b1 : 1'b0; + + // redist26_expY_uid12_fpDivTest_b_23_cmpReg(REG,310) + always @ (posedge clk) + begin + if (areset) + begin + redist26_expY_uid12_fpDivTest_b_23_cmpReg_q <= 1'b0; + end + else if (en == 1'b1) + begin + redist26_expY_uid12_fpDivTest_b_23_cmpReg_q <= redist26_expY_uid12_fpDivTest_b_23_cmp_q; + end + end + + // redist26_expY_uid12_fpDivTest_b_23_sticky_ena(REG,313) + always @ (posedge clk) + begin + if (areset) + begin + redist26_expY_uid12_fpDivTest_b_23_sticky_ena_q <= 1'b0; + end + else if (redist26_expY_uid12_fpDivTest_b_23_nor_q == 1'b1) + begin + redist26_expY_uid12_fpDivTest_b_23_sticky_ena_q <= redist26_expY_uid12_fpDivTest_b_23_cmpReg_q; + end + end + + // redist26_expY_uid12_fpDivTest_b_23_enaAnd(LOGICAL,314) + assign redist26_expY_uid12_fpDivTest_b_23_enaAnd_q = redist26_expY_uid12_fpDivTest_b_23_sticky_ena_q & en; + + // redist26_expY_uid12_fpDivTest_b_23_rdcnt(COUNTER,305) + // low=0, high=21, step=1, init=0 + always @ (posedge clk) + begin + if (areset) + begin + redist26_expY_uid12_fpDivTest_b_23_rdcnt_i <= 5'd0; + redist26_expY_uid12_fpDivTest_b_23_rdcnt_eq <= 1'b0; + end + else if (en == 1'b1) + begin + if (redist26_expY_uid12_fpDivTest_b_23_rdcnt_i == 5'd20) + begin + redist26_expY_uid12_fpDivTest_b_23_rdcnt_eq <= 1'b1; + end + else + begin + redist26_expY_uid12_fpDivTest_b_23_rdcnt_eq <= 1'b0; + end + if (redist26_expY_uid12_fpDivTest_b_23_rdcnt_eq == 1'b1) + begin + redist26_expY_uid12_fpDivTest_b_23_rdcnt_i <= $unsigned(redist26_expY_uid12_fpDivTest_b_23_rdcnt_i) + $unsigned(5'd11); + end + else + begin + redist26_expY_uid12_fpDivTest_b_23_rdcnt_i <= $unsigned(redist26_expY_uid12_fpDivTest_b_23_rdcnt_i) + $unsigned(5'd1); + end + end + end + assign redist26_expY_uid12_fpDivTest_b_23_rdcnt_q = redist26_expY_uid12_fpDivTest_b_23_rdcnt_i[4:0]; + + // redist26_expY_uid12_fpDivTest_b_23_rdmux(MUX,306) + assign redist26_expY_uid12_fpDivTest_b_23_rdmux_s = en; + always @(redist26_expY_uid12_fpDivTest_b_23_rdmux_s or redist26_expY_uid12_fpDivTest_b_23_wraddr_q or redist26_expY_uid12_fpDivTest_b_23_rdcnt_q) + begin + unique case (redist26_expY_uid12_fpDivTest_b_23_rdmux_s) + 1'b0 : redist26_expY_uid12_fpDivTest_b_23_rdmux_q = redist26_expY_uid12_fpDivTest_b_23_wraddr_q; + 1'b1 : redist26_expY_uid12_fpDivTest_b_23_rdmux_q = redist26_expY_uid12_fpDivTest_b_23_rdcnt_q; + default : redist26_expY_uid12_fpDivTest_b_23_rdmux_q = 5'b0; + endcase + end + + // expY_uid12_fpDivTest(BITSELECT,11)@0 + assign expY_uid12_fpDivTest_b = b[30:23]; + + // redist26_expY_uid12_fpDivTest_b_23_wraddr(REG,307) + always @ (posedge clk) + begin + if (areset) + begin + redist26_expY_uid12_fpDivTest_b_23_wraddr_q <= 5'b10101; + end + else + begin + redist26_expY_uid12_fpDivTest_b_23_wraddr_q <= redist26_expY_uid12_fpDivTest_b_23_rdmux_q; + end + end + + // redist26_expY_uid12_fpDivTest_b_23_mem(DUALMEM,304) + assign redist26_expY_uid12_fpDivTest_b_23_mem_ia = expY_uid12_fpDivTest_b; + assign redist26_expY_uid12_fpDivTest_b_23_mem_aa = redist26_expY_uid12_fpDivTest_b_23_wraddr_q; + assign redist26_expY_uid12_fpDivTest_b_23_mem_ab = redist26_expY_uid12_fpDivTest_b_23_rdmux_q; + assign redist26_expY_uid12_fpDivTest_b_23_mem_reset0 = areset; + altera_syncram #( + .ram_block_type("MLAB"), + .operation_mode("DUAL_PORT"), + .width_a(8), + .widthad_a(5), + .numwords_a(22), + .width_b(8), + .widthad_b(5), + .numwords_b(22), + .lpm_type("altera_syncram"), + .width_byteena_a(1), + .address_reg_b("CLOCK0"), + .indata_reg_b("CLOCK0"), + .rdcontrol_reg_b("CLOCK0"), + .byteena_reg_b("CLOCK0"), + .outdata_reg_b("CLOCK1"), + .outdata_sclr_b("SCLEAR"), + .clock_enable_input_a("NORMAL"), + .clock_enable_input_b("NORMAL"), + .clock_enable_output_b("NORMAL"), + .read_during_write_mode_mixed_ports("DONT_CARE"), + .power_up_uninitialized("TRUE"), + .intended_device_family("Stratix 10") + ) redist26_expY_uid12_fpDivTest_b_23_mem_dmem ( + .clocken1(redist26_expY_uid12_fpDivTest_b_23_mem_enaOr_rst), + .clocken0(VCC_q[0]), + .clock0(clk), + .sclr(redist26_expY_uid12_fpDivTest_b_23_mem_reset0), + .clock1(clk), + .address_a(redist26_expY_uid12_fpDivTest_b_23_mem_aa), + .data_a(redist26_expY_uid12_fpDivTest_b_23_mem_ia), + .wren_a(en[0]), + .address_b(redist26_expY_uid12_fpDivTest_b_23_mem_ab), + .q_b(redist26_expY_uid12_fpDivTest_b_23_mem_iq), + .wren_b(), + .rden_a(), + .rden_b(), + .data_b(), + .clocken2(), + .clocken3(), + .aclr0(), + .aclr1(), + .addressstall_a(), + .addressstall_b(), + .byteena_a(), + .byteena_b(), + .eccencbypass(), + .eccencparity(), + .address2_a(), + .address2_b(), + .q_a(), + .eccstatus() + ); + assign redist26_expY_uid12_fpDivTest_b_23_mem_q = redist26_expY_uid12_fpDivTest_b_23_mem_iq[7:0]; + assign redist26_expY_uid12_fpDivTest_b_23_mem_enaOr_rst = redist26_expY_uid12_fpDivTest_b_23_enaAnd_q[0] | redist26_expY_uid12_fpDivTest_b_23_mem_reset0; + + // redist27_expY_uid12_fpDivTest_b_24(DELAY,213) + always @ (posedge clk) + begin + if (areset) + begin + redist27_expY_uid12_fpDivTest_b_24_q <= '0; + end + else if (en == 1'b1) + begin + redist27_expY_uid12_fpDivTest_b_24_q <= redist26_expY_uid12_fpDivTest_b_23_mem_q; + end + end + + // expXIsMax_uid38_fpDivTest(LOGICAL,37)@24 + 1 + assign expXIsMax_uid38_fpDivTest_qi = redist27_expY_uid12_fpDivTest_b_24_q == cstAllOWE_uid18_fpDivTest_q ? 1'b1 : 1'b0; + dspba_delay_ver #( .width(1), .depth(1), .reset_kind("SYNC"), .phase(0), .modulus(1) ) + expXIsMax_uid38_fpDivTest_delay ( .xin(expXIsMax_uid38_fpDivTest_qi), .xout(expXIsMax_uid38_fpDivTest_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // excI_y_uid41_fpDivTest(LOGICAL,40)@25 + assign excI_y_uid41_fpDivTest_q = expXIsMax_uid38_fpDivTest_q & fracXIsZero_uid39_fpDivTest_q; + + // redist30_fracX_uid10_fpDivTest_b_24_notEnable(LOGICAL,346) + assign redist30_fracX_uid10_fpDivTest_b_24_notEnable_q = ~ (en); + + // redist30_fracX_uid10_fpDivTest_b_24_nor(LOGICAL,347) + assign redist30_fracX_uid10_fpDivTest_b_24_nor_q = ~ (redist30_fracX_uid10_fpDivTest_b_24_notEnable_q | redist30_fracX_uid10_fpDivTest_b_24_sticky_ena_q); + + // redist30_fracX_uid10_fpDivTest_b_24_mem_last(CONSTANT,343) + assign redist30_fracX_uid10_fpDivTest_b_24_mem_last_q = 4'b0100; + + // redist30_fracX_uid10_fpDivTest_b_24_cmp(LOGICAL,344) + assign redist30_fracX_uid10_fpDivTest_b_24_cmp_b = {1'b0, redist30_fracX_uid10_fpDivTest_b_24_rdmux_q}; + assign redist30_fracX_uid10_fpDivTest_b_24_cmp_q = redist30_fracX_uid10_fpDivTest_b_24_mem_last_q == redist30_fracX_uid10_fpDivTest_b_24_cmp_b ? 1'b1 : 1'b0; + + // redist30_fracX_uid10_fpDivTest_b_24_cmpReg(REG,345) + always @ (posedge clk) + begin + if (areset) + begin + redist30_fracX_uid10_fpDivTest_b_24_cmpReg_q <= 1'b0; + end + else if (en == 1'b1) + begin + redist30_fracX_uid10_fpDivTest_b_24_cmpReg_q <= redist30_fracX_uid10_fpDivTest_b_24_cmp_q; + end + end + + // redist30_fracX_uid10_fpDivTest_b_24_sticky_ena(REG,348) + always @ (posedge clk) + begin + if (areset) + begin + redist30_fracX_uid10_fpDivTest_b_24_sticky_ena_q <= 1'b0; + end + else if (redist30_fracX_uid10_fpDivTest_b_24_nor_q == 1'b1) + begin + redist30_fracX_uid10_fpDivTest_b_24_sticky_ena_q <= redist30_fracX_uid10_fpDivTest_b_24_cmpReg_q; + end + end + + // redist30_fracX_uid10_fpDivTest_b_24_enaAnd(LOGICAL,349) + assign redist30_fracX_uid10_fpDivTest_b_24_enaAnd_q = redist30_fracX_uid10_fpDivTest_b_24_sticky_ena_q & en; + + // redist30_fracX_uid10_fpDivTest_b_24_rdcnt(COUNTER,340) + // low=0, high=5, step=1, init=0 + always @ (posedge clk) + begin + if (areset) + begin + redist30_fracX_uid10_fpDivTest_b_24_rdcnt_i <= 3'd0; + redist30_fracX_uid10_fpDivTest_b_24_rdcnt_eq <= 1'b0; + end + else if (en == 1'b1) + begin + if (redist30_fracX_uid10_fpDivTest_b_24_rdcnt_i == 3'd4) + begin + redist30_fracX_uid10_fpDivTest_b_24_rdcnt_eq <= 1'b1; + end + else + begin + redist30_fracX_uid10_fpDivTest_b_24_rdcnt_eq <= 1'b0; + end + if (redist30_fracX_uid10_fpDivTest_b_24_rdcnt_eq == 1'b1) + begin + redist30_fracX_uid10_fpDivTest_b_24_rdcnt_i <= $unsigned(redist30_fracX_uid10_fpDivTest_b_24_rdcnt_i) + $unsigned(3'd3); + end + else + begin + redist30_fracX_uid10_fpDivTest_b_24_rdcnt_i <= $unsigned(redist30_fracX_uid10_fpDivTest_b_24_rdcnt_i) + $unsigned(3'd1); + end + end + end + assign redist30_fracX_uid10_fpDivTest_b_24_rdcnt_q = redist30_fracX_uid10_fpDivTest_b_24_rdcnt_i[2:0]; + + // redist30_fracX_uid10_fpDivTest_b_24_rdmux(MUX,341) + assign redist30_fracX_uid10_fpDivTest_b_24_rdmux_s = en; + always @(redist30_fracX_uid10_fpDivTest_b_24_rdmux_s or redist30_fracX_uid10_fpDivTest_b_24_wraddr_q or redist30_fracX_uid10_fpDivTest_b_24_rdcnt_q) + begin + unique case (redist30_fracX_uid10_fpDivTest_b_24_rdmux_s) + 1'b0 : redist30_fracX_uid10_fpDivTest_b_24_rdmux_q = redist30_fracX_uid10_fpDivTest_b_24_wraddr_q; + 1'b1 : redist30_fracX_uid10_fpDivTest_b_24_rdmux_q = redist30_fracX_uid10_fpDivTest_b_24_rdcnt_q; + default : redist30_fracX_uid10_fpDivTest_b_24_rdmux_q = 3'b0; + endcase + end + + // redist29_fracX_uid10_fpDivTest_b_17_notEnable(LOGICAL,335) + assign redist29_fracX_uid10_fpDivTest_b_17_notEnable_q = ~ (en); + + // redist29_fracX_uid10_fpDivTest_b_17_nor(LOGICAL,336) + assign redist29_fracX_uid10_fpDivTest_b_17_nor_q = ~ (redist29_fracX_uid10_fpDivTest_b_17_notEnable_q | redist29_fracX_uid10_fpDivTest_b_17_sticky_ena_q); + + // redist29_fracX_uid10_fpDivTest_b_17_mem_last(CONSTANT,332) + assign redist29_fracX_uid10_fpDivTest_b_17_mem_last_q = 5'b01101; + + // redist29_fracX_uid10_fpDivTest_b_17_cmp(LOGICAL,333) + assign redist29_fracX_uid10_fpDivTest_b_17_cmp_b = {1'b0, redist29_fracX_uid10_fpDivTest_b_17_rdmux_q}; + assign redist29_fracX_uid10_fpDivTest_b_17_cmp_q = redist29_fracX_uid10_fpDivTest_b_17_mem_last_q == redist29_fracX_uid10_fpDivTest_b_17_cmp_b ? 1'b1 : 1'b0; + + // redist29_fracX_uid10_fpDivTest_b_17_cmpReg(REG,334) + always @ (posedge clk) + begin + if (areset) + begin + redist29_fracX_uid10_fpDivTest_b_17_cmpReg_q <= 1'b0; + end + else if (en == 1'b1) + begin + redist29_fracX_uid10_fpDivTest_b_17_cmpReg_q <= redist29_fracX_uid10_fpDivTest_b_17_cmp_q; + end + end + + // redist29_fracX_uid10_fpDivTest_b_17_sticky_ena(REG,337) + always @ (posedge clk) + begin + if (areset) + begin + redist29_fracX_uid10_fpDivTest_b_17_sticky_ena_q <= 1'b0; + end + else if (redist29_fracX_uid10_fpDivTest_b_17_nor_q == 1'b1) + begin + redist29_fracX_uid10_fpDivTest_b_17_sticky_ena_q <= redist29_fracX_uid10_fpDivTest_b_17_cmpReg_q; + end + end + + // redist29_fracX_uid10_fpDivTest_b_17_enaAnd(LOGICAL,338) + assign redist29_fracX_uid10_fpDivTest_b_17_enaAnd_q = redist29_fracX_uid10_fpDivTest_b_17_sticky_ena_q & en; + + // redist29_fracX_uid10_fpDivTest_b_17_rdcnt(COUNTER,329) + // low=0, high=14, step=1, init=0 + always @ (posedge clk) + begin + if (areset) + begin + redist29_fracX_uid10_fpDivTest_b_17_rdcnt_i <= 4'd0; + redist29_fracX_uid10_fpDivTest_b_17_rdcnt_eq <= 1'b0; + end + else if (en == 1'b1) + begin + if (redist29_fracX_uid10_fpDivTest_b_17_rdcnt_i == 4'd13) + begin + redist29_fracX_uid10_fpDivTest_b_17_rdcnt_eq <= 1'b1; + end + else + begin + redist29_fracX_uid10_fpDivTest_b_17_rdcnt_eq <= 1'b0; + end + if (redist29_fracX_uid10_fpDivTest_b_17_rdcnt_eq == 1'b1) + begin + redist29_fracX_uid10_fpDivTest_b_17_rdcnt_i <= $unsigned(redist29_fracX_uid10_fpDivTest_b_17_rdcnt_i) + $unsigned(4'd2); + end + else + begin + redist29_fracX_uid10_fpDivTest_b_17_rdcnt_i <= $unsigned(redist29_fracX_uid10_fpDivTest_b_17_rdcnt_i) + $unsigned(4'd1); + end + end + end + assign redist29_fracX_uid10_fpDivTest_b_17_rdcnt_q = redist29_fracX_uid10_fpDivTest_b_17_rdcnt_i[3:0]; + + // redist29_fracX_uid10_fpDivTest_b_17_rdmux(MUX,330) + assign redist29_fracX_uid10_fpDivTest_b_17_rdmux_s = en; + always @(redist29_fracX_uid10_fpDivTest_b_17_rdmux_s or redist29_fracX_uid10_fpDivTest_b_17_wraddr_q or redist29_fracX_uid10_fpDivTest_b_17_rdcnt_q) + begin + unique case (redist29_fracX_uid10_fpDivTest_b_17_rdmux_s) + 1'b0 : redist29_fracX_uid10_fpDivTest_b_17_rdmux_q = redist29_fracX_uid10_fpDivTest_b_17_wraddr_q; + 1'b1 : redist29_fracX_uid10_fpDivTest_b_17_rdmux_q = redist29_fracX_uid10_fpDivTest_b_17_rdcnt_q; + default : redist29_fracX_uid10_fpDivTest_b_17_rdmux_q = 4'b0; + endcase + end + + // fracX_uid10_fpDivTest(BITSELECT,9)@0 + assign fracX_uid10_fpDivTest_b = a[22:0]; + + // redist29_fracX_uid10_fpDivTest_b_17_wraddr(REG,331) + always @ (posedge clk) + begin + if (areset) + begin + redist29_fracX_uid10_fpDivTest_b_17_wraddr_q <= 4'b1110; + end + else + begin + redist29_fracX_uid10_fpDivTest_b_17_wraddr_q <= redist29_fracX_uid10_fpDivTest_b_17_rdmux_q; + end + end + + // redist29_fracX_uid10_fpDivTest_b_17_mem(DUALMEM,328) + assign redist29_fracX_uid10_fpDivTest_b_17_mem_ia = fracX_uid10_fpDivTest_b; + assign redist29_fracX_uid10_fpDivTest_b_17_mem_aa = redist29_fracX_uid10_fpDivTest_b_17_wraddr_q; + assign redist29_fracX_uid10_fpDivTest_b_17_mem_ab = redist29_fracX_uid10_fpDivTest_b_17_rdmux_q; + assign redist29_fracX_uid10_fpDivTest_b_17_mem_reset0 = areset; + altera_syncram #( + .ram_block_type("MLAB"), + .operation_mode("DUAL_PORT"), + .width_a(23), + .widthad_a(4), + .numwords_a(15), + .width_b(23), + .widthad_b(4), + .numwords_b(15), + .lpm_type("altera_syncram"), + .width_byteena_a(1), + .address_reg_b("CLOCK0"), + .indata_reg_b("CLOCK0"), + .rdcontrol_reg_b("CLOCK0"), + .byteena_reg_b("CLOCK0"), + .outdata_reg_b("CLOCK1"), + .outdata_sclr_b("SCLEAR"), + .clock_enable_input_a("NORMAL"), + .clock_enable_input_b("NORMAL"), + .clock_enable_output_b("NORMAL"), + .read_during_write_mode_mixed_ports("DONT_CARE"), + .power_up_uninitialized("TRUE"), + .intended_device_family("Stratix 10") + ) redist29_fracX_uid10_fpDivTest_b_17_mem_dmem ( + .clocken1(redist29_fracX_uid10_fpDivTest_b_17_mem_enaOr_rst), + .clocken0(VCC_q[0]), + .clock0(clk), + .sclr(redist29_fracX_uid10_fpDivTest_b_17_mem_reset0), + .clock1(clk), + .address_a(redist29_fracX_uid10_fpDivTest_b_17_mem_aa), + .data_a(redist29_fracX_uid10_fpDivTest_b_17_mem_ia), + .wren_a(en[0]), + .address_b(redist29_fracX_uid10_fpDivTest_b_17_mem_ab), + .q_b(redist29_fracX_uid10_fpDivTest_b_17_mem_iq), + .wren_b(), + .rden_a(), + .rden_b(), + .data_b(), + .clocken2(), + .clocken3(), + .aclr0(), + .aclr1(), + .addressstall_a(), + .addressstall_b(), + .byteena_a(), + .byteena_b(), + .eccencbypass(), + .eccencparity(), + .address2_a(), + .address2_b(), + .q_a(), + .eccstatus() + ); + assign redist29_fracX_uid10_fpDivTest_b_17_mem_q = redist29_fracX_uid10_fpDivTest_b_17_mem_iq[22:0]; + assign redist29_fracX_uid10_fpDivTest_b_17_mem_enaOr_rst = redist29_fracX_uid10_fpDivTest_b_17_enaAnd_q[0] | redist29_fracX_uid10_fpDivTest_b_17_mem_reset0; + + // redist29_fracX_uid10_fpDivTest_b_17_outputreg0(DELAY,327) + always @ (posedge clk) + begin + if (areset) + begin + redist29_fracX_uid10_fpDivTest_b_17_outputreg0_q <= '0; + end + else if (en == 1'b1) + begin + redist29_fracX_uid10_fpDivTest_b_17_outputreg0_q <= redist29_fracX_uid10_fpDivTest_b_17_mem_q; + end + end + + // redist30_fracX_uid10_fpDivTest_b_24_wraddr(REG,342) + always @ (posedge clk) + begin + if (areset) + begin + redist30_fracX_uid10_fpDivTest_b_24_wraddr_q <= 3'b101; + end + else + begin + redist30_fracX_uid10_fpDivTest_b_24_wraddr_q <= redist30_fracX_uid10_fpDivTest_b_24_rdmux_q; + end + end + + // redist30_fracX_uid10_fpDivTest_b_24_mem(DUALMEM,339) + assign redist30_fracX_uid10_fpDivTest_b_24_mem_ia = redist29_fracX_uid10_fpDivTest_b_17_outputreg0_q; + assign redist30_fracX_uid10_fpDivTest_b_24_mem_aa = redist30_fracX_uid10_fpDivTest_b_24_wraddr_q; + assign redist30_fracX_uid10_fpDivTest_b_24_mem_ab = redist30_fracX_uid10_fpDivTest_b_24_rdmux_q; + assign redist30_fracX_uid10_fpDivTest_b_24_mem_reset0 = areset; + altera_syncram #( + .ram_block_type("MLAB"), + .operation_mode("DUAL_PORT"), + .width_a(23), + .widthad_a(3), + .numwords_a(6), + .width_b(23), + .widthad_b(3), + .numwords_b(6), + .lpm_type("altera_syncram"), + .width_byteena_a(1), + .address_reg_b("CLOCK0"), + .indata_reg_b("CLOCK0"), + .rdcontrol_reg_b("CLOCK0"), + .byteena_reg_b("CLOCK0"), + .outdata_reg_b("CLOCK1"), + .outdata_sclr_b("SCLEAR"), + .clock_enable_input_a("NORMAL"), + .clock_enable_input_b("NORMAL"), + .clock_enable_output_b("NORMAL"), + .read_during_write_mode_mixed_ports("DONT_CARE"), + .power_up_uninitialized("TRUE"), + .intended_device_family("Stratix 10") + ) redist30_fracX_uid10_fpDivTest_b_24_mem_dmem ( + .clocken1(redist30_fracX_uid10_fpDivTest_b_24_mem_enaOr_rst), + .clocken0(VCC_q[0]), + .clock0(clk), + .sclr(redist30_fracX_uid10_fpDivTest_b_24_mem_reset0), + .clock1(clk), + .address_a(redist30_fracX_uid10_fpDivTest_b_24_mem_aa), + .data_a(redist30_fracX_uid10_fpDivTest_b_24_mem_ia), + .wren_a(en[0]), + .address_b(redist30_fracX_uid10_fpDivTest_b_24_mem_ab), + .q_b(redist30_fracX_uid10_fpDivTest_b_24_mem_iq), + .wren_b(), + .rden_a(), + .rden_b(), + .data_b(), + .clocken2(), + .clocken3(), + .aclr0(), + .aclr1(), + .addressstall_a(), + .addressstall_b(), + .byteena_a(), + .byteena_b(), + .eccencbypass(), + .eccencparity(), + .address2_a(), + .address2_b(), + .q_a(), + .eccstatus() + ); + assign redist30_fracX_uid10_fpDivTest_b_24_mem_q = redist30_fracX_uid10_fpDivTest_b_24_mem_iq[22:0]; + assign redist30_fracX_uid10_fpDivTest_b_24_mem_enaOr_rst = redist30_fracX_uid10_fpDivTest_b_24_enaAnd_q[0] | redist30_fracX_uid10_fpDivTest_b_24_mem_reset0; + + // fracXIsZero_uid25_fpDivTest(LOGICAL,24)@24 + 1 + assign fracXIsZero_uid25_fpDivTest_qi = paddingY_uid15_fpDivTest_q == redist30_fracX_uid10_fpDivTest_b_24_mem_q ? 1'b1 : 1'b0; + dspba_delay_ver #( .width(1), .depth(1), .reset_kind("SYNC"), .phase(0), .modulus(1) ) + fracXIsZero_uid25_fpDivTest_delay ( .xin(fracXIsZero_uid25_fpDivTest_qi), .xout(fracXIsZero_uid25_fpDivTest_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // redist33_expX_uid9_fpDivTest_b_23_notEnable(LOGICAL,368) + assign redist33_expX_uid9_fpDivTest_b_23_notEnable_q = ~ (en); + + // redist33_expX_uid9_fpDivTest_b_23_nor(LOGICAL,369) + assign redist33_expX_uid9_fpDivTest_b_23_nor_q = ~ (redist33_expX_uid9_fpDivTest_b_23_notEnable_q | redist33_expX_uid9_fpDivTest_b_23_sticky_ena_q); + + // redist33_expX_uid9_fpDivTest_b_23_mem_last(CONSTANT,365) + assign redist33_expX_uid9_fpDivTest_b_23_mem_last_q = 6'b010100; + + // redist33_expX_uid9_fpDivTest_b_23_cmp(LOGICAL,366) + assign redist33_expX_uid9_fpDivTest_b_23_cmp_b = {1'b0, redist33_expX_uid9_fpDivTest_b_23_rdmux_q}; + assign redist33_expX_uid9_fpDivTest_b_23_cmp_q = redist33_expX_uid9_fpDivTest_b_23_mem_last_q == redist33_expX_uid9_fpDivTest_b_23_cmp_b ? 1'b1 : 1'b0; + + // redist33_expX_uid9_fpDivTest_b_23_cmpReg(REG,367) + always @ (posedge clk) + begin + if (areset) + begin + redist33_expX_uid9_fpDivTest_b_23_cmpReg_q <= 1'b0; + end + else if (en == 1'b1) + begin + redist33_expX_uid9_fpDivTest_b_23_cmpReg_q <= redist33_expX_uid9_fpDivTest_b_23_cmp_q; + end + end + + // redist33_expX_uid9_fpDivTest_b_23_sticky_ena(REG,370) + always @ (posedge clk) + begin + if (areset) + begin + redist33_expX_uid9_fpDivTest_b_23_sticky_ena_q <= 1'b0; + end + else if (redist33_expX_uid9_fpDivTest_b_23_nor_q == 1'b1) + begin + redist33_expX_uid9_fpDivTest_b_23_sticky_ena_q <= redist33_expX_uid9_fpDivTest_b_23_cmpReg_q; + end + end + + // redist33_expX_uid9_fpDivTest_b_23_enaAnd(LOGICAL,371) + assign redist33_expX_uid9_fpDivTest_b_23_enaAnd_q = redist33_expX_uid9_fpDivTest_b_23_sticky_ena_q & en; + + // redist33_expX_uid9_fpDivTest_b_23_rdcnt(COUNTER,362) + // low=0, high=21, step=1, init=0 + always @ (posedge clk) + begin + if (areset) + begin + redist33_expX_uid9_fpDivTest_b_23_rdcnt_i <= 5'd0; + redist33_expX_uid9_fpDivTest_b_23_rdcnt_eq <= 1'b0; + end + else if (en == 1'b1) + begin + if (redist33_expX_uid9_fpDivTest_b_23_rdcnt_i == 5'd20) + begin + redist33_expX_uid9_fpDivTest_b_23_rdcnt_eq <= 1'b1; + end + else + begin + redist33_expX_uid9_fpDivTest_b_23_rdcnt_eq <= 1'b0; + end + if (redist33_expX_uid9_fpDivTest_b_23_rdcnt_eq == 1'b1) + begin + redist33_expX_uid9_fpDivTest_b_23_rdcnt_i <= $unsigned(redist33_expX_uid9_fpDivTest_b_23_rdcnt_i) + $unsigned(5'd11); + end + else + begin + redist33_expX_uid9_fpDivTest_b_23_rdcnt_i <= $unsigned(redist33_expX_uid9_fpDivTest_b_23_rdcnt_i) + $unsigned(5'd1); + end + end + end + assign redist33_expX_uid9_fpDivTest_b_23_rdcnt_q = redist33_expX_uid9_fpDivTest_b_23_rdcnt_i[4:0]; + + // redist33_expX_uid9_fpDivTest_b_23_rdmux(MUX,363) + assign redist33_expX_uid9_fpDivTest_b_23_rdmux_s = en; + always @(redist33_expX_uid9_fpDivTest_b_23_rdmux_s or redist33_expX_uid9_fpDivTest_b_23_wraddr_q or redist33_expX_uid9_fpDivTest_b_23_rdcnt_q) + begin + unique case (redist33_expX_uid9_fpDivTest_b_23_rdmux_s) + 1'b0 : redist33_expX_uid9_fpDivTest_b_23_rdmux_q = redist33_expX_uid9_fpDivTest_b_23_wraddr_q; + 1'b1 : redist33_expX_uid9_fpDivTest_b_23_rdmux_q = redist33_expX_uid9_fpDivTest_b_23_rdcnt_q; + default : redist33_expX_uid9_fpDivTest_b_23_rdmux_q = 5'b0; + endcase + end + + // expX_uid9_fpDivTest(BITSELECT,8)@0 + assign expX_uid9_fpDivTest_b = a[30:23]; + + // redist33_expX_uid9_fpDivTest_b_23_wraddr(REG,364) + always @ (posedge clk) + begin + if (areset) + begin + redist33_expX_uid9_fpDivTest_b_23_wraddr_q <= 5'b10101; + end + else + begin + redist33_expX_uid9_fpDivTest_b_23_wraddr_q <= redist33_expX_uid9_fpDivTest_b_23_rdmux_q; + end + end + + // redist33_expX_uid9_fpDivTest_b_23_mem(DUALMEM,361) + assign redist33_expX_uid9_fpDivTest_b_23_mem_ia = expX_uid9_fpDivTest_b; + assign redist33_expX_uid9_fpDivTest_b_23_mem_aa = redist33_expX_uid9_fpDivTest_b_23_wraddr_q; + assign redist33_expX_uid9_fpDivTest_b_23_mem_ab = redist33_expX_uid9_fpDivTest_b_23_rdmux_q; + assign redist33_expX_uid9_fpDivTest_b_23_mem_reset0 = areset; + altera_syncram #( + .ram_block_type("MLAB"), + .operation_mode("DUAL_PORT"), + .width_a(8), + .widthad_a(5), + .numwords_a(22), + .width_b(8), + .widthad_b(5), + .numwords_b(22), + .lpm_type("altera_syncram"), + .width_byteena_a(1), + .address_reg_b("CLOCK0"), + .indata_reg_b("CLOCK0"), + .rdcontrol_reg_b("CLOCK0"), + .byteena_reg_b("CLOCK0"), + .outdata_reg_b("CLOCK1"), + .outdata_sclr_b("SCLEAR"), + .clock_enable_input_a("NORMAL"), + .clock_enable_input_b("NORMAL"), + .clock_enable_output_b("NORMAL"), + .read_during_write_mode_mixed_ports("DONT_CARE"), + .power_up_uninitialized("TRUE"), + .intended_device_family("Stratix 10") + ) redist33_expX_uid9_fpDivTest_b_23_mem_dmem ( + .clocken1(redist33_expX_uid9_fpDivTest_b_23_mem_enaOr_rst), + .clocken0(VCC_q[0]), + .clock0(clk), + .sclr(redist33_expX_uid9_fpDivTest_b_23_mem_reset0), + .clock1(clk), + .address_a(redist33_expX_uid9_fpDivTest_b_23_mem_aa), + .data_a(redist33_expX_uid9_fpDivTest_b_23_mem_ia), + .wren_a(en[0]), + .address_b(redist33_expX_uid9_fpDivTest_b_23_mem_ab), + .q_b(redist33_expX_uid9_fpDivTest_b_23_mem_iq), + .wren_b(), + .rden_a(), + .rden_b(), + .data_b(), + .clocken2(), + .clocken3(), + .aclr0(), + .aclr1(), + .addressstall_a(), + .addressstall_b(), + .byteena_a(), + .byteena_b(), + .eccencbypass(), + .eccencparity(), + .address2_a(), + .address2_b(), + .q_a(), + .eccstatus() + ); + assign redist33_expX_uid9_fpDivTest_b_23_mem_q = redist33_expX_uid9_fpDivTest_b_23_mem_iq[7:0]; + assign redist33_expX_uid9_fpDivTest_b_23_mem_enaOr_rst = redist33_expX_uid9_fpDivTest_b_23_enaAnd_q[0] | redist33_expX_uid9_fpDivTest_b_23_mem_reset0; + + // redist34_expX_uid9_fpDivTest_b_24(DELAY,220) + always @ (posedge clk) + begin + if (areset) + begin + redist34_expX_uid9_fpDivTest_b_24_q <= '0; + end + else if (en == 1'b1) + begin + redist34_expX_uid9_fpDivTest_b_24_q <= redist33_expX_uid9_fpDivTest_b_23_mem_q; + end + end + + // expXIsMax_uid24_fpDivTest(LOGICAL,23)@24 + assign expXIsMax_uid24_fpDivTest_q = redist34_expX_uid9_fpDivTest_b_24_q == cstAllOWE_uid18_fpDivTest_q ? 1'b1 : 1'b0; + + // redist21_expXIsMax_uid24_fpDivTest_q_1(DELAY,207) + always @ (posedge clk) + begin + if (areset) + begin + redist21_expXIsMax_uid24_fpDivTest_q_1_q <= '0; + end + else if (en == 1'b1) + begin + redist21_expXIsMax_uid24_fpDivTest_q_1_q <= expXIsMax_uid24_fpDivTest_q; + end + end + + // excI_x_uid27_fpDivTest(LOGICAL,26)@25 + assign excI_x_uid27_fpDivTest_q = redist21_expXIsMax_uid24_fpDivTest_q_1_q & fracXIsZero_uid25_fpDivTest_q; + + // excXIYI_uid130_fpDivTest(LOGICAL,129)@25 + assign excXIYI_uid130_fpDivTest_q = excI_x_uid27_fpDivTest_q & excI_y_uid41_fpDivTest_q; + + // fracXIsNotZero_uid40_fpDivTest(LOGICAL,39)@25 + assign fracXIsNotZero_uid40_fpDivTest_q = ~ (fracXIsZero_uid39_fpDivTest_q); + + // excN_y_uid42_fpDivTest(LOGICAL,41)@25 + assign excN_y_uid42_fpDivTest_q = expXIsMax_uid38_fpDivTest_q & fracXIsNotZero_uid40_fpDivTest_q; + + // fracXIsNotZero_uid26_fpDivTest(LOGICAL,25)@25 + assign fracXIsNotZero_uid26_fpDivTest_q = ~ (fracXIsZero_uid25_fpDivTest_q); + + // excN_x_uid28_fpDivTest(LOGICAL,27)@25 + assign excN_x_uid28_fpDivTest_q = redist21_expXIsMax_uid24_fpDivTest_q_1_q & fracXIsNotZero_uid26_fpDivTest_q; + + // cstAllZWE_uid20_fpDivTest(CONSTANT,19) + assign cstAllZWE_uid20_fpDivTest_q = 8'b00000000; + + // excZ_y_uid37_fpDivTest(LOGICAL,36)@24 + 1 + assign excZ_y_uid37_fpDivTest_qi = redist27_expY_uid12_fpDivTest_b_24_q == cstAllZWE_uid20_fpDivTest_q ? 1'b1 : 1'b0; + dspba_delay_ver #( .width(1), .depth(1), .reset_kind("SYNC"), .phase(0), .modulus(1) ) + excZ_y_uid37_fpDivTest_delay ( .xin(excZ_y_uid37_fpDivTest_qi), .xout(excZ_y_uid37_fpDivTest_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // excZ_x_uid23_fpDivTest(LOGICAL,22)@24 + assign excZ_x_uid23_fpDivTest_q = redist34_expX_uid9_fpDivTest_b_24_q == cstAllZWE_uid20_fpDivTest_q ? 1'b1 : 1'b0; + + // redist22_excZ_x_uid23_fpDivTest_q_1(DELAY,208) + always @ (posedge clk) + begin + if (areset) + begin + redist22_excZ_x_uid23_fpDivTest_q_1_q <= '0; + end + else if (en == 1'b1) + begin + redist22_excZ_x_uid23_fpDivTest_q_1_q <= excZ_x_uid23_fpDivTest_q; + end + end + + // excXZYZ_uid129_fpDivTest(LOGICAL,128)@25 + assign excXZYZ_uid129_fpDivTest_q = redist22_excZ_x_uid23_fpDivTest_q_1_q & excZ_y_uid37_fpDivTest_q; + + // excRNaN_uid131_fpDivTest(LOGICAL,130)@25 + assign excRNaN_uid131_fpDivTest_q = excXZYZ_uid129_fpDivTest_q | excN_x_uid28_fpDivTest_q | excN_y_uid42_fpDivTest_q | excXIYI_uid130_fpDivTest_q; + + // invExcRNaN_uid142_fpDivTest(LOGICAL,141)@25 + assign invExcRNaN_uid142_fpDivTest_q = ~ (excRNaN_uid131_fpDivTest_q); + + // signY_uid14_fpDivTest(BITSELECT,13)@0 + assign signY_uid14_fpDivTest_b = b[31:31]; + + // signX_uid11_fpDivTest(BITSELECT,10)@0 + assign signX_uid11_fpDivTest_b = a[31:31]; + + // signR_uid46_fpDivTest(LOGICAL,45)@0 + 1 + assign signR_uid46_fpDivTest_qi = signX_uid11_fpDivTest_b ^ signY_uid14_fpDivTest_b; + dspba_delay_ver #( .width(1), .depth(1), .reset_kind("SYNC"), .phase(0), .modulus(1) ) + signR_uid46_fpDivTest_delay ( .xin(signR_uid46_fpDivTest_qi), .xout(signR_uid46_fpDivTest_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // redist20_signR_uid46_fpDivTest_q_25(DELAY,206) + dspba_delay_ver #( .width(1), .depth(24), .reset_kind("SYNC"), .phase(0), .modulus(1) ) + redist20_signR_uid46_fpDivTest_q_25 ( .xin(signR_uid46_fpDivTest_q), .xout(redist20_signR_uid46_fpDivTest_q_25_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // sRPostExc_uid143_fpDivTest(LOGICAL,142)@25 + 1 + assign sRPostExc_uid143_fpDivTest_qi = redist20_signR_uid46_fpDivTest_q_25_q & invExcRNaN_uid142_fpDivTest_q; + dspba_delay_ver #( .width(1), .depth(1), .reset_kind("SYNC"), .phase(0), .modulus(1) ) + sRPostExc_uid143_fpDivTest_delay ( .xin(sRPostExc_uid143_fpDivTest_qi), .xout(sRPostExc_uid143_fpDivTest_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // redist2_sRPostExc_uid143_fpDivTest_q_9(DELAY,188) + dspba_delay_ver #( .width(1), .depth(8), .reset_kind("SYNC"), .phase(0), .modulus(1) ) + redist2_sRPostExc_uid143_fpDivTest_q_9 ( .xin(sRPostExc_uid143_fpDivTest_q), .xout(redist2_sRPostExc_uid143_fpDivTest_q_9_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // redist4_fracPostRndFT_uid104_fpDivTest_b_8_notEnable(LOGICAL,230) + assign redist4_fracPostRndFT_uid104_fpDivTest_b_8_notEnable_q = ~ (en); + + // redist4_fracPostRndFT_uid104_fpDivTest_b_8_nor(LOGICAL,231) + assign redist4_fracPostRndFT_uid104_fpDivTest_b_8_nor_q = ~ (redist4_fracPostRndFT_uid104_fpDivTest_b_8_notEnable_q | redist4_fracPostRndFT_uid104_fpDivTest_b_8_sticky_ena_q); + + // redist4_fracPostRndFT_uid104_fpDivTest_b_8_mem_last(CONSTANT,227) + assign redist4_fracPostRndFT_uid104_fpDivTest_b_8_mem_last_q = 4'b0101; + + // redist4_fracPostRndFT_uid104_fpDivTest_b_8_cmp(LOGICAL,228) + assign redist4_fracPostRndFT_uid104_fpDivTest_b_8_cmp_b = {1'b0, redist4_fracPostRndFT_uid104_fpDivTest_b_8_rdmux_q}; + assign redist4_fracPostRndFT_uid104_fpDivTest_b_8_cmp_q = redist4_fracPostRndFT_uid104_fpDivTest_b_8_mem_last_q == redist4_fracPostRndFT_uid104_fpDivTest_b_8_cmp_b ? 1'b1 : 1'b0; + + // redist4_fracPostRndFT_uid104_fpDivTest_b_8_cmpReg(REG,229) + always @ (posedge clk) + begin + if (areset) + begin + redist4_fracPostRndFT_uid104_fpDivTest_b_8_cmpReg_q <= 1'b0; + end + else if (en == 1'b1) + begin + redist4_fracPostRndFT_uid104_fpDivTest_b_8_cmpReg_q <= redist4_fracPostRndFT_uid104_fpDivTest_b_8_cmp_q; + end + end + + // redist4_fracPostRndFT_uid104_fpDivTest_b_8_sticky_ena(REG,232) + always @ (posedge clk) + begin + if (areset) + begin + redist4_fracPostRndFT_uid104_fpDivTest_b_8_sticky_ena_q <= 1'b0; + end + else if (redist4_fracPostRndFT_uid104_fpDivTest_b_8_nor_q == 1'b1) + begin + redist4_fracPostRndFT_uid104_fpDivTest_b_8_sticky_ena_q <= redist4_fracPostRndFT_uid104_fpDivTest_b_8_cmpReg_q; + end + end + + // redist4_fracPostRndFT_uid104_fpDivTest_b_8_enaAnd(LOGICAL,233) + assign redist4_fracPostRndFT_uid104_fpDivTest_b_8_enaAnd_q = redist4_fracPostRndFT_uid104_fpDivTest_b_8_sticky_ena_q & en; + + // redist4_fracPostRndFT_uid104_fpDivTest_b_8_rdcnt(COUNTER,224) + // low=0, high=6, step=1, init=0 + always @ (posedge clk) + begin + if (areset) + begin + redist4_fracPostRndFT_uid104_fpDivTest_b_8_rdcnt_i <= 3'd0; + redist4_fracPostRndFT_uid104_fpDivTest_b_8_rdcnt_eq <= 1'b0; + end + else if (en == 1'b1) + begin + if (redist4_fracPostRndFT_uid104_fpDivTest_b_8_rdcnt_i == 3'd5) + begin + redist4_fracPostRndFT_uid104_fpDivTest_b_8_rdcnt_eq <= 1'b1; + end + else + begin + redist4_fracPostRndFT_uid104_fpDivTest_b_8_rdcnt_eq <= 1'b0; + end + if (redist4_fracPostRndFT_uid104_fpDivTest_b_8_rdcnt_eq == 1'b1) + begin + redist4_fracPostRndFT_uid104_fpDivTest_b_8_rdcnt_i <= $unsigned(redist4_fracPostRndFT_uid104_fpDivTest_b_8_rdcnt_i) + $unsigned(3'd2); + end + else + begin + redist4_fracPostRndFT_uid104_fpDivTest_b_8_rdcnt_i <= $unsigned(redist4_fracPostRndFT_uid104_fpDivTest_b_8_rdcnt_i) + $unsigned(3'd1); + end + end + end + assign redist4_fracPostRndFT_uid104_fpDivTest_b_8_rdcnt_q = redist4_fracPostRndFT_uid104_fpDivTest_b_8_rdcnt_i[2:0]; + + // redist4_fracPostRndFT_uid104_fpDivTest_b_8_rdmux(MUX,225) + assign redist4_fracPostRndFT_uid104_fpDivTest_b_8_rdmux_s = en; + always @(redist4_fracPostRndFT_uid104_fpDivTest_b_8_rdmux_s or redist4_fracPostRndFT_uid104_fpDivTest_b_8_wraddr_q or redist4_fracPostRndFT_uid104_fpDivTest_b_8_rdcnt_q) + begin + unique case (redist4_fracPostRndFT_uid104_fpDivTest_b_8_rdmux_s) + 1'b0 : redist4_fracPostRndFT_uid104_fpDivTest_b_8_rdmux_q = redist4_fracPostRndFT_uid104_fpDivTest_b_8_wraddr_q; + 1'b1 : redist4_fracPostRndFT_uid104_fpDivTest_b_8_rdmux_q = redist4_fracPostRndFT_uid104_fpDivTest_b_8_rdcnt_q; + default : redist4_fracPostRndFT_uid104_fpDivTest_b_8_rdmux_q = 3'b0; + endcase + end + + // redist31_fracX_uid10_fpDivTest_b_25(DELAY,217) + always @ (posedge clk) + begin + if (areset) + begin + redist31_fracX_uid10_fpDivTest_b_25_q <= '0; + end + else if (en == 1'b1) + begin + redist31_fracX_uid10_fpDivTest_b_25_q <= redist30_fracX_uid10_fpDivTest_b_24_mem_q; + end + end + + // GND(CONSTANT,0) + assign GND_q = 1'b0; + + // fracXExt_uid77_fpDivTest(BITJOIN,76)@25 + assign fracXExt_uid77_fpDivTest_q = {redist31_fracX_uid10_fpDivTest_b_25_q, GND_q}; + + // redist12_lOAdded_uid57_fpDivTest_q_6_notEnable(LOGICAL,253) + assign redist12_lOAdded_uid57_fpDivTest_q_6_notEnable_q = ~ (en); + + // redist12_lOAdded_uid57_fpDivTest_q_6_nor(LOGICAL,254) + assign redist12_lOAdded_uid57_fpDivTest_q_6_nor_q = ~ (redist12_lOAdded_uid57_fpDivTest_q_6_notEnable_q | redist12_lOAdded_uid57_fpDivTest_q_6_sticky_ena_q); + + // redist12_lOAdded_uid57_fpDivTest_q_6_mem_last(CONSTANT,250) + assign redist12_lOAdded_uid57_fpDivTest_q_6_mem_last_q = 3'b011; + + // redist12_lOAdded_uid57_fpDivTest_q_6_cmp(LOGICAL,251) + assign redist12_lOAdded_uid57_fpDivTest_q_6_cmp_q = redist12_lOAdded_uid57_fpDivTest_q_6_mem_last_q == redist12_lOAdded_uid57_fpDivTest_q_6_rdmux_q ? 1'b1 : 1'b0; + + // redist12_lOAdded_uid57_fpDivTest_q_6_cmpReg(REG,252) + always @ (posedge clk) + begin + if (areset) + begin + redist12_lOAdded_uid57_fpDivTest_q_6_cmpReg_q <= 1'b0; + end + else if (en == 1'b1) + begin + redist12_lOAdded_uid57_fpDivTest_q_6_cmpReg_q <= redist12_lOAdded_uid57_fpDivTest_q_6_cmp_q; + end + end + + // redist12_lOAdded_uid57_fpDivTest_q_6_sticky_ena(REG,255) + always @ (posedge clk) + begin + if (areset) + begin + redist12_lOAdded_uid57_fpDivTest_q_6_sticky_ena_q <= 1'b0; + end + else if (redist12_lOAdded_uid57_fpDivTest_q_6_nor_q == 1'b1) + begin + redist12_lOAdded_uid57_fpDivTest_q_6_sticky_ena_q <= redist12_lOAdded_uid57_fpDivTest_q_6_cmpReg_q; + end + end + + // redist12_lOAdded_uid57_fpDivTest_q_6_enaAnd(LOGICAL,256) + assign redist12_lOAdded_uid57_fpDivTest_q_6_enaAnd_q = redist12_lOAdded_uid57_fpDivTest_q_6_sticky_ena_q & en; + + // redist12_lOAdded_uid57_fpDivTest_q_6_rdcnt(COUNTER,247) + // low=0, high=4, step=1, init=0 + always @ (posedge clk) + begin + if (areset) + begin + redist12_lOAdded_uid57_fpDivTest_q_6_rdcnt_i <= 3'd0; + redist12_lOAdded_uid57_fpDivTest_q_6_rdcnt_eq <= 1'b0; + end + else if (en == 1'b1) + begin + if (redist12_lOAdded_uid57_fpDivTest_q_6_rdcnt_i == 3'd3) + begin + redist12_lOAdded_uid57_fpDivTest_q_6_rdcnt_eq <= 1'b1; + end + else + begin + redist12_lOAdded_uid57_fpDivTest_q_6_rdcnt_eq <= 1'b0; + end + if (redist12_lOAdded_uid57_fpDivTest_q_6_rdcnt_eq == 1'b1) + begin + redist12_lOAdded_uid57_fpDivTest_q_6_rdcnt_i <= $unsigned(redist12_lOAdded_uid57_fpDivTest_q_6_rdcnt_i) + $unsigned(3'd4); + end + else + begin + redist12_lOAdded_uid57_fpDivTest_q_6_rdcnt_i <= $unsigned(redist12_lOAdded_uid57_fpDivTest_q_6_rdcnt_i) + $unsigned(3'd1); + end + end + end + assign redist12_lOAdded_uid57_fpDivTest_q_6_rdcnt_q = redist12_lOAdded_uid57_fpDivTest_q_6_rdcnt_i[2:0]; + + // redist12_lOAdded_uid57_fpDivTest_q_6_rdmux(MUX,248) + assign redist12_lOAdded_uid57_fpDivTest_q_6_rdmux_s = en; + always @(redist12_lOAdded_uid57_fpDivTest_q_6_rdmux_s or redist12_lOAdded_uid57_fpDivTest_q_6_wraddr_q or redist12_lOAdded_uid57_fpDivTest_q_6_rdcnt_q) + begin + unique case (redist12_lOAdded_uid57_fpDivTest_q_6_rdmux_s) + 1'b0 : redist12_lOAdded_uid57_fpDivTest_q_6_rdmux_q = redist12_lOAdded_uid57_fpDivTest_q_6_wraddr_q; + 1'b1 : redist12_lOAdded_uid57_fpDivTest_q_6_rdmux_q = redist12_lOAdded_uid57_fpDivTest_q_6_rdcnt_q; + default : redist12_lOAdded_uid57_fpDivTest_q_6_rdmux_q = 3'b0; + endcase + end + + // lOAdded_uid57_fpDivTest(BITJOIN,56)@17 + assign lOAdded_uid57_fpDivTest_q = {VCC_q, redist29_fracX_uid10_fpDivTest_b_17_outputreg0_q}; + + // redist12_lOAdded_uid57_fpDivTest_q_6_wraddr(REG,249) + always @ (posedge clk) + begin + if (areset) + begin + redist12_lOAdded_uid57_fpDivTest_q_6_wraddr_q <= 3'b100; + end + else + begin + redist12_lOAdded_uid57_fpDivTest_q_6_wraddr_q <= redist12_lOAdded_uid57_fpDivTest_q_6_rdmux_q; + end + end + + // redist12_lOAdded_uid57_fpDivTest_q_6_mem(DUALMEM,246) + assign redist12_lOAdded_uid57_fpDivTest_q_6_mem_ia = lOAdded_uid57_fpDivTest_q; + assign redist12_lOAdded_uid57_fpDivTest_q_6_mem_aa = redist12_lOAdded_uid57_fpDivTest_q_6_wraddr_q; + assign redist12_lOAdded_uid57_fpDivTest_q_6_mem_ab = redist12_lOAdded_uid57_fpDivTest_q_6_rdmux_q; + assign redist12_lOAdded_uid57_fpDivTest_q_6_mem_reset0 = areset; + altera_syncram #( + .ram_block_type("MLAB"), + .operation_mode("DUAL_PORT"), + .width_a(24), + .widthad_a(3), + .numwords_a(5), + .width_b(24), + .widthad_b(3), + .numwords_b(5), + .lpm_type("altera_syncram"), + .width_byteena_a(1), + .address_reg_b("CLOCK0"), + .indata_reg_b("CLOCK0"), + .rdcontrol_reg_b("CLOCK0"), + .byteena_reg_b("CLOCK0"), + .outdata_reg_b("CLOCK1"), + .outdata_sclr_b("SCLEAR"), + .clock_enable_input_a("NORMAL"), + .clock_enable_input_b("NORMAL"), + .clock_enable_output_b("NORMAL"), + .read_during_write_mode_mixed_ports("DONT_CARE"), + .power_up_uninitialized("TRUE"), + .intended_device_family("Stratix 10") + ) redist12_lOAdded_uid57_fpDivTest_q_6_mem_dmem ( + .clocken1(redist12_lOAdded_uid57_fpDivTest_q_6_mem_enaOr_rst), + .clocken0(VCC_q[0]), + .clock0(clk), + .sclr(redist12_lOAdded_uid57_fpDivTest_q_6_mem_reset0), + .clock1(clk), + .address_a(redist12_lOAdded_uid57_fpDivTest_q_6_mem_aa), + .data_a(redist12_lOAdded_uid57_fpDivTest_q_6_mem_ia), + .wren_a(en[0]), + .address_b(redist12_lOAdded_uid57_fpDivTest_q_6_mem_ab), + .q_b(redist12_lOAdded_uid57_fpDivTest_q_6_mem_iq), + .wren_b(), + .rden_a(), + .rden_b(), + .data_b(), + .clocken2(), + .clocken3(), + .aclr0(), + .aclr1(), + .addressstall_a(), + .addressstall_b(), + .byteena_a(), + .byteena_b(), + .eccencbypass(), + .eccencparity(), + .address2_a(), + .address2_b(), + .q_a(), + .eccstatus() + ); + assign redist12_lOAdded_uid57_fpDivTest_q_6_mem_q = redist12_lOAdded_uid57_fpDivTest_q_6_mem_iq[23:0]; + assign redist12_lOAdded_uid57_fpDivTest_q_6_mem_enaOr_rst = redist12_lOAdded_uid57_fpDivTest_q_6_enaAnd_q[0] | redist12_lOAdded_uid57_fpDivTest_q_6_mem_reset0; + + // z4_uid60_fpDivTest(CONSTANT,59) + assign z4_uid60_fpDivTest_q = 4'b0000; + + // oFracXZ4_uid61_fpDivTest(BITJOIN,60)@23 + assign oFracXZ4_uid61_fpDivTest_q = {redist12_lOAdded_uid57_fpDivTest_q_6_mem_q, z4_uid60_fpDivTest_q}; + + // yAddr_uid51_fpDivTest(BITSELECT,50)@0 + assign yAddr_uid51_fpDivTest_b = fracY_uid13_fpDivTest_b[22:14]; + + // memoryC2_uid152_invTables_lutmem(DUALMEM,181)@0 + 2 + // in j@20000000 + assign memoryC2_uid152_invTables_lutmem_aa = yAddr_uid51_fpDivTest_b; + assign memoryC2_uid152_invTables_lutmem_reset0 = areset; + altera_syncram #( + .ram_block_type("M20K"), + .operation_mode("ROM"), + .width_a(13), + .widthad_a(9), + .numwords_a(512), + .lpm_type("altera_syncram"), + .width_byteena_a(1), + .outdata_reg_a("CLOCK0"), + .outdata_sclr_a("SCLEAR"), + .clock_enable_input_a("NORMAL"), + .power_up_uninitialized("FALSE"), + .init_file("acl_fdiv_memoryC2_uid152_invTables_lutmem.hex"), + .init_file_layout("PORT_A"), + .intended_device_family("Stratix 10") + ) memoryC2_uid152_invTables_lutmem_dmem ( + .clocken0(en[0]), + .sclr(memoryC2_uid152_invTables_lutmem_reset0), + .clock0(clk), + .address_a(memoryC2_uid152_invTables_lutmem_aa), + .q_a(memoryC2_uid152_invTables_lutmem_ir), + .wren_a(), + .wren_b(), + .rden_a(), + .rden_b(), + .data_a(), + .data_b(), + .address_b(), + .clock1(), + .clocken1(), + .clocken2(), + .clocken3(), + .aclr0(), + .aclr1(), + .addressstall_a(), + .addressstall_b(), + .byteena_a(), + .byteena_b(), + .eccencbypass(), + .eccencparity(), + .address2_a(), + .address2_b(), + .q_b(), + .eccstatus() + ); + assign memoryC2_uid152_invTables_lutmem_r = memoryC2_uid152_invTables_lutmem_ir[12:0]; + assign memoryC2_uid152_invTables_lutmem_enaOr_rst = en[0] | memoryC2_uid152_invTables_lutmem_reset0; + + // redist0_memoryC2_uid152_invTables_lutmem_r_1(DELAY,186) + always @ (posedge clk) + begin + if (areset) + begin + redist0_memoryC2_uid152_invTables_lutmem_r_1_q <= '0; + end + else if (en == 1'b1) + begin + redist0_memoryC2_uid152_invTables_lutmem_r_1_q <= memoryC2_uid152_invTables_lutmem_r; + end + end + + // yPE_uid52_fpDivTest(BITSELECT,51)@0 + assign yPE_uid52_fpDivTest_b = b[13:0]; + + // redist16_yPE_uid52_fpDivTest_b_3(DELAY,202) + always @ (posedge clk) + begin + if (areset) + begin + redist16_yPE_uid52_fpDivTest_b_3_delay_0 <= '0; + redist16_yPE_uid52_fpDivTest_b_3_delay_1 <= '0; + redist16_yPE_uid52_fpDivTest_b_3_q <= '0; + end + else if (en == 1'b1) + begin + redist16_yPE_uid52_fpDivTest_b_3_delay_0 <= yPE_uid52_fpDivTest_b; + redist16_yPE_uid52_fpDivTest_b_3_delay_1 <= redist16_yPE_uid52_fpDivTest_b_3_delay_0; + redist16_yPE_uid52_fpDivTest_b_3_q <= redist16_yPE_uid52_fpDivTest_b_3_delay_1; + end + end + + // yT1_uid158_invPolyEval(BITSELECT,157)@3 + assign yT1_uid158_invPolyEval_b = redist16_yPE_uid52_fpDivTest_b_3_q[13:1]; + + // prodXY_uid174_pT1_uid159_invPolyEval_cma(CHAINMULTADD,184)@3 + 5 + // out q@9 + assign prodXY_uid174_pT1_uid159_invPolyEval_cma_reset = areset; + assign prodXY_uid174_pT1_uid159_invPolyEval_cma_ena0 = en[0] | prodXY_uid174_pT1_uid159_invPolyEval_cma_reset; + assign prodXY_uid174_pT1_uid159_invPolyEval_cma_ena1 = prodXY_uid174_pT1_uid159_invPolyEval_cma_ena0; + assign prodXY_uid174_pT1_uid159_invPolyEval_cma_ena2 = prodXY_uid174_pT1_uid159_invPolyEval_cma_ena0; + always @ (posedge clk) + begin + if (0) + begin + end + else + begin + if (en == 1'b1) + begin + prodXY_uid174_pT1_uid159_invPolyEval_cma_ah[0] <= yT1_uid158_invPolyEval_b; + prodXY_uid174_pT1_uid159_invPolyEval_cma_ch[0] <= redist0_memoryC2_uid152_invTables_lutmem_r_1_q; + end + end + end + + assign prodXY_uid174_pT1_uid159_invPolyEval_cma_a0 = prodXY_uid174_pT1_uid159_invPolyEval_cma_ah[0]; + assign prodXY_uid174_pT1_uid159_invPolyEval_cma_c0 = prodXY_uid174_pT1_uid159_invPolyEval_cma_ch[0]; + fourteennm_mac #( + .operation_mode("m18x18_full"), + .clear_type("sclr"), + .ay_scan_in_clock("0"), + .ay_scan_in_width(13), + .ax_clock("0"), + .ax_width(13), + .signed_may("false"), + .signed_max("true"), + .input_pipeline_clock("2"), + .second_pipeline_clock("2"), + .output_clock("1"), + .result_a_width(26) + ) prodXY_uid174_pT1_uid159_invPolyEval_cma_DSP0 ( + .clk({clk,clk,clk}), + .ena({ prodXY_uid174_pT1_uid159_invPolyEval_cma_ena2, prodXY_uid174_pT1_uid159_invPolyEval_cma_ena1, prodXY_uid174_pT1_uid159_invPolyEval_cma_ena0 }), + .clr({ prodXY_uid174_pT1_uid159_invPolyEval_cma_reset, prodXY_uid174_pT1_uid159_invPolyEval_cma_reset }), + .ay(prodXY_uid174_pT1_uid159_invPolyEval_cma_a0), + .ax(prodXY_uid174_pT1_uid159_invPolyEval_cma_c0), + .resulta(prodXY_uid174_pT1_uid159_invPolyEval_cma_s0), + .accumulate(), + .loadconst(), + .negate(), + .sub(), + .az(), + .coefsela(), + .bx(), + .by(), + .bz(), + .coefselb(), + .scanin(), + .scanout(), + .chainin(), + .chainout(), + .resultb(), + .dfxlfsrena(), + .dfxmisrena(), + .dftout() + ); + dspba_delay_ver #( .width(26), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1) ) + prodXY_uid174_pT1_uid159_invPolyEval_cma_delay ( .xin(prodXY_uid174_pT1_uid159_invPolyEval_cma_s0), .xout(prodXY_uid174_pT1_uid159_invPolyEval_cma_qq), .ena(en[0]), .clk(clk), .aclr(areset) ); + assign prodXY_uid174_pT1_uid159_invPolyEval_cma_q = prodXY_uid174_pT1_uid159_invPolyEval_cma_qq[25:0]; + + // osig_uid175_pT1_uid159_invPolyEval(BITSELECT,174)@9 + assign osig_uid175_pT1_uid159_invPolyEval_b = prodXY_uid174_pT1_uid159_invPolyEval_cma_q[25:12]; + + // highBBits_uid161_invPolyEval(BITSELECT,160)@9 + assign highBBits_uid161_invPolyEval_b = osig_uid175_pT1_uid159_invPolyEval_b[13:1]; + + // redist18_yAddr_uid51_fpDivTest_b_7_notEnable(LOGICAL,277) + assign redist18_yAddr_uid51_fpDivTest_b_7_notEnable_q = ~ (en); + + // redist18_yAddr_uid51_fpDivTest_b_7_nor(LOGICAL,278) + assign redist18_yAddr_uid51_fpDivTest_b_7_nor_q = ~ (redist18_yAddr_uid51_fpDivTest_b_7_notEnable_q | redist18_yAddr_uid51_fpDivTest_b_7_sticky_ena_q); + + // redist18_yAddr_uid51_fpDivTest_b_7_mem_last(CONSTANT,274) + assign redist18_yAddr_uid51_fpDivTest_b_7_mem_last_q = 3'b011; + + // redist18_yAddr_uid51_fpDivTest_b_7_cmp(LOGICAL,275) + assign redist18_yAddr_uid51_fpDivTest_b_7_cmp_q = redist18_yAddr_uid51_fpDivTest_b_7_mem_last_q == redist18_yAddr_uid51_fpDivTest_b_7_rdmux_q ? 1'b1 : 1'b0; + + // redist18_yAddr_uid51_fpDivTest_b_7_cmpReg(REG,276) + always @ (posedge clk) + begin + if (areset) + begin + redist18_yAddr_uid51_fpDivTest_b_7_cmpReg_q <= 1'b0; + end + else if (en == 1'b1) + begin + redist18_yAddr_uid51_fpDivTest_b_7_cmpReg_q <= redist18_yAddr_uid51_fpDivTest_b_7_cmp_q; + end + end + + // redist18_yAddr_uid51_fpDivTest_b_7_sticky_ena(REG,279) + always @ (posedge clk) + begin + if (areset) + begin + redist18_yAddr_uid51_fpDivTest_b_7_sticky_ena_q <= 1'b0; + end + else if (redist18_yAddr_uid51_fpDivTest_b_7_nor_q == 1'b1) + begin + redist18_yAddr_uid51_fpDivTest_b_7_sticky_ena_q <= redist18_yAddr_uid51_fpDivTest_b_7_cmpReg_q; + end + end + + // redist18_yAddr_uid51_fpDivTest_b_7_enaAnd(LOGICAL,280) + assign redist18_yAddr_uid51_fpDivTest_b_7_enaAnd_q = redist18_yAddr_uid51_fpDivTest_b_7_sticky_ena_q & en; + + // redist18_yAddr_uid51_fpDivTest_b_7_rdcnt(COUNTER,271) + // low=0, high=4, step=1, init=0 + always @ (posedge clk) + begin + if (areset) + begin + redist18_yAddr_uid51_fpDivTest_b_7_rdcnt_i <= 3'd0; + redist18_yAddr_uid51_fpDivTest_b_7_rdcnt_eq <= 1'b0; + end + else if (en == 1'b1) + begin + if (redist18_yAddr_uid51_fpDivTest_b_7_rdcnt_i == 3'd3) + begin + redist18_yAddr_uid51_fpDivTest_b_7_rdcnt_eq <= 1'b1; + end + else + begin + redist18_yAddr_uid51_fpDivTest_b_7_rdcnt_eq <= 1'b0; + end + if (redist18_yAddr_uid51_fpDivTest_b_7_rdcnt_eq == 1'b1) + begin + redist18_yAddr_uid51_fpDivTest_b_7_rdcnt_i <= $unsigned(redist18_yAddr_uid51_fpDivTest_b_7_rdcnt_i) + $unsigned(3'd4); + end + else + begin + redist18_yAddr_uid51_fpDivTest_b_7_rdcnt_i <= $unsigned(redist18_yAddr_uid51_fpDivTest_b_7_rdcnt_i) + $unsigned(3'd1); + end + end + end + assign redist18_yAddr_uid51_fpDivTest_b_7_rdcnt_q = redist18_yAddr_uid51_fpDivTest_b_7_rdcnt_i[2:0]; + + // redist18_yAddr_uid51_fpDivTest_b_7_rdmux(MUX,272) + assign redist18_yAddr_uid51_fpDivTest_b_7_rdmux_s = en; + always @(redist18_yAddr_uid51_fpDivTest_b_7_rdmux_s or redist18_yAddr_uid51_fpDivTest_b_7_wraddr_q or redist18_yAddr_uid51_fpDivTest_b_7_rdcnt_q) + begin + unique case (redist18_yAddr_uid51_fpDivTest_b_7_rdmux_s) + 1'b0 : redist18_yAddr_uid51_fpDivTest_b_7_rdmux_q = redist18_yAddr_uid51_fpDivTest_b_7_wraddr_q; + 1'b1 : redist18_yAddr_uid51_fpDivTest_b_7_rdmux_q = redist18_yAddr_uid51_fpDivTest_b_7_rdcnt_q; + default : redist18_yAddr_uid51_fpDivTest_b_7_rdmux_q = 3'b0; + endcase + end + + // redist18_yAddr_uid51_fpDivTest_b_7_wraddr(REG,273) + always @ (posedge clk) + begin + if (areset) + begin + redist18_yAddr_uid51_fpDivTest_b_7_wraddr_q <= 3'b100; + end + else + begin + redist18_yAddr_uid51_fpDivTest_b_7_wraddr_q <= redist18_yAddr_uid51_fpDivTest_b_7_rdmux_q; + end + end + + // redist18_yAddr_uid51_fpDivTest_b_7_mem(DUALMEM,270) + assign redist18_yAddr_uid51_fpDivTest_b_7_mem_ia = yAddr_uid51_fpDivTest_b; + assign redist18_yAddr_uid51_fpDivTest_b_7_mem_aa = redist18_yAddr_uid51_fpDivTest_b_7_wraddr_q; + assign redist18_yAddr_uid51_fpDivTest_b_7_mem_ab = redist18_yAddr_uid51_fpDivTest_b_7_rdmux_q; + assign redist18_yAddr_uid51_fpDivTest_b_7_mem_reset0 = areset; + altera_syncram #( + .ram_block_type("MLAB"), + .operation_mode("DUAL_PORT"), + .width_a(9), + .widthad_a(3), + .numwords_a(5), + .width_b(9), + .widthad_b(3), + .numwords_b(5), + .lpm_type("altera_syncram"), + .width_byteena_a(1), + .address_reg_b("CLOCK0"), + .indata_reg_b("CLOCK0"), + .rdcontrol_reg_b("CLOCK0"), + .byteena_reg_b("CLOCK0"), + .outdata_reg_b("CLOCK1"), + .outdata_sclr_b("SCLEAR"), + .clock_enable_input_a("NORMAL"), + .clock_enable_input_b("NORMAL"), + .clock_enable_output_b("NORMAL"), + .read_during_write_mode_mixed_ports("DONT_CARE"), + .power_up_uninitialized("TRUE"), + .intended_device_family("Stratix 10") + ) redist18_yAddr_uid51_fpDivTest_b_7_mem_dmem ( + .clocken1(redist18_yAddr_uid51_fpDivTest_b_7_mem_enaOr_rst), + .clocken0(VCC_q[0]), + .clock0(clk), + .sclr(redist18_yAddr_uid51_fpDivTest_b_7_mem_reset0), + .clock1(clk), + .address_a(redist18_yAddr_uid51_fpDivTest_b_7_mem_aa), + .data_a(redist18_yAddr_uid51_fpDivTest_b_7_mem_ia), + .wren_a(en[0]), + .address_b(redist18_yAddr_uid51_fpDivTest_b_7_mem_ab), + .q_b(redist18_yAddr_uid51_fpDivTest_b_7_mem_iq), + .wren_b(), + .rden_a(), + .rden_b(), + .data_b(), + .clocken2(), + .clocken3(), + .aclr0(), + .aclr1(), + .addressstall_a(), + .addressstall_b(), + .byteena_a(), + .byteena_b(), + .eccencbypass(), + .eccencparity(), + .address2_a(), + .address2_b(), + .q_a(), + .eccstatus() + ); + assign redist18_yAddr_uid51_fpDivTest_b_7_mem_q = redist18_yAddr_uid51_fpDivTest_b_7_mem_iq[8:0]; + assign redist18_yAddr_uid51_fpDivTest_b_7_mem_enaOr_rst = redist18_yAddr_uid51_fpDivTest_b_7_enaAnd_q[0] | redist18_yAddr_uid51_fpDivTest_b_7_mem_reset0; + + // redist18_yAddr_uid51_fpDivTest_b_7_outputreg0(DELAY,269) + always @ (posedge clk) + begin + if (areset) + begin + redist18_yAddr_uid51_fpDivTest_b_7_outputreg0_q <= '0; + end + else if (en == 1'b1) + begin + redist18_yAddr_uid51_fpDivTest_b_7_outputreg0_q <= redist18_yAddr_uid51_fpDivTest_b_7_mem_q; + end + end + + // memoryC1_uid149_invTables_lutmem(DUALMEM,180)@7 + 2 + // in j@20000000 + assign memoryC1_uid149_invTables_lutmem_aa = redist18_yAddr_uid51_fpDivTest_b_7_outputreg0_q; + assign memoryC1_uid149_invTables_lutmem_reset0 = areset; + altera_syncram #( + .ram_block_type("M20K"), + .operation_mode("ROM"), + .width_a(22), + .widthad_a(9), + .numwords_a(512), + .lpm_type("altera_syncram"), + .width_byteena_a(1), + .outdata_reg_a("CLOCK0"), + .outdata_sclr_a("SCLEAR"), + .clock_enable_input_a("NORMAL"), + .power_up_uninitialized("FALSE"), + .init_file("acl_fdiv_memoryC1_uid149_invTables_lutmem.hex"), + .init_file_layout("PORT_A"), + .intended_device_family("Stratix 10") + ) memoryC1_uid149_invTables_lutmem_dmem ( + .clocken0(en[0]), + .sclr(memoryC1_uid149_invTables_lutmem_reset0), + .clock0(clk), + .address_a(memoryC1_uid149_invTables_lutmem_aa), + .q_a(memoryC1_uid149_invTables_lutmem_ir), + .wren_a(), + .wren_b(), + .rden_a(), + .rden_b(), + .data_a(), + .data_b(), + .address_b(), + .clock1(), + .clocken1(), + .clocken2(), + .clocken3(), + .aclr0(), + .aclr1(), + .addressstall_a(), + .addressstall_b(), + .byteena_a(), + .byteena_b(), + .eccencbypass(), + .eccencparity(), + .address2_a(), + .address2_b(), + .q_b(), + .eccstatus() + ); + assign memoryC1_uid149_invTables_lutmem_r = memoryC1_uid149_invTables_lutmem_ir[21:0]; + assign memoryC1_uid149_invTables_lutmem_enaOr_rst = en[0] | memoryC1_uid149_invTables_lutmem_reset0; + + // s1sumAHighB_uid162_invPolyEval(ADD,161)@9 + 1 + assign s1sumAHighB_uid162_invPolyEval_a = {{1{memoryC1_uid149_invTables_lutmem_r[21]}}, memoryC1_uid149_invTables_lutmem_r}; + assign s1sumAHighB_uid162_invPolyEval_b = {{10{highBBits_uid161_invPolyEval_b[12]}}, highBBits_uid161_invPolyEval_b}; + always @ (posedge clk) + begin + if (areset) + begin + s1sumAHighB_uid162_invPolyEval_o <= 23'b0; + end + else if (en == 1'b1) + begin + s1sumAHighB_uid162_invPolyEval_o <= $signed(s1sumAHighB_uid162_invPolyEval_a) + $signed(s1sumAHighB_uid162_invPolyEval_b); + end + end + assign s1sumAHighB_uid162_invPolyEval_q = s1sumAHighB_uid162_invPolyEval_o[22:0]; + + // lowRangeB_uid160_invPolyEval(BITSELECT,159)@9 + assign lowRangeB_uid160_invPolyEval_in = osig_uid175_pT1_uid159_invPolyEval_b[0:0]; + assign lowRangeB_uid160_invPolyEval_b = lowRangeB_uid160_invPolyEval_in[0:0]; + + // redist1_lowRangeB_uid160_invPolyEval_b_1(DELAY,187) + always @ (posedge clk) + begin + if (areset) + begin + redist1_lowRangeB_uid160_invPolyEval_b_1_q <= '0; + end + else if (en == 1'b1) + begin + redist1_lowRangeB_uid160_invPolyEval_b_1_q <= lowRangeB_uid160_invPolyEval_b; + end + end + + // s1_uid163_invPolyEval(BITJOIN,162)@10 + assign s1_uid163_invPolyEval_q = {s1sumAHighB_uid162_invPolyEval_q, redist1_lowRangeB_uid160_invPolyEval_b_1_q}; + + // redist17_yPE_uid52_fpDivTest_b_10_notEnable(LOGICAL,265) + assign redist17_yPE_uid52_fpDivTest_b_10_notEnable_q = ~ (en); + + // redist17_yPE_uid52_fpDivTest_b_10_nor(LOGICAL,266) + assign redist17_yPE_uid52_fpDivTest_b_10_nor_q = ~ (redist17_yPE_uid52_fpDivTest_b_10_notEnable_q | redist17_yPE_uid52_fpDivTest_b_10_sticky_ena_q); + + // redist17_yPE_uid52_fpDivTest_b_10_mem_last(CONSTANT,262) + assign redist17_yPE_uid52_fpDivTest_b_10_mem_last_q = 3'b011; + + // redist17_yPE_uid52_fpDivTest_b_10_cmp(LOGICAL,263) + assign redist17_yPE_uid52_fpDivTest_b_10_cmp_q = redist17_yPE_uid52_fpDivTest_b_10_mem_last_q == redist17_yPE_uid52_fpDivTest_b_10_rdmux_q ? 1'b1 : 1'b0; + + // redist17_yPE_uid52_fpDivTest_b_10_cmpReg(REG,264) + always @ (posedge clk) + begin + if (areset) + begin + redist17_yPE_uid52_fpDivTest_b_10_cmpReg_q <= 1'b0; + end + else if (en == 1'b1) + begin + redist17_yPE_uid52_fpDivTest_b_10_cmpReg_q <= redist17_yPE_uid52_fpDivTest_b_10_cmp_q; + end + end + + // redist17_yPE_uid52_fpDivTest_b_10_sticky_ena(REG,267) + always @ (posedge clk) + begin + if (areset) + begin + redist17_yPE_uid52_fpDivTest_b_10_sticky_ena_q <= 1'b0; + end + else if (redist17_yPE_uid52_fpDivTest_b_10_nor_q == 1'b1) + begin + redist17_yPE_uid52_fpDivTest_b_10_sticky_ena_q <= redist17_yPE_uid52_fpDivTest_b_10_cmpReg_q; + end + end + + // redist17_yPE_uid52_fpDivTest_b_10_enaAnd(LOGICAL,268) + assign redist17_yPE_uid52_fpDivTest_b_10_enaAnd_q = redist17_yPE_uid52_fpDivTest_b_10_sticky_ena_q & en; + + // redist17_yPE_uid52_fpDivTest_b_10_rdcnt(COUNTER,259) + // low=0, high=4, step=1, init=0 + always @ (posedge clk) + begin + if (areset) + begin + redist17_yPE_uid52_fpDivTest_b_10_rdcnt_i <= 3'd0; + redist17_yPE_uid52_fpDivTest_b_10_rdcnt_eq <= 1'b0; + end + else if (en == 1'b1) + begin + if (redist17_yPE_uid52_fpDivTest_b_10_rdcnt_i == 3'd3) + begin + redist17_yPE_uid52_fpDivTest_b_10_rdcnt_eq <= 1'b1; + end + else + begin + redist17_yPE_uid52_fpDivTest_b_10_rdcnt_eq <= 1'b0; + end + if (redist17_yPE_uid52_fpDivTest_b_10_rdcnt_eq == 1'b1) + begin + redist17_yPE_uid52_fpDivTest_b_10_rdcnt_i <= $unsigned(redist17_yPE_uid52_fpDivTest_b_10_rdcnt_i) + $unsigned(3'd4); + end + else + begin + redist17_yPE_uid52_fpDivTest_b_10_rdcnt_i <= $unsigned(redist17_yPE_uid52_fpDivTest_b_10_rdcnt_i) + $unsigned(3'd1); + end + end + end + assign redist17_yPE_uid52_fpDivTest_b_10_rdcnt_q = redist17_yPE_uid52_fpDivTest_b_10_rdcnt_i[2:0]; + + // redist17_yPE_uid52_fpDivTest_b_10_rdmux(MUX,260) + assign redist17_yPE_uid52_fpDivTest_b_10_rdmux_s = en; + always @(redist17_yPE_uid52_fpDivTest_b_10_rdmux_s or redist17_yPE_uid52_fpDivTest_b_10_wraddr_q or redist17_yPE_uid52_fpDivTest_b_10_rdcnt_q) + begin + unique case (redist17_yPE_uid52_fpDivTest_b_10_rdmux_s) + 1'b0 : redist17_yPE_uid52_fpDivTest_b_10_rdmux_q = redist17_yPE_uid52_fpDivTest_b_10_wraddr_q; + 1'b1 : redist17_yPE_uid52_fpDivTest_b_10_rdmux_q = redist17_yPE_uid52_fpDivTest_b_10_rdcnt_q; + default : redist17_yPE_uid52_fpDivTest_b_10_rdmux_q = 3'b0; + endcase + end + + // redist17_yPE_uid52_fpDivTest_b_10_wraddr(REG,261) + always @ (posedge clk) + begin + if (areset) + begin + redist17_yPE_uid52_fpDivTest_b_10_wraddr_q <= 3'b100; + end + else + begin + redist17_yPE_uid52_fpDivTest_b_10_wraddr_q <= redist17_yPE_uid52_fpDivTest_b_10_rdmux_q; + end + end + + // redist17_yPE_uid52_fpDivTest_b_10_mem(DUALMEM,258) + assign redist17_yPE_uid52_fpDivTest_b_10_mem_ia = redist16_yPE_uid52_fpDivTest_b_3_q; + assign redist17_yPE_uid52_fpDivTest_b_10_mem_aa = redist17_yPE_uid52_fpDivTest_b_10_wraddr_q; + assign redist17_yPE_uid52_fpDivTest_b_10_mem_ab = redist17_yPE_uid52_fpDivTest_b_10_rdmux_q; + assign redist17_yPE_uid52_fpDivTest_b_10_mem_reset0 = areset; + altera_syncram #( + .ram_block_type("MLAB"), + .operation_mode("DUAL_PORT"), + .width_a(14), + .widthad_a(3), + .numwords_a(5), + .width_b(14), + .widthad_b(3), + .numwords_b(5), + .lpm_type("altera_syncram"), + .width_byteena_a(1), + .address_reg_b("CLOCK0"), + .indata_reg_b("CLOCK0"), + .rdcontrol_reg_b("CLOCK0"), + .byteena_reg_b("CLOCK0"), + .outdata_reg_b("CLOCK1"), + .outdata_sclr_b("SCLEAR"), + .clock_enable_input_a("NORMAL"), + .clock_enable_input_b("NORMAL"), + .clock_enable_output_b("NORMAL"), + .read_during_write_mode_mixed_ports("DONT_CARE"), + .power_up_uninitialized("TRUE"), + .intended_device_family("Stratix 10") + ) redist17_yPE_uid52_fpDivTest_b_10_mem_dmem ( + .clocken1(redist17_yPE_uid52_fpDivTest_b_10_mem_enaOr_rst), + .clocken0(VCC_q[0]), + .clock0(clk), + .sclr(redist17_yPE_uid52_fpDivTest_b_10_mem_reset0), + .clock1(clk), + .address_a(redist17_yPE_uid52_fpDivTest_b_10_mem_aa), + .data_a(redist17_yPE_uid52_fpDivTest_b_10_mem_ia), + .wren_a(en[0]), + .address_b(redist17_yPE_uid52_fpDivTest_b_10_mem_ab), + .q_b(redist17_yPE_uid52_fpDivTest_b_10_mem_iq), + .wren_b(), + .rden_a(), + .rden_b(), + .data_b(), + .clocken2(), + .clocken3(), + .aclr0(), + .aclr1(), + .addressstall_a(), + .addressstall_b(), + .byteena_a(), + .byteena_b(), + .eccencbypass(), + .eccencparity(), + .address2_a(), + .address2_b(), + .q_a(), + .eccstatus() + ); + assign redist17_yPE_uid52_fpDivTest_b_10_mem_q = redist17_yPE_uid52_fpDivTest_b_10_mem_iq[13:0]; + assign redist17_yPE_uid52_fpDivTest_b_10_mem_enaOr_rst = redist17_yPE_uid52_fpDivTest_b_10_enaAnd_q[0] | redist17_yPE_uid52_fpDivTest_b_10_mem_reset0; + + // redist17_yPE_uid52_fpDivTest_b_10_outputreg0(DELAY,257) + always @ (posedge clk) + begin + if (areset) + begin + redist17_yPE_uid52_fpDivTest_b_10_outputreg0_q <= '0; + end + else if (en == 1'b1) + begin + redist17_yPE_uid52_fpDivTest_b_10_outputreg0_q <= redist17_yPE_uid52_fpDivTest_b_10_mem_q; + end + end + + // prodXY_uid177_pT2_uid165_invPolyEval_cma(CHAINMULTADD,185)@10 + 5 + // out q@16 + assign prodXY_uid177_pT2_uid165_invPolyEval_cma_reset = areset; + assign prodXY_uid177_pT2_uid165_invPolyEval_cma_ena0 = en[0] | prodXY_uid177_pT2_uid165_invPolyEval_cma_reset; + assign prodXY_uid177_pT2_uid165_invPolyEval_cma_ena1 = prodXY_uid177_pT2_uid165_invPolyEval_cma_ena0; + assign prodXY_uid177_pT2_uid165_invPolyEval_cma_ena2 = prodXY_uid177_pT2_uid165_invPolyEval_cma_ena0; + always @ (posedge clk) + begin + if (0) + begin + end + else + begin + if (en == 1'b1) + begin + prodXY_uid177_pT2_uid165_invPolyEval_cma_ah[0] <= redist17_yPE_uid52_fpDivTest_b_10_outputreg0_q; + prodXY_uid177_pT2_uid165_invPolyEval_cma_ch[0] <= s1_uid163_invPolyEval_q; + end + end + end + + assign prodXY_uid177_pT2_uid165_invPolyEval_cma_a0 = prodXY_uid177_pT2_uid165_invPolyEval_cma_ah[0]; + assign prodXY_uid177_pT2_uid165_invPolyEval_cma_c0 = prodXY_uid177_pT2_uid165_invPolyEval_cma_ch[0]; + fourteennm_mac #( + .operation_mode("m27x27"), + .clear_type("sclr"), + .use_chainadder("false"), + .ay_scan_in_clock("0"), + .ay_scan_in_width(14), + .ax_clock("0"), + .ax_width(24), + .signed_may("false"), + .signed_max("true"), + .input_pipeline_clock("2"), + .second_pipeline_clock("2"), + .output_clock("1"), + .result_a_width(38) + ) prodXY_uid177_pT2_uid165_invPolyEval_cma_DSP0 ( + .clk({clk,clk,clk}), + .ena({ prodXY_uid177_pT2_uid165_invPolyEval_cma_ena2, prodXY_uid177_pT2_uid165_invPolyEval_cma_ena1, prodXY_uid177_pT2_uid165_invPolyEval_cma_ena0 }), + .clr({ prodXY_uid177_pT2_uid165_invPolyEval_cma_reset, prodXY_uid177_pT2_uid165_invPolyEval_cma_reset }), + .ay(prodXY_uid177_pT2_uid165_invPolyEval_cma_a0), + .ax(prodXY_uid177_pT2_uid165_invPolyEval_cma_c0), + .resulta(prodXY_uid177_pT2_uid165_invPolyEval_cma_s0), + .accumulate(), + .loadconst(), + .negate(), + .sub(), + .az(), + .coefsela(), + .bx(), + .by(), + .bz(), + .coefselb(), + .scanin(), + .scanout(), + .chainin(), + .chainout(), + .resultb(), + .dfxlfsrena(), + .dfxmisrena(), + .dftout() + ); + dspba_delay_ver #( .width(38), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1) ) + prodXY_uid177_pT2_uid165_invPolyEval_cma_delay ( .xin(prodXY_uid177_pT2_uid165_invPolyEval_cma_s0), .xout(prodXY_uid177_pT2_uid165_invPolyEval_cma_qq), .ena(en[0]), .clk(clk), .aclr(areset) ); + assign prodXY_uid177_pT2_uid165_invPolyEval_cma_q = prodXY_uid177_pT2_uid165_invPolyEval_cma_qq[37:0]; + + // osig_uid178_pT2_uid165_invPolyEval(BITSELECT,177)@16 + assign osig_uid178_pT2_uid165_invPolyEval_b = prodXY_uid177_pT2_uid165_invPolyEval_cma_q[37:13]; + + // highBBits_uid167_invPolyEval(BITSELECT,166)@16 + assign highBBits_uid167_invPolyEval_b = osig_uid178_pT2_uid165_invPolyEval_b[24:2]; + + // redist19_yAddr_uid51_fpDivTest_b_14_notEnable(LOGICAL,289) + assign redist19_yAddr_uid51_fpDivTest_b_14_notEnable_q = ~ (en); + + // redist19_yAddr_uid51_fpDivTest_b_14_nor(LOGICAL,290) + assign redist19_yAddr_uid51_fpDivTest_b_14_nor_q = ~ (redist19_yAddr_uid51_fpDivTest_b_14_notEnable_q | redist19_yAddr_uid51_fpDivTest_b_14_sticky_ena_q); + + // redist19_yAddr_uid51_fpDivTest_b_14_mem_last(CONSTANT,286) + assign redist19_yAddr_uid51_fpDivTest_b_14_mem_last_q = 3'b011; + + // redist19_yAddr_uid51_fpDivTest_b_14_cmp(LOGICAL,287) + assign redist19_yAddr_uid51_fpDivTest_b_14_cmp_q = redist19_yAddr_uid51_fpDivTest_b_14_mem_last_q == redist19_yAddr_uid51_fpDivTest_b_14_rdmux_q ? 1'b1 : 1'b0; + + // redist19_yAddr_uid51_fpDivTest_b_14_cmpReg(REG,288) + always @ (posedge clk) + begin + if (areset) + begin + redist19_yAddr_uid51_fpDivTest_b_14_cmpReg_q <= 1'b0; + end + else if (en == 1'b1) + begin + redist19_yAddr_uid51_fpDivTest_b_14_cmpReg_q <= redist19_yAddr_uid51_fpDivTest_b_14_cmp_q; + end + end + + // redist19_yAddr_uid51_fpDivTest_b_14_sticky_ena(REG,291) + always @ (posedge clk) + begin + if (areset) + begin + redist19_yAddr_uid51_fpDivTest_b_14_sticky_ena_q <= 1'b0; + end + else if (redist19_yAddr_uid51_fpDivTest_b_14_nor_q == 1'b1) + begin + redist19_yAddr_uid51_fpDivTest_b_14_sticky_ena_q <= redist19_yAddr_uid51_fpDivTest_b_14_cmpReg_q; + end + end + + // redist19_yAddr_uid51_fpDivTest_b_14_enaAnd(LOGICAL,292) + assign redist19_yAddr_uid51_fpDivTest_b_14_enaAnd_q = redist19_yAddr_uid51_fpDivTest_b_14_sticky_ena_q & en; + + // redist19_yAddr_uid51_fpDivTest_b_14_rdcnt(COUNTER,283) + // low=0, high=4, step=1, init=0 + always @ (posedge clk) + begin + if (areset) + begin + redist19_yAddr_uid51_fpDivTest_b_14_rdcnt_i <= 3'd0; + redist19_yAddr_uid51_fpDivTest_b_14_rdcnt_eq <= 1'b0; + end + else if (en == 1'b1) + begin + if (redist19_yAddr_uid51_fpDivTest_b_14_rdcnt_i == 3'd3) + begin + redist19_yAddr_uid51_fpDivTest_b_14_rdcnt_eq <= 1'b1; + end + else + begin + redist19_yAddr_uid51_fpDivTest_b_14_rdcnt_eq <= 1'b0; + end + if (redist19_yAddr_uid51_fpDivTest_b_14_rdcnt_eq == 1'b1) + begin + redist19_yAddr_uid51_fpDivTest_b_14_rdcnt_i <= $unsigned(redist19_yAddr_uid51_fpDivTest_b_14_rdcnt_i) + $unsigned(3'd4); + end + else + begin + redist19_yAddr_uid51_fpDivTest_b_14_rdcnt_i <= $unsigned(redist19_yAddr_uid51_fpDivTest_b_14_rdcnt_i) + $unsigned(3'd1); + end + end + end + assign redist19_yAddr_uid51_fpDivTest_b_14_rdcnt_q = redist19_yAddr_uid51_fpDivTest_b_14_rdcnt_i[2:0]; + + // redist19_yAddr_uid51_fpDivTest_b_14_rdmux(MUX,284) + assign redist19_yAddr_uid51_fpDivTest_b_14_rdmux_s = en; + always @(redist19_yAddr_uid51_fpDivTest_b_14_rdmux_s or redist19_yAddr_uid51_fpDivTest_b_14_wraddr_q or redist19_yAddr_uid51_fpDivTest_b_14_rdcnt_q) + begin + unique case (redist19_yAddr_uid51_fpDivTest_b_14_rdmux_s) + 1'b0 : redist19_yAddr_uid51_fpDivTest_b_14_rdmux_q = redist19_yAddr_uid51_fpDivTest_b_14_wraddr_q; + 1'b1 : redist19_yAddr_uid51_fpDivTest_b_14_rdmux_q = redist19_yAddr_uid51_fpDivTest_b_14_rdcnt_q; + default : redist19_yAddr_uid51_fpDivTest_b_14_rdmux_q = 3'b0; + endcase + end + + // redist19_yAddr_uid51_fpDivTest_b_14_wraddr(REG,285) + always @ (posedge clk) + begin + if (areset) + begin + redist19_yAddr_uid51_fpDivTest_b_14_wraddr_q <= 3'b100; + end + else + begin + redist19_yAddr_uid51_fpDivTest_b_14_wraddr_q <= redist19_yAddr_uid51_fpDivTest_b_14_rdmux_q; + end + end + + // redist19_yAddr_uid51_fpDivTest_b_14_mem(DUALMEM,282) + assign redist19_yAddr_uid51_fpDivTest_b_14_mem_ia = redist18_yAddr_uid51_fpDivTest_b_7_outputreg0_q; + assign redist19_yAddr_uid51_fpDivTest_b_14_mem_aa = redist19_yAddr_uid51_fpDivTest_b_14_wraddr_q; + assign redist19_yAddr_uid51_fpDivTest_b_14_mem_ab = redist19_yAddr_uid51_fpDivTest_b_14_rdmux_q; + assign redist19_yAddr_uid51_fpDivTest_b_14_mem_reset0 = areset; + altera_syncram #( + .ram_block_type("MLAB"), + .operation_mode("DUAL_PORT"), + .width_a(9), + .widthad_a(3), + .numwords_a(5), + .width_b(9), + .widthad_b(3), + .numwords_b(5), + .lpm_type("altera_syncram"), + .width_byteena_a(1), + .address_reg_b("CLOCK0"), + .indata_reg_b("CLOCK0"), + .rdcontrol_reg_b("CLOCK0"), + .byteena_reg_b("CLOCK0"), + .outdata_reg_b("CLOCK1"), + .outdata_sclr_b("SCLEAR"), + .clock_enable_input_a("NORMAL"), + .clock_enable_input_b("NORMAL"), + .clock_enable_output_b("NORMAL"), + .read_during_write_mode_mixed_ports("DONT_CARE"), + .power_up_uninitialized("TRUE"), + .intended_device_family("Stratix 10") + ) redist19_yAddr_uid51_fpDivTest_b_14_mem_dmem ( + .clocken1(redist19_yAddr_uid51_fpDivTest_b_14_mem_enaOr_rst), + .clocken0(VCC_q[0]), + .clock0(clk), + .sclr(redist19_yAddr_uid51_fpDivTest_b_14_mem_reset0), + .clock1(clk), + .address_a(redist19_yAddr_uid51_fpDivTest_b_14_mem_aa), + .data_a(redist19_yAddr_uid51_fpDivTest_b_14_mem_ia), + .wren_a(en[0]), + .address_b(redist19_yAddr_uid51_fpDivTest_b_14_mem_ab), + .q_b(redist19_yAddr_uid51_fpDivTest_b_14_mem_iq), + .wren_b(), + .rden_a(), + .rden_b(), + .data_b(), + .clocken2(), + .clocken3(), + .aclr0(), + .aclr1(), + .addressstall_a(), + .addressstall_b(), + .byteena_a(), + .byteena_b(), + .eccencbypass(), + .eccencparity(), + .address2_a(), + .address2_b(), + .q_a(), + .eccstatus() + ); + assign redist19_yAddr_uid51_fpDivTest_b_14_mem_q = redist19_yAddr_uid51_fpDivTest_b_14_mem_iq[8:0]; + assign redist19_yAddr_uid51_fpDivTest_b_14_mem_enaOr_rst = redist19_yAddr_uid51_fpDivTest_b_14_enaAnd_q[0] | redist19_yAddr_uid51_fpDivTest_b_14_mem_reset0; + + // redist19_yAddr_uid51_fpDivTest_b_14_outputreg0(DELAY,281) + always @ (posedge clk) + begin + if (areset) + begin + redist19_yAddr_uid51_fpDivTest_b_14_outputreg0_q <= '0; + end + else if (en == 1'b1) + begin + redist19_yAddr_uid51_fpDivTest_b_14_outputreg0_q <= redist19_yAddr_uid51_fpDivTest_b_14_mem_q; + end + end + + // memoryC0_uid146_invTables_lutmem(DUALMEM,179)@14 + 2 + // in j@20000000 + assign memoryC0_uid146_invTables_lutmem_aa = redist19_yAddr_uid51_fpDivTest_b_14_outputreg0_q; + assign memoryC0_uid146_invTables_lutmem_reset0 = areset; + altera_syncram #( + .ram_block_type("M20K"), + .operation_mode("ROM"), + .width_a(32), + .widthad_a(9), + .numwords_a(512), + .lpm_type("altera_syncram"), + .width_byteena_a(1), + .outdata_reg_a("CLOCK0"), + .outdata_sclr_a("SCLEAR"), + .clock_enable_input_a("NORMAL"), + .power_up_uninitialized("FALSE"), + .init_file("acl_fdiv_memoryC0_uid146_invTables_lutmem.hex"), + .init_file_layout("PORT_A"), + .intended_device_family("Stratix 10") + ) memoryC0_uid146_invTables_lutmem_dmem ( + .clocken0(en[0]), + .sclr(memoryC0_uid146_invTables_lutmem_reset0), + .clock0(clk), + .address_a(memoryC0_uid146_invTables_lutmem_aa), + .q_a(memoryC0_uid146_invTables_lutmem_ir), + .wren_a(), + .wren_b(), + .rden_a(), + .rden_b(), + .data_a(), + .data_b(), + .address_b(), + .clock1(), + .clocken1(), + .clocken2(), + .clocken3(), + .aclr0(), + .aclr1(), + .addressstall_a(), + .addressstall_b(), + .byteena_a(), + .byteena_b(), + .eccencbypass(), + .eccencparity(), + .address2_a(), + .address2_b(), + .q_b(), + .eccstatus() + ); + assign memoryC0_uid146_invTables_lutmem_r = memoryC0_uid146_invTables_lutmem_ir[31:0]; + assign memoryC0_uid146_invTables_lutmem_enaOr_rst = en[0] | memoryC0_uid146_invTables_lutmem_reset0; + + // s2sumAHighB_uid168_invPolyEval(ADD,167)@16 + assign s2sumAHighB_uid168_invPolyEval_a = {{1{memoryC0_uid146_invTables_lutmem_r[31]}}, memoryC0_uid146_invTables_lutmem_r}; + assign s2sumAHighB_uid168_invPolyEval_b = {{10{highBBits_uid167_invPolyEval_b[22]}}, highBBits_uid167_invPolyEval_b}; + assign s2sumAHighB_uid168_invPolyEval_o = $signed(s2sumAHighB_uid168_invPolyEval_a) + $signed(s2sumAHighB_uid168_invPolyEval_b); + assign s2sumAHighB_uid168_invPolyEval_q = s2sumAHighB_uid168_invPolyEval_o[32:0]; + + // lowRangeB_uid166_invPolyEval(BITSELECT,165)@16 + assign lowRangeB_uid166_invPolyEval_in = osig_uid178_pT2_uid165_invPolyEval_b[1:0]; + assign lowRangeB_uid166_invPolyEval_b = lowRangeB_uid166_invPolyEval_in[1:0]; + + // s2_uid169_invPolyEval(BITJOIN,168)@16 + assign s2_uid169_invPolyEval_q = {s2sumAHighB_uid168_invPolyEval_q, lowRangeB_uid166_invPolyEval_b}; + + // invY_uid54_fpDivTest(BITSELECT,53)@16 + assign invY_uid54_fpDivTest_in = s2_uid169_invPolyEval_q[31:0]; + assign invY_uid54_fpDivTest_b = invY_uid54_fpDivTest_in[31:5]; + + // redist15_invY_uid54_fpDivTest_b_1(DELAY,201) + always @ (posedge clk) + begin + if (areset) + begin + redist15_invY_uid54_fpDivTest_b_1_q <= '0; + end + else if (en == 1'b1) + begin + redist15_invY_uid54_fpDivTest_b_1_q <= invY_uid54_fpDivTest_b; + end + end + + // prodXY_uid171_divValPreNorm_uid59_fpDivTest_cma(CHAINMULTADD,183)@17 + 5 + // out q@23 + assign prodXY_uid171_divValPreNorm_uid59_fpDivTest_cma_reset = areset; + assign prodXY_uid171_divValPreNorm_uid59_fpDivTest_cma_ena0 = en[0] | prodXY_uid171_divValPreNorm_uid59_fpDivTest_cma_reset; + assign prodXY_uid171_divValPreNorm_uid59_fpDivTest_cma_ena1 = prodXY_uid171_divValPreNorm_uid59_fpDivTest_cma_ena0; + assign prodXY_uid171_divValPreNorm_uid59_fpDivTest_cma_ena2 = prodXY_uid171_divValPreNorm_uid59_fpDivTest_cma_ena0; + always @ (posedge clk) + begin + if (0) + begin + end + else + begin + if (en == 1'b1) + begin + prodXY_uid171_divValPreNorm_uid59_fpDivTest_cma_ah[0] <= redist15_invY_uid54_fpDivTest_b_1_q; + prodXY_uid171_divValPreNorm_uid59_fpDivTest_cma_ch[0] <= lOAdded_uid57_fpDivTest_q; + end + end + end + + assign prodXY_uid171_divValPreNorm_uid59_fpDivTest_cma_a0 = prodXY_uid171_divValPreNorm_uid59_fpDivTest_cma_ah[0]; + assign prodXY_uid171_divValPreNorm_uid59_fpDivTest_cma_c0 = prodXY_uid171_divValPreNorm_uid59_fpDivTest_cma_ch[0]; + fourteennm_mac #( + .operation_mode("m27x27"), + .clear_type("sclr"), + .use_chainadder("false"), + .ay_scan_in_clock("0"), + .ay_scan_in_width(27), + .ax_clock("0"), + .ax_width(24), + .signed_may("false"), + .signed_max("false"), + .input_pipeline_clock("2"), + .second_pipeline_clock("2"), + .output_clock("1"), + .result_a_width(51) + ) prodXY_uid171_divValPreNorm_uid59_fpDivTest_cma_DSP0 ( + .clk({clk,clk,clk}), + .ena({ prodXY_uid171_divValPreNorm_uid59_fpDivTest_cma_ena2, prodXY_uid171_divValPreNorm_uid59_fpDivTest_cma_ena1, prodXY_uid171_divValPreNorm_uid59_fpDivTest_cma_ena0 }), + .clr({ prodXY_uid171_divValPreNorm_uid59_fpDivTest_cma_reset, prodXY_uid171_divValPreNorm_uid59_fpDivTest_cma_reset }), + .ay(prodXY_uid171_divValPreNorm_uid59_fpDivTest_cma_a0), + .ax(prodXY_uid171_divValPreNorm_uid59_fpDivTest_cma_c0), + .resulta(prodXY_uid171_divValPreNorm_uid59_fpDivTest_cma_s0), + .accumulate(), + .loadconst(), + .negate(), + .sub(), + .az(), + .coefsela(), + .bx(), + .by(), + .bz(), + .coefselb(), + .scanin(), + .scanout(), + .chainin(), + .chainout(), + .resultb(), + .dfxlfsrena(), + .dfxmisrena(), + .dftout() + ); + dspba_delay_ver #( .width(51), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1) ) + prodXY_uid171_divValPreNorm_uid59_fpDivTest_cma_delay ( .xin(prodXY_uid171_divValPreNorm_uid59_fpDivTest_cma_s0), .xout(prodXY_uid171_divValPreNorm_uid59_fpDivTest_cma_qq), .ena(en[0]), .clk(clk), .aclr(areset) ); + assign prodXY_uid171_divValPreNorm_uid59_fpDivTest_cma_q = prodXY_uid171_divValPreNorm_uid59_fpDivTest_cma_qq[50:0]; + + // osig_uid172_divValPreNorm_uid59_fpDivTest(BITSELECT,171)@23 + assign osig_uid172_divValPreNorm_uid59_fpDivTest_b = prodXY_uid171_divValPreNorm_uid59_fpDivTest_cma_q[50:23]; + + // updatedY_uid16_fpDivTest(BITJOIN,15)@22 + assign updatedY_uid16_fpDivTest_q = {GND_q, paddingY_uid15_fpDivTest_q}; + + // fracYZero_uid15_fpDivTest(LOGICAL,16)@22 + 1 + assign fracYZero_uid15_fpDivTest_a = {1'b0, redist23_fracY_uid13_fpDivTest_b_22_mem_q}; + assign fracYZero_uid15_fpDivTest_qi = fracYZero_uid15_fpDivTest_a == updatedY_uid16_fpDivTest_q ? 1'b1 : 1'b0; + dspba_delay_ver #( .width(1), .depth(1), .reset_kind("SYNC"), .phase(0), .modulus(1) ) + fracYZero_uid15_fpDivTest_delay ( .xin(fracYZero_uid15_fpDivTest_qi), .xout(fracYZero_uid15_fpDivTest_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // divValPreNormYPow2Exc_uid63_fpDivTest(MUX,62)@23 + assign divValPreNormYPow2Exc_uid63_fpDivTest_s = fracYZero_uid15_fpDivTest_q; + always @(divValPreNormYPow2Exc_uid63_fpDivTest_s or en or osig_uid172_divValPreNorm_uid59_fpDivTest_b or oFracXZ4_uid61_fpDivTest_q) + begin + unique case (divValPreNormYPow2Exc_uid63_fpDivTest_s) + 1'b0 : divValPreNormYPow2Exc_uid63_fpDivTest_q = osig_uid172_divValPreNorm_uid59_fpDivTest_b; + 1'b1 : divValPreNormYPow2Exc_uid63_fpDivTest_q = oFracXZ4_uid61_fpDivTest_q; + default : divValPreNormYPow2Exc_uid63_fpDivTest_q = 28'b0; + endcase + end + + // norm_uid64_fpDivTest(BITSELECT,63)@23 + assign norm_uid64_fpDivTest_b = divValPreNormYPow2Exc_uid63_fpDivTest_q[27:27]; + + // redist11_norm_uid64_fpDivTest_b_1(DELAY,197) + always @ (posedge clk) + begin + if (areset) + begin + redist11_norm_uid64_fpDivTest_b_1_q <= '0; + end + else if (en == 1'b1) + begin + redist11_norm_uid64_fpDivTest_b_1_q <= norm_uid64_fpDivTest_b; + end + end + + // zeroPaddingInAddition_uid74_fpDivTest(CONSTANT,73) + assign zeroPaddingInAddition_uid74_fpDivTest_q = 24'b000000000000000000000000; + + // expFracPostRnd_uid75_fpDivTest(BITJOIN,74)@24 + assign expFracPostRnd_uid75_fpDivTest_q = {redist11_norm_uid64_fpDivTest_b_1_q, zeroPaddingInAddition_uid74_fpDivTest_q, VCC_q}; + + // cstBiasM1_uid6_fpDivTest(CONSTANT,5) + assign cstBiasM1_uid6_fpDivTest_q = 8'b01111110; + + // expXmY_uid47_fpDivTest(SUB,46)@23 + assign expXmY_uid47_fpDivTest_a = {1'b0, redist33_expX_uid9_fpDivTest_b_23_mem_q}; + assign expXmY_uid47_fpDivTest_b = {1'b0, redist26_expY_uid12_fpDivTest_b_23_mem_q}; + assign expXmY_uid47_fpDivTest_o = $unsigned(expXmY_uid47_fpDivTest_a) - $unsigned(expXmY_uid47_fpDivTest_b); + assign expXmY_uid47_fpDivTest_q = expXmY_uid47_fpDivTest_o[8:0]; + + // expR_uid48_fpDivTest(ADD,47)@23 + 1 + assign expR_uid48_fpDivTest_a = {{2{expXmY_uid47_fpDivTest_q[8]}}, expXmY_uid47_fpDivTest_q}; + assign expR_uid48_fpDivTest_b = {3'b000, cstBiasM1_uid6_fpDivTest_q}; + always @ (posedge clk) + begin + if (areset) + begin + expR_uid48_fpDivTest_o <= 11'b0; + end + else if (en == 1'b1) + begin + expR_uid48_fpDivTest_o <= $signed(expR_uid48_fpDivTest_a) + $signed(expR_uid48_fpDivTest_b); + end + end + assign expR_uid48_fpDivTest_q = expR_uid48_fpDivTest_o[9:0]; + + // divValPreNormHigh_uid65_fpDivTest(BITSELECT,64)@23 + assign divValPreNormHigh_uid65_fpDivTest_in = divValPreNormYPow2Exc_uid63_fpDivTest_q[26:0]; + assign divValPreNormHigh_uid65_fpDivTest_b = divValPreNormHigh_uid65_fpDivTest_in[26:2]; + + // divValPreNormLow_uid66_fpDivTest(BITSELECT,65)@23 + assign divValPreNormLow_uid66_fpDivTest_in = divValPreNormYPow2Exc_uid63_fpDivTest_q[25:0]; + assign divValPreNormLow_uid66_fpDivTest_b = divValPreNormLow_uid66_fpDivTest_in[25:1]; + + // normFracRnd_uid67_fpDivTest(MUX,66)@23 + 1 + assign normFracRnd_uid67_fpDivTest_s = norm_uid64_fpDivTest_b; + always @ (posedge clk) + begin + if (areset) + begin + normFracRnd_uid67_fpDivTest_q <= 25'b0; + end + else if (en == 1'b1) + begin + unique case (normFracRnd_uid67_fpDivTest_s) + 1'b0 : normFracRnd_uid67_fpDivTest_q <= divValPreNormLow_uid66_fpDivTest_b; + 1'b1 : normFracRnd_uid67_fpDivTest_q <= divValPreNormHigh_uid65_fpDivTest_b; + default : normFracRnd_uid67_fpDivTest_q <= 25'b0; + endcase + end + end + + // expFracRnd_uid68_fpDivTest(BITJOIN,67)@24 + assign expFracRnd_uid68_fpDivTest_q = {expR_uid48_fpDivTest_q, normFracRnd_uid67_fpDivTest_q}; + + // expFracPostRnd_uid76_fpDivTest(ADD,75)@24 + assign expFracPostRnd_uid76_fpDivTest_a = {{2{expFracRnd_uid68_fpDivTest_q[34]}}, expFracRnd_uid68_fpDivTest_q}; + assign expFracPostRnd_uid76_fpDivTest_b = {11'b00000000000, expFracPostRnd_uid75_fpDivTest_q}; + assign expFracPostRnd_uid76_fpDivTest_o = $signed(expFracPostRnd_uid76_fpDivTest_a) + $signed(expFracPostRnd_uid76_fpDivTest_b); + assign expFracPostRnd_uid76_fpDivTest_q = expFracPostRnd_uid76_fpDivTest_o[35:0]; + + // fracPostRndF_uid79_fpDivTest(BITSELECT,78)@24 + assign fracPostRndF_uid79_fpDivTest_in = expFracPostRnd_uid76_fpDivTest_q[24:0]; + assign fracPostRndF_uid79_fpDivTest_b = fracPostRndF_uid79_fpDivTest_in[24:1]; + + // redist10_fracPostRndF_uid79_fpDivTest_b_1(DELAY,196) + always @ (posedge clk) + begin + if (areset) + begin + redist10_fracPostRndF_uid79_fpDivTest_b_1_q <= '0; + end + else if (en == 1'b1) + begin + redist10_fracPostRndF_uid79_fpDivTest_b_1_q <= fracPostRndF_uid79_fpDivTest_b; + end + end + + // invYO_uid55_fpDivTest(BITSELECT,54)@16 + assign invYO_uid55_fpDivTest_in = s2_uid169_invPolyEval_q[32:0]; + assign invYO_uid55_fpDivTest_b = invYO_uid55_fpDivTest_in[32:32]; + + // redist13_invYO_uid55_fpDivTest_b_9(DELAY,199) + dspba_delay_ver #( .width(1), .depth(9), .reset_kind("SYNC"), .phase(0), .modulus(1) ) + redist13_invYO_uid55_fpDivTest_b_9 ( .xin(invYO_uid55_fpDivTest_b), .xout(redist13_invYO_uid55_fpDivTest_b_9_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // fracPostRndF_uid80_fpDivTest(MUX,79)@25 + assign fracPostRndF_uid80_fpDivTest_s = redist13_invYO_uid55_fpDivTest_b_9_q; + always @(fracPostRndF_uid80_fpDivTest_s or en or redist10_fracPostRndF_uid79_fpDivTest_b_1_q or fracXExt_uid77_fpDivTest_q) + begin + unique case (fracPostRndF_uid80_fpDivTest_s) + 1'b0 : fracPostRndF_uid80_fpDivTest_q = redist10_fracPostRndF_uid79_fpDivTest_b_1_q; + 1'b1 : fracPostRndF_uid80_fpDivTest_q = fracXExt_uid77_fpDivTest_q; + default : fracPostRndF_uid80_fpDivTest_q = 24'b0; + endcase + end + + // fracPostRndFT_uid104_fpDivTest(BITSELECT,103)@25 + assign fracPostRndFT_uid104_fpDivTest_b = fracPostRndF_uid80_fpDivTest_q[23:1]; + + // redist4_fracPostRndFT_uid104_fpDivTest_b_8_wraddr(REG,226) + always @ (posedge clk) + begin + if (areset) + begin + redist4_fracPostRndFT_uid104_fpDivTest_b_8_wraddr_q <= 3'b110; + end + else + begin + redist4_fracPostRndFT_uid104_fpDivTest_b_8_wraddr_q <= redist4_fracPostRndFT_uid104_fpDivTest_b_8_rdmux_q; + end + end + + // redist4_fracPostRndFT_uid104_fpDivTest_b_8_mem(DUALMEM,223) + assign redist4_fracPostRndFT_uid104_fpDivTest_b_8_mem_ia = fracPostRndFT_uid104_fpDivTest_b; + assign redist4_fracPostRndFT_uid104_fpDivTest_b_8_mem_aa = redist4_fracPostRndFT_uid104_fpDivTest_b_8_wraddr_q; + assign redist4_fracPostRndFT_uid104_fpDivTest_b_8_mem_ab = redist4_fracPostRndFT_uid104_fpDivTest_b_8_rdmux_q; + assign redist4_fracPostRndFT_uid104_fpDivTest_b_8_mem_reset0 = areset; + altera_syncram #( + .ram_block_type("MLAB"), + .operation_mode("DUAL_PORT"), + .width_a(23), + .widthad_a(3), + .numwords_a(7), + .width_b(23), + .widthad_b(3), + .numwords_b(7), + .lpm_type("altera_syncram"), + .width_byteena_a(1), + .address_reg_b("CLOCK0"), + .indata_reg_b("CLOCK0"), + .rdcontrol_reg_b("CLOCK0"), + .byteena_reg_b("CLOCK0"), + .outdata_reg_b("CLOCK1"), + .outdata_sclr_b("SCLEAR"), + .clock_enable_input_a("NORMAL"), + .clock_enable_input_b("NORMAL"), + .clock_enable_output_b("NORMAL"), + .read_during_write_mode_mixed_ports("DONT_CARE"), + .power_up_uninitialized("TRUE"), + .intended_device_family("Stratix 10") + ) redist4_fracPostRndFT_uid104_fpDivTest_b_8_mem_dmem ( + .clocken1(redist4_fracPostRndFT_uid104_fpDivTest_b_8_mem_enaOr_rst), + .clocken0(VCC_q[0]), + .clock0(clk), + .sclr(redist4_fracPostRndFT_uid104_fpDivTest_b_8_mem_reset0), + .clock1(clk), + .address_a(redist4_fracPostRndFT_uid104_fpDivTest_b_8_mem_aa), + .data_a(redist4_fracPostRndFT_uid104_fpDivTest_b_8_mem_ia), + .wren_a(en[0]), + .address_b(redist4_fracPostRndFT_uid104_fpDivTest_b_8_mem_ab), + .q_b(redist4_fracPostRndFT_uid104_fpDivTest_b_8_mem_iq), + .wren_b(), + .rden_a(), + .rden_b(), + .data_b(), + .clocken2(), + .clocken3(), + .aclr0(), + .aclr1(), + .addressstall_a(), + .addressstall_b(), + .byteena_a(), + .byteena_b(), + .eccencbypass(), + .eccencparity(), + .address2_a(), + .address2_b(), + .q_a(), + .eccstatus() + ); + assign redist4_fracPostRndFT_uid104_fpDivTest_b_8_mem_q = redist4_fracPostRndFT_uid104_fpDivTest_b_8_mem_iq[22:0]; + assign redist4_fracPostRndFT_uid104_fpDivTest_b_8_mem_enaOr_rst = redist4_fracPostRndFT_uid104_fpDivTest_b_8_enaAnd_q[0] | redist4_fracPostRndFT_uid104_fpDivTest_b_8_mem_reset0; + + // fracRPreExcExt_uid105_fpDivTest(ADD,104)@33 + assign fracRPreExcExt_uid105_fpDivTest_a = {1'b0, redist4_fracPostRndFT_uid104_fpDivTest_b_8_mem_q}; + assign fracRPreExcExt_uid105_fpDivTest_b = {23'b00000000000000000000000, extraUlp_uid103_fpDivTest_q}; + assign fracRPreExcExt_uid105_fpDivTest_o = $unsigned(fracRPreExcExt_uid105_fpDivTest_a) + $unsigned(fracRPreExcExt_uid105_fpDivTest_b); + assign fracRPreExcExt_uid105_fpDivTest_q = fracRPreExcExt_uid105_fpDivTest_o[23:0]; + + // ovfIncRnd_uid109_fpDivTest(BITSELECT,108)@33 + assign ovfIncRnd_uid109_fpDivTest_b = fracRPreExcExt_uid105_fpDivTest_q[23:23]; + + // expFracPostRndInc_uid110_fpDivTest(ADD,109)@33 + assign expFracPostRndInc_uid110_fpDivTest_a = {1'b0, redist9_expPostRndFR_uid81_fpDivTest_b_9_q}; + assign expFracPostRndInc_uid110_fpDivTest_b = {8'b00000000, ovfIncRnd_uid109_fpDivTest_b}; + assign expFracPostRndInc_uid110_fpDivTest_o = $unsigned(expFracPostRndInc_uid110_fpDivTest_a) + $unsigned(expFracPostRndInc_uid110_fpDivTest_b); + assign expFracPostRndInc_uid110_fpDivTest_q = expFracPostRndInc_uid110_fpDivTest_o[8:0]; + + // expFracPostRndR_uid111_fpDivTest(BITSELECT,110)@33 + assign expFracPostRndR_uid111_fpDivTest_in = expFracPostRndInc_uid110_fpDivTest_q[7:0]; + assign expFracPostRndR_uid111_fpDivTest_b = expFracPostRndR_uid111_fpDivTest_in[7:0]; + + // redist8_expPostRndFR_uid81_fpDivTest_b_7_notEnable(LOGICAL,242) + assign redist8_expPostRndFR_uid81_fpDivTest_b_7_notEnable_q = ~ (en); + + // redist8_expPostRndFR_uid81_fpDivTest_b_7_nor(LOGICAL,243) + assign redist8_expPostRndFR_uid81_fpDivTest_b_7_nor_q = ~ (redist8_expPostRndFR_uid81_fpDivTest_b_7_notEnable_q | redist8_expPostRndFR_uid81_fpDivTest_b_7_sticky_ena_q); + + // redist8_expPostRndFR_uid81_fpDivTest_b_7_mem_last(CONSTANT,239) + assign redist8_expPostRndFR_uid81_fpDivTest_b_7_mem_last_q = 3'b011; + + // redist8_expPostRndFR_uid81_fpDivTest_b_7_cmp(LOGICAL,240) + assign redist8_expPostRndFR_uid81_fpDivTest_b_7_cmp_q = redist8_expPostRndFR_uid81_fpDivTest_b_7_mem_last_q == redist8_expPostRndFR_uid81_fpDivTest_b_7_rdmux_q ? 1'b1 : 1'b0; + + // redist8_expPostRndFR_uid81_fpDivTest_b_7_cmpReg(REG,241) + always @ (posedge clk) + begin + if (areset) + begin + redist8_expPostRndFR_uid81_fpDivTest_b_7_cmpReg_q <= 1'b0; + end + else if (en == 1'b1) + begin + redist8_expPostRndFR_uid81_fpDivTest_b_7_cmpReg_q <= redist8_expPostRndFR_uid81_fpDivTest_b_7_cmp_q; + end + end + + // redist8_expPostRndFR_uid81_fpDivTest_b_7_sticky_ena(REG,244) + always @ (posedge clk) + begin + if (areset) + begin + redist8_expPostRndFR_uid81_fpDivTest_b_7_sticky_ena_q <= 1'b0; + end + else if (redist8_expPostRndFR_uid81_fpDivTest_b_7_nor_q == 1'b1) + begin + redist8_expPostRndFR_uid81_fpDivTest_b_7_sticky_ena_q <= redist8_expPostRndFR_uid81_fpDivTest_b_7_cmpReg_q; + end + end + + // redist8_expPostRndFR_uid81_fpDivTest_b_7_enaAnd(LOGICAL,245) + assign redist8_expPostRndFR_uid81_fpDivTest_b_7_enaAnd_q = redist8_expPostRndFR_uid81_fpDivTest_b_7_sticky_ena_q & en; + + // redist8_expPostRndFR_uid81_fpDivTest_b_7_rdcnt(COUNTER,236) + // low=0, high=4, step=1, init=0 + always @ (posedge clk) + begin + if (areset) + begin + redist8_expPostRndFR_uid81_fpDivTest_b_7_rdcnt_i <= 3'd0; + redist8_expPostRndFR_uid81_fpDivTest_b_7_rdcnt_eq <= 1'b0; + end + else if (en == 1'b1) + begin + if (redist8_expPostRndFR_uid81_fpDivTest_b_7_rdcnt_i == 3'd3) + begin + redist8_expPostRndFR_uid81_fpDivTest_b_7_rdcnt_eq <= 1'b1; + end + else + begin + redist8_expPostRndFR_uid81_fpDivTest_b_7_rdcnt_eq <= 1'b0; + end + if (redist8_expPostRndFR_uid81_fpDivTest_b_7_rdcnt_eq == 1'b1) + begin + redist8_expPostRndFR_uid81_fpDivTest_b_7_rdcnt_i <= $unsigned(redist8_expPostRndFR_uid81_fpDivTest_b_7_rdcnt_i) + $unsigned(3'd4); + end + else + begin + redist8_expPostRndFR_uid81_fpDivTest_b_7_rdcnt_i <= $unsigned(redist8_expPostRndFR_uid81_fpDivTest_b_7_rdcnt_i) + $unsigned(3'd1); + end + end + end + assign redist8_expPostRndFR_uid81_fpDivTest_b_7_rdcnt_q = redist8_expPostRndFR_uid81_fpDivTest_b_7_rdcnt_i[2:0]; + + // redist8_expPostRndFR_uid81_fpDivTest_b_7_rdmux(MUX,237) + assign redist8_expPostRndFR_uid81_fpDivTest_b_7_rdmux_s = en; + always @(redist8_expPostRndFR_uid81_fpDivTest_b_7_rdmux_s or redist8_expPostRndFR_uid81_fpDivTest_b_7_wraddr_q or redist8_expPostRndFR_uid81_fpDivTest_b_7_rdcnt_q) + begin + unique case (redist8_expPostRndFR_uid81_fpDivTest_b_7_rdmux_s) + 1'b0 : redist8_expPostRndFR_uid81_fpDivTest_b_7_rdmux_q = redist8_expPostRndFR_uid81_fpDivTest_b_7_wraddr_q; + 1'b1 : redist8_expPostRndFR_uid81_fpDivTest_b_7_rdmux_q = redist8_expPostRndFR_uid81_fpDivTest_b_7_rdcnt_q; + default : redist8_expPostRndFR_uid81_fpDivTest_b_7_rdmux_q = 3'b0; + endcase + end + + // expPostRndFR_uid81_fpDivTest(BITSELECT,80)@24 + assign expPostRndFR_uid81_fpDivTest_in = expFracPostRnd_uid76_fpDivTest_q[32:0]; + assign expPostRndFR_uid81_fpDivTest_b = expPostRndFR_uid81_fpDivTest_in[32:25]; + + // redist8_expPostRndFR_uid81_fpDivTest_b_7_wraddr(REG,238) + always @ (posedge clk) + begin + if (areset) + begin + redist8_expPostRndFR_uid81_fpDivTest_b_7_wraddr_q <= 3'b100; + end + else + begin + redist8_expPostRndFR_uid81_fpDivTest_b_7_wraddr_q <= redist8_expPostRndFR_uid81_fpDivTest_b_7_rdmux_q; + end + end + + // redist8_expPostRndFR_uid81_fpDivTest_b_7_mem(DUALMEM,235) + assign redist8_expPostRndFR_uid81_fpDivTest_b_7_mem_ia = expPostRndFR_uid81_fpDivTest_b; + assign redist8_expPostRndFR_uid81_fpDivTest_b_7_mem_aa = redist8_expPostRndFR_uid81_fpDivTest_b_7_wraddr_q; + assign redist8_expPostRndFR_uid81_fpDivTest_b_7_mem_ab = redist8_expPostRndFR_uid81_fpDivTest_b_7_rdmux_q; + assign redist8_expPostRndFR_uid81_fpDivTest_b_7_mem_reset0 = areset; + altera_syncram #( + .ram_block_type("MLAB"), + .operation_mode("DUAL_PORT"), + .width_a(8), + .widthad_a(3), + .numwords_a(5), + .width_b(8), + .widthad_b(3), + .numwords_b(5), + .lpm_type("altera_syncram"), + .width_byteena_a(1), + .address_reg_b("CLOCK0"), + .indata_reg_b("CLOCK0"), + .rdcontrol_reg_b("CLOCK0"), + .byteena_reg_b("CLOCK0"), + .outdata_reg_b("CLOCK1"), + .outdata_sclr_b("SCLEAR"), + .clock_enable_input_a("NORMAL"), + .clock_enable_input_b("NORMAL"), + .clock_enable_output_b("NORMAL"), + .read_during_write_mode_mixed_ports("DONT_CARE"), + .power_up_uninitialized("TRUE"), + .intended_device_family("Stratix 10") + ) redist8_expPostRndFR_uid81_fpDivTest_b_7_mem_dmem ( + .clocken1(redist8_expPostRndFR_uid81_fpDivTest_b_7_mem_enaOr_rst), + .clocken0(VCC_q[0]), + .clock0(clk), + .sclr(redist8_expPostRndFR_uid81_fpDivTest_b_7_mem_reset0), + .clock1(clk), + .address_a(redist8_expPostRndFR_uid81_fpDivTest_b_7_mem_aa), + .data_a(redist8_expPostRndFR_uid81_fpDivTest_b_7_mem_ia), + .wren_a(en[0]), + .address_b(redist8_expPostRndFR_uid81_fpDivTest_b_7_mem_ab), + .q_b(redist8_expPostRndFR_uid81_fpDivTest_b_7_mem_iq), + .wren_b(), + .rden_a(), + .rden_b(), + .data_b(), + .clocken2(), + .clocken3(), + .aclr0(), + .aclr1(), + .addressstall_a(), + .addressstall_b(), + .byteena_a(), + .byteena_b(), + .eccencbypass(), + .eccencparity(), + .address2_a(), + .address2_b(), + .q_a(), + .eccstatus() + ); + assign redist8_expPostRndFR_uid81_fpDivTest_b_7_mem_q = redist8_expPostRndFR_uid81_fpDivTest_b_7_mem_iq[7:0]; + assign redist8_expPostRndFR_uid81_fpDivTest_b_7_mem_enaOr_rst = redist8_expPostRndFR_uid81_fpDivTest_b_7_enaAnd_q[0] | redist8_expPostRndFR_uid81_fpDivTest_b_7_mem_reset0; + + // redist8_expPostRndFR_uid81_fpDivTest_b_7_outputreg0(DELAY,234) + always @ (posedge clk) + begin + if (areset) + begin + redist8_expPostRndFR_uid81_fpDivTest_b_7_outputreg0_q <= '0; + end + else if (en == 1'b1) + begin + redist8_expPostRndFR_uid81_fpDivTest_b_7_outputreg0_q <= redist8_expPostRndFR_uid81_fpDivTest_b_7_mem_q; + end + end + + // redist9_expPostRndFR_uid81_fpDivTest_b_9(DELAY,195) + always @ (posedge clk) + begin + if (areset) + begin + redist9_expPostRndFR_uid81_fpDivTest_b_9_delay_0 <= '0; + redist9_expPostRndFR_uid81_fpDivTest_b_9_q <= '0; + end + else if (en == 1'b1) + begin + redist9_expPostRndFR_uid81_fpDivTest_b_9_delay_0 <= redist8_expPostRndFR_uid81_fpDivTest_b_7_outputreg0_q; + redist9_expPostRndFR_uid81_fpDivTest_b_9_q <= redist9_expPostRndFR_uid81_fpDivTest_b_9_delay_0; + end + end + + // betweenFPwF_uid102_fpDivTest(BITSELECT,101)@25 + assign betweenFPwF_uid102_fpDivTest_in = fracPostRndF_uid80_fpDivTest_q[0:0]; + assign betweenFPwF_uid102_fpDivTest_b = betweenFPwF_uid102_fpDivTest_in[0:0]; + + // redist5_betweenFPwF_uid102_fpDivTest_b_7(DELAY,191) + dspba_delay_ver #( .width(1), .depth(7), .reset_kind("SYNC"), .phase(0), .modulus(1) ) + redist5_betweenFPwF_uid102_fpDivTest_b_7 ( .xin(betweenFPwF_uid102_fpDivTest_b), .xout(redist5_betweenFPwF_uid102_fpDivTest_b_7_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // redist35_expX_uid9_fpDivTest_b_31_notEnable(LOGICAL,380) + assign redist35_expX_uid9_fpDivTest_b_31_notEnable_q = ~ (en); + + // redist35_expX_uid9_fpDivTest_b_31_nor(LOGICAL,381) + assign redist35_expX_uid9_fpDivTest_b_31_nor_q = ~ (redist35_expX_uid9_fpDivTest_b_31_notEnable_q | redist35_expX_uid9_fpDivTest_b_31_sticky_ena_q); + + // redist35_expX_uid9_fpDivTest_b_31_mem_last(CONSTANT,377) + assign redist35_expX_uid9_fpDivTest_b_31_mem_last_q = 3'b011; + + // redist35_expX_uid9_fpDivTest_b_31_cmp(LOGICAL,378) + assign redist35_expX_uid9_fpDivTest_b_31_cmp_q = redist35_expX_uid9_fpDivTest_b_31_mem_last_q == redist35_expX_uid9_fpDivTest_b_31_rdmux_q ? 1'b1 : 1'b0; + + // redist35_expX_uid9_fpDivTest_b_31_cmpReg(REG,379) + always @ (posedge clk) + begin + if (areset) + begin + redist35_expX_uid9_fpDivTest_b_31_cmpReg_q <= 1'b0; + end + else if (en == 1'b1) + begin + redist35_expX_uid9_fpDivTest_b_31_cmpReg_q <= redist35_expX_uid9_fpDivTest_b_31_cmp_q; + end + end + + // redist35_expX_uid9_fpDivTest_b_31_sticky_ena(REG,382) + always @ (posedge clk) + begin + if (areset) + begin + redist35_expX_uid9_fpDivTest_b_31_sticky_ena_q <= 1'b0; + end + else if (redist35_expX_uid9_fpDivTest_b_31_nor_q == 1'b1) + begin + redist35_expX_uid9_fpDivTest_b_31_sticky_ena_q <= redist35_expX_uid9_fpDivTest_b_31_cmpReg_q; + end + end + + // redist35_expX_uid9_fpDivTest_b_31_enaAnd(LOGICAL,383) + assign redist35_expX_uid9_fpDivTest_b_31_enaAnd_q = redist35_expX_uid9_fpDivTest_b_31_sticky_ena_q & en; + + // redist35_expX_uid9_fpDivTest_b_31_rdcnt(COUNTER,374) + // low=0, high=4, step=1, init=0 + always @ (posedge clk) + begin + if (areset) + begin + redist35_expX_uid9_fpDivTest_b_31_rdcnt_i <= 3'd0; + redist35_expX_uid9_fpDivTest_b_31_rdcnt_eq <= 1'b0; + end + else if (en == 1'b1) + begin + if (redist35_expX_uid9_fpDivTest_b_31_rdcnt_i == 3'd3) + begin + redist35_expX_uid9_fpDivTest_b_31_rdcnt_eq <= 1'b1; + end + else + begin + redist35_expX_uid9_fpDivTest_b_31_rdcnt_eq <= 1'b0; + end + if (redist35_expX_uid9_fpDivTest_b_31_rdcnt_eq == 1'b1) + begin + redist35_expX_uid9_fpDivTest_b_31_rdcnt_i <= $unsigned(redist35_expX_uid9_fpDivTest_b_31_rdcnt_i) + $unsigned(3'd4); + end + else + begin + redist35_expX_uid9_fpDivTest_b_31_rdcnt_i <= $unsigned(redist35_expX_uid9_fpDivTest_b_31_rdcnt_i) + $unsigned(3'd1); + end + end + end + assign redist35_expX_uid9_fpDivTest_b_31_rdcnt_q = redist35_expX_uid9_fpDivTest_b_31_rdcnt_i[2:0]; + + // redist35_expX_uid9_fpDivTest_b_31_rdmux(MUX,375) + assign redist35_expX_uid9_fpDivTest_b_31_rdmux_s = en; + always @(redist35_expX_uid9_fpDivTest_b_31_rdmux_s or redist35_expX_uid9_fpDivTest_b_31_wraddr_q or redist35_expX_uid9_fpDivTest_b_31_rdcnt_q) + begin + unique case (redist35_expX_uid9_fpDivTest_b_31_rdmux_s) + 1'b0 : redist35_expX_uid9_fpDivTest_b_31_rdmux_q = redist35_expX_uid9_fpDivTest_b_31_wraddr_q; + 1'b1 : redist35_expX_uid9_fpDivTest_b_31_rdmux_q = redist35_expX_uid9_fpDivTest_b_31_rdcnt_q; + default : redist35_expX_uid9_fpDivTest_b_31_rdmux_q = 3'b0; + endcase + end + + // redist35_expX_uid9_fpDivTest_b_31_wraddr(REG,376) + always @ (posedge clk) + begin + if (areset) + begin + redist35_expX_uid9_fpDivTest_b_31_wraddr_q <= 3'b100; + end + else + begin + redist35_expX_uid9_fpDivTest_b_31_wraddr_q <= redist35_expX_uid9_fpDivTest_b_31_rdmux_q; + end + end + + // redist35_expX_uid9_fpDivTest_b_31_mem(DUALMEM,373) + assign redist35_expX_uid9_fpDivTest_b_31_mem_ia = redist34_expX_uid9_fpDivTest_b_24_q; + assign redist35_expX_uid9_fpDivTest_b_31_mem_aa = redist35_expX_uid9_fpDivTest_b_31_wraddr_q; + assign redist35_expX_uid9_fpDivTest_b_31_mem_ab = redist35_expX_uid9_fpDivTest_b_31_rdmux_q; + assign redist35_expX_uid9_fpDivTest_b_31_mem_reset0 = areset; + altera_syncram #( + .ram_block_type("MLAB"), + .operation_mode("DUAL_PORT"), + .width_a(8), + .widthad_a(3), + .numwords_a(5), + .width_b(8), + .widthad_b(3), + .numwords_b(5), + .lpm_type("altera_syncram"), + .width_byteena_a(1), + .address_reg_b("CLOCK0"), + .indata_reg_b("CLOCK0"), + .rdcontrol_reg_b("CLOCK0"), + .byteena_reg_b("CLOCK0"), + .outdata_reg_b("CLOCK1"), + .outdata_sclr_b("SCLEAR"), + .clock_enable_input_a("NORMAL"), + .clock_enable_input_b("NORMAL"), + .clock_enable_output_b("NORMAL"), + .read_during_write_mode_mixed_ports("DONT_CARE"), + .power_up_uninitialized("TRUE"), + .intended_device_family("Stratix 10") + ) redist35_expX_uid9_fpDivTest_b_31_mem_dmem ( + .clocken1(redist35_expX_uid9_fpDivTest_b_31_mem_enaOr_rst), + .clocken0(VCC_q[0]), + .clock0(clk), + .sclr(redist35_expX_uid9_fpDivTest_b_31_mem_reset0), + .clock1(clk), + .address_a(redist35_expX_uid9_fpDivTest_b_31_mem_aa), + .data_a(redist35_expX_uid9_fpDivTest_b_31_mem_ia), + .wren_a(en[0]), + .address_b(redist35_expX_uid9_fpDivTest_b_31_mem_ab), + .q_b(redist35_expX_uid9_fpDivTest_b_31_mem_iq), + .wren_b(), + .rden_a(), + .rden_b(), + .data_b(), + .clocken2(), + .clocken3(), + .aclr0(), + .aclr1(), + .addressstall_a(), + .addressstall_b(), + .byteena_a(), + .byteena_b(), + .eccencbypass(), + .eccencparity(), + .address2_a(), + .address2_b(), + .q_a(), + .eccstatus() + ); + assign redist35_expX_uid9_fpDivTest_b_31_mem_q = redist35_expX_uid9_fpDivTest_b_31_mem_iq[7:0]; + assign redist35_expX_uid9_fpDivTest_b_31_mem_enaOr_rst = redist35_expX_uid9_fpDivTest_b_31_enaAnd_q[0] | redist35_expX_uid9_fpDivTest_b_31_mem_reset0; + + // redist35_expX_uid9_fpDivTest_b_31_outputreg0(DELAY,372) + always @ (posedge clk) + begin + if (areset) + begin + redist35_expX_uid9_fpDivTest_b_31_outputreg0_q <= '0; + end + else if (en == 1'b1) + begin + redist35_expX_uid9_fpDivTest_b_31_outputreg0_q <= redist35_expX_uid9_fpDivTest_b_31_mem_q; + end + end + + // redist36_expX_uid9_fpDivTest_b_32(DELAY,222) + always @ (posedge clk) + begin + if (areset) + begin + redist36_expX_uid9_fpDivTest_b_32_q <= '0; + end + else if (en == 1'b1) + begin + redist36_expX_uid9_fpDivTest_b_32_q <= redist35_expX_uid9_fpDivTest_b_31_outputreg0_q; + end + end + + // redist32_fracX_uid10_fpDivTest_b_32_notEnable(LOGICAL,357) + assign redist32_fracX_uid10_fpDivTest_b_32_notEnable_q = ~ (en); + + // redist32_fracX_uid10_fpDivTest_b_32_nor(LOGICAL,358) + assign redist32_fracX_uid10_fpDivTest_b_32_nor_q = ~ (redist32_fracX_uid10_fpDivTest_b_32_notEnable_q | redist32_fracX_uid10_fpDivTest_b_32_sticky_ena_q); + + // redist32_fracX_uid10_fpDivTest_b_32_mem_last(CONSTANT,354) + assign redist32_fracX_uid10_fpDivTest_b_32_mem_last_q = 4'b0100; + + // redist32_fracX_uid10_fpDivTest_b_32_cmp(LOGICAL,355) + assign redist32_fracX_uid10_fpDivTest_b_32_cmp_b = {1'b0, redist32_fracX_uid10_fpDivTest_b_32_rdmux_q}; + assign redist32_fracX_uid10_fpDivTest_b_32_cmp_q = redist32_fracX_uid10_fpDivTest_b_32_mem_last_q == redist32_fracX_uid10_fpDivTest_b_32_cmp_b ? 1'b1 : 1'b0; + + // redist32_fracX_uid10_fpDivTest_b_32_cmpReg(REG,356) + always @ (posedge clk) + begin + if (areset) + begin + redist32_fracX_uid10_fpDivTest_b_32_cmpReg_q <= 1'b0; + end + else if (en == 1'b1) + begin + redist32_fracX_uid10_fpDivTest_b_32_cmpReg_q <= redist32_fracX_uid10_fpDivTest_b_32_cmp_q; + end + end + + // redist32_fracX_uid10_fpDivTest_b_32_sticky_ena(REG,359) + always @ (posedge clk) + begin + if (areset) + begin + redist32_fracX_uid10_fpDivTest_b_32_sticky_ena_q <= 1'b0; + end + else if (redist32_fracX_uid10_fpDivTest_b_32_nor_q == 1'b1) + begin + redist32_fracX_uid10_fpDivTest_b_32_sticky_ena_q <= redist32_fracX_uid10_fpDivTest_b_32_cmpReg_q; + end + end + + // redist32_fracX_uid10_fpDivTest_b_32_enaAnd(LOGICAL,360) + assign redist32_fracX_uid10_fpDivTest_b_32_enaAnd_q = redist32_fracX_uid10_fpDivTest_b_32_sticky_ena_q & en; + + // redist32_fracX_uid10_fpDivTest_b_32_rdcnt(COUNTER,351) + // low=0, high=5, step=1, init=0 + always @ (posedge clk) + begin + if (areset) + begin + redist32_fracX_uid10_fpDivTest_b_32_rdcnt_i <= 3'd0; + redist32_fracX_uid10_fpDivTest_b_32_rdcnt_eq <= 1'b0; + end + else if (en == 1'b1) + begin + if (redist32_fracX_uid10_fpDivTest_b_32_rdcnt_i == 3'd4) + begin + redist32_fracX_uid10_fpDivTest_b_32_rdcnt_eq <= 1'b1; + end + else + begin + redist32_fracX_uid10_fpDivTest_b_32_rdcnt_eq <= 1'b0; + end + if (redist32_fracX_uid10_fpDivTest_b_32_rdcnt_eq == 1'b1) + begin + redist32_fracX_uid10_fpDivTest_b_32_rdcnt_i <= $unsigned(redist32_fracX_uid10_fpDivTest_b_32_rdcnt_i) + $unsigned(3'd3); + end + else + begin + redist32_fracX_uid10_fpDivTest_b_32_rdcnt_i <= $unsigned(redist32_fracX_uid10_fpDivTest_b_32_rdcnt_i) + $unsigned(3'd1); + end + end + end + assign redist32_fracX_uid10_fpDivTest_b_32_rdcnt_q = redist32_fracX_uid10_fpDivTest_b_32_rdcnt_i[2:0]; + + // redist32_fracX_uid10_fpDivTest_b_32_rdmux(MUX,352) + assign redist32_fracX_uid10_fpDivTest_b_32_rdmux_s = en; + always @(redist32_fracX_uid10_fpDivTest_b_32_rdmux_s or redist32_fracX_uid10_fpDivTest_b_32_wraddr_q or redist32_fracX_uid10_fpDivTest_b_32_rdcnt_q) + begin + unique case (redist32_fracX_uid10_fpDivTest_b_32_rdmux_s) + 1'b0 : redist32_fracX_uid10_fpDivTest_b_32_rdmux_q = redist32_fracX_uid10_fpDivTest_b_32_wraddr_q; + 1'b1 : redist32_fracX_uid10_fpDivTest_b_32_rdmux_q = redist32_fracX_uid10_fpDivTest_b_32_rdcnt_q; + default : redist32_fracX_uid10_fpDivTest_b_32_rdmux_q = 3'b0; + endcase + end + + // redist32_fracX_uid10_fpDivTest_b_32_wraddr(REG,353) + always @ (posedge clk) + begin + if (areset) + begin + redist32_fracX_uid10_fpDivTest_b_32_wraddr_q <= 3'b101; + end + else + begin + redist32_fracX_uid10_fpDivTest_b_32_wraddr_q <= redist32_fracX_uid10_fpDivTest_b_32_rdmux_q; + end + end + + // redist32_fracX_uid10_fpDivTest_b_32_mem(DUALMEM,350) + assign redist32_fracX_uid10_fpDivTest_b_32_mem_ia = redist31_fracX_uid10_fpDivTest_b_25_q; + assign redist32_fracX_uid10_fpDivTest_b_32_mem_aa = redist32_fracX_uid10_fpDivTest_b_32_wraddr_q; + assign redist32_fracX_uid10_fpDivTest_b_32_mem_ab = redist32_fracX_uid10_fpDivTest_b_32_rdmux_q; + assign redist32_fracX_uid10_fpDivTest_b_32_mem_reset0 = areset; + altera_syncram #( + .ram_block_type("MLAB"), + .operation_mode("DUAL_PORT"), + .width_a(23), + .widthad_a(3), + .numwords_a(6), + .width_b(23), + .widthad_b(3), + .numwords_b(6), + .lpm_type("altera_syncram"), + .width_byteena_a(1), + .address_reg_b("CLOCK0"), + .indata_reg_b("CLOCK0"), + .rdcontrol_reg_b("CLOCK0"), + .byteena_reg_b("CLOCK0"), + .outdata_reg_b("CLOCK1"), + .outdata_sclr_b("SCLEAR"), + .clock_enable_input_a("NORMAL"), + .clock_enable_input_b("NORMAL"), + .clock_enable_output_b("NORMAL"), + .read_during_write_mode_mixed_ports("DONT_CARE"), + .power_up_uninitialized("TRUE"), + .intended_device_family("Stratix 10") + ) redist32_fracX_uid10_fpDivTest_b_32_mem_dmem ( + .clocken1(redist32_fracX_uid10_fpDivTest_b_32_mem_enaOr_rst), + .clocken0(VCC_q[0]), + .clock0(clk), + .sclr(redist32_fracX_uid10_fpDivTest_b_32_mem_reset0), + .clock1(clk), + .address_a(redist32_fracX_uid10_fpDivTest_b_32_mem_aa), + .data_a(redist32_fracX_uid10_fpDivTest_b_32_mem_ia), + .wren_a(en[0]), + .address_b(redist32_fracX_uid10_fpDivTest_b_32_mem_ab), + .q_b(redist32_fracX_uid10_fpDivTest_b_32_mem_iq), + .wren_b(), + .rden_a(), + .rden_b(), + .data_b(), + .clocken2(), + .clocken3(), + .aclr0(), + .aclr1(), + .addressstall_a(), + .addressstall_b(), + .byteena_a(), + .byteena_b(), + .eccencbypass(), + .eccencparity(), + .address2_a(), + .address2_b(), + .q_a(), + .eccstatus() + ); + assign redist32_fracX_uid10_fpDivTest_b_32_mem_q = redist32_fracX_uid10_fpDivTest_b_32_mem_iq[22:0]; + assign redist32_fracX_uid10_fpDivTest_b_32_mem_enaOr_rst = redist32_fracX_uid10_fpDivTest_b_32_enaAnd_q[0] | redist32_fracX_uid10_fpDivTest_b_32_mem_reset0; + + // qDivProdLTX_opB_uid100_fpDivTest(BITJOIN,99)@32 + assign qDivProdLTX_opB_uid100_fpDivTest_q = {redist36_expX_uid9_fpDivTest_b_32_q, redist32_fracX_uid10_fpDivTest_b_32_mem_q}; + + // redist25_fracY_uid13_fpDivTest_b_25(DELAY,211) + always @ (posedge clk) + begin + if (areset) + begin + redist25_fracY_uid13_fpDivTest_b_25_q <= '0; + end + else if (en == 1'b1) + begin + redist25_fracY_uid13_fpDivTest_b_25_q <= redist24_fracY_uid13_fpDivTest_b_24_q; + end + end + + // lOAdded_uid87_fpDivTest(BITJOIN,86)@25 + assign lOAdded_uid87_fpDivTest_q = {VCC_q, redist25_fracY_uid13_fpDivTest_b_25_q}; + + // lOAdded_uid84_fpDivTest(BITJOIN,83)@25 + assign lOAdded_uid84_fpDivTest_q = {VCC_q, fracPostRndF_uid80_fpDivTest_q}; + + // qDivProd_uid89_fpDivTest_cma(CHAINMULTADD,182)@25 + 5 + // out q@31 + assign qDivProd_uid89_fpDivTest_cma_reset = areset; + assign qDivProd_uid89_fpDivTest_cma_ena0 = en[0] | qDivProd_uid89_fpDivTest_cma_reset; + assign qDivProd_uid89_fpDivTest_cma_ena1 = qDivProd_uid89_fpDivTest_cma_ena0; + assign qDivProd_uid89_fpDivTest_cma_ena2 = qDivProd_uid89_fpDivTest_cma_ena0; + always @ (posedge clk) + begin + if (0) + begin + end + else + begin + if (en == 1'b1) + begin + qDivProd_uid89_fpDivTest_cma_ah[0] <= lOAdded_uid84_fpDivTest_q; + qDivProd_uid89_fpDivTest_cma_ch[0] <= lOAdded_uid87_fpDivTest_q; + end + end + end + + assign qDivProd_uid89_fpDivTest_cma_a0 = qDivProd_uid89_fpDivTest_cma_ah[0]; + assign qDivProd_uid89_fpDivTest_cma_c0 = qDivProd_uid89_fpDivTest_cma_ch[0]; + fourteennm_mac #( + .operation_mode("m27x27"), + .clear_type("sclr"), + .use_chainadder("false"), + .ay_scan_in_clock("0"), + .ay_scan_in_width(25), + .ax_clock("0"), + .ax_width(24), + .signed_may("false"), + .signed_max("false"), + .input_pipeline_clock("2"), + .second_pipeline_clock("2"), + .output_clock("1"), + .result_a_width(49) + ) qDivProd_uid89_fpDivTest_cma_DSP0 ( + .clk({clk,clk,clk}), + .ena({ qDivProd_uid89_fpDivTest_cma_ena2, qDivProd_uid89_fpDivTest_cma_ena1, qDivProd_uid89_fpDivTest_cma_ena0 }), + .clr({ qDivProd_uid89_fpDivTest_cma_reset, qDivProd_uid89_fpDivTest_cma_reset }), + .ay(qDivProd_uid89_fpDivTest_cma_a0), + .ax(qDivProd_uid89_fpDivTest_cma_c0), + .resulta(qDivProd_uid89_fpDivTest_cma_s0), + .accumulate(), + .loadconst(), + .negate(), + .sub(), + .az(), + .coefsela(), + .bx(), + .by(), + .bz(), + .coefselb(), + .scanin(), + .scanout(), + .chainin(), + .chainout(), + .resultb(), + .dfxlfsrena(), + .dfxmisrena(), + .dftout() + ); + dspba_delay_ver #( .width(49), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1) ) + qDivProd_uid89_fpDivTest_cma_delay ( .xin(qDivProd_uid89_fpDivTest_cma_s0), .xout(qDivProd_uid89_fpDivTest_cma_qq), .ena(en[0]), .clk(clk), .aclr(areset) ); + assign qDivProd_uid89_fpDivTest_cma_q = qDivProd_uid89_fpDivTest_cma_qq[48:0]; + + // qDivProdNorm_uid90_fpDivTest(BITSELECT,89)@31 + assign qDivProdNorm_uid90_fpDivTest_b = qDivProd_uid89_fpDivTest_cma_q[48:48]; + + // cstBias_uid7_fpDivTest(CONSTANT,6) + assign cstBias_uid7_fpDivTest_q = 8'b01111111; + + // qDivProdExp_opBs_uid95_fpDivTest(SUB,94)@31 + assign qDivProdExp_opBs_uid95_fpDivTest_a = {1'b0, cstBias_uid7_fpDivTest_q}; + assign qDivProdExp_opBs_uid95_fpDivTest_b = {8'b00000000, qDivProdNorm_uid90_fpDivTest_b}; + assign qDivProdExp_opBs_uid95_fpDivTest_o = $unsigned(qDivProdExp_opBs_uid95_fpDivTest_a) - $unsigned(qDivProdExp_opBs_uid95_fpDivTest_b); + assign qDivProdExp_opBs_uid95_fpDivTest_q = qDivProdExp_opBs_uid95_fpDivTest_o[8:0]; + + // redist14_invYO_uid55_fpDivTest_b_15(DELAY,200) + dspba_delay_ver #( .width(1), .depth(6), .reset_kind("SYNC"), .phase(0), .modulus(1) ) + redist14_invYO_uid55_fpDivTest_b_15 ( .xin(redist13_invYO_uid55_fpDivTest_b_9_q), .xout(redist14_invYO_uid55_fpDivTest_b_15_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // expPostRndF_uid82_fpDivTest(MUX,81)@31 + assign expPostRndF_uid82_fpDivTest_s = redist14_invYO_uid55_fpDivTest_b_15_q; + always @(expPostRndF_uid82_fpDivTest_s or en or redist8_expPostRndFR_uid81_fpDivTest_b_7_outputreg0_q or redist35_expX_uid9_fpDivTest_b_31_outputreg0_q) + begin + unique case (expPostRndF_uid82_fpDivTest_s) + 1'b0 : expPostRndF_uid82_fpDivTest_q = redist8_expPostRndFR_uid81_fpDivTest_b_7_outputreg0_q; + 1'b1 : expPostRndF_uid82_fpDivTest_q = redist35_expX_uid9_fpDivTest_b_31_outputreg0_q; + default : expPostRndF_uid82_fpDivTest_q = 8'b0; + endcase + end + + // redist28_expY_uid12_fpDivTest_b_31_notEnable(LOGICAL,323) + assign redist28_expY_uid12_fpDivTest_b_31_notEnable_q = ~ (en); + + // redist28_expY_uid12_fpDivTest_b_31_nor(LOGICAL,324) + assign redist28_expY_uid12_fpDivTest_b_31_nor_q = ~ (redist28_expY_uid12_fpDivTest_b_31_notEnable_q | redist28_expY_uid12_fpDivTest_b_31_sticky_ena_q); + + // redist28_expY_uid12_fpDivTest_b_31_mem_last(CONSTANT,320) + assign redist28_expY_uid12_fpDivTest_b_31_mem_last_q = 3'b011; + + // redist28_expY_uid12_fpDivTest_b_31_cmp(LOGICAL,321) + assign redist28_expY_uid12_fpDivTest_b_31_cmp_q = redist28_expY_uid12_fpDivTest_b_31_mem_last_q == redist28_expY_uid12_fpDivTest_b_31_rdmux_q ? 1'b1 : 1'b0; + + // redist28_expY_uid12_fpDivTest_b_31_cmpReg(REG,322) + always @ (posedge clk) + begin + if (areset) + begin + redist28_expY_uid12_fpDivTest_b_31_cmpReg_q <= 1'b0; + end + else if (en == 1'b1) + begin + redist28_expY_uid12_fpDivTest_b_31_cmpReg_q <= redist28_expY_uid12_fpDivTest_b_31_cmp_q; + end + end + + // redist28_expY_uid12_fpDivTest_b_31_sticky_ena(REG,325) + always @ (posedge clk) + begin + if (areset) + begin + redist28_expY_uid12_fpDivTest_b_31_sticky_ena_q <= 1'b0; + end + else if (redist28_expY_uid12_fpDivTest_b_31_nor_q == 1'b1) + begin + redist28_expY_uid12_fpDivTest_b_31_sticky_ena_q <= redist28_expY_uid12_fpDivTest_b_31_cmpReg_q; + end + end + + // redist28_expY_uid12_fpDivTest_b_31_enaAnd(LOGICAL,326) + assign redist28_expY_uid12_fpDivTest_b_31_enaAnd_q = redist28_expY_uid12_fpDivTest_b_31_sticky_ena_q & en; + + // redist28_expY_uid12_fpDivTest_b_31_rdcnt(COUNTER,317) + // low=0, high=4, step=1, init=0 + always @ (posedge clk) + begin + if (areset) + begin + redist28_expY_uid12_fpDivTest_b_31_rdcnt_i <= 3'd0; + redist28_expY_uid12_fpDivTest_b_31_rdcnt_eq <= 1'b0; + end + else if (en == 1'b1) + begin + if (redist28_expY_uid12_fpDivTest_b_31_rdcnt_i == 3'd3) + begin + redist28_expY_uid12_fpDivTest_b_31_rdcnt_eq <= 1'b1; + end + else + begin + redist28_expY_uid12_fpDivTest_b_31_rdcnt_eq <= 1'b0; + end + if (redist28_expY_uid12_fpDivTest_b_31_rdcnt_eq == 1'b1) + begin + redist28_expY_uid12_fpDivTest_b_31_rdcnt_i <= $unsigned(redist28_expY_uid12_fpDivTest_b_31_rdcnt_i) + $unsigned(3'd4); + end + else + begin + redist28_expY_uid12_fpDivTest_b_31_rdcnt_i <= $unsigned(redist28_expY_uid12_fpDivTest_b_31_rdcnt_i) + $unsigned(3'd1); + end + end + end + assign redist28_expY_uid12_fpDivTest_b_31_rdcnt_q = redist28_expY_uid12_fpDivTest_b_31_rdcnt_i[2:0]; + + // redist28_expY_uid12_fpDivTest_b_31_rdmux(MUX,318) + assign redist28_expY_uid12_fpDivTest_b_31_rdmux_s = en; + always @(redist28_expY_uid12_fpDivTest_b_31_rdmux_s or redist28_expY_uid12_fpDivTest_b_31_wraddr_q or redist28_expY_uid12_fpDivTest_b_31_rdcnt_q) + begin + unique case (redist28_expY_uid12_fpDivTest_b_31_rdmux_s) + 1'b0 : redist28_expY_uid12_fpDivTest_b_31_rdmux_q = redist28_expY_uid12_fpDivTest_b_31_wraddr_q; + 1'b1 : redist28_expY_uid12_fpDivTest_b_31_rdmux_q = redist28_expY_uid12_fpDivTest_b_31_rdcnt_q; + default : redist28_expY_uid12_fpDivTest_b_31_rdmux_q = 3'b0; + endcase + end + + // redist28_expY_uid12_fpDivTest_b_31_wraddr(REG,319) + always @ (posedge clk) + begin + if (areset) + begin + redist28_expY_uid12_fpDivTest_b_31_wraddr_q <= 3'b100; + end + else + begin + redist28_expY_uid12_fpDivTest_b_31_wraddr_q <= redist28_expY_uid12_fpDivTest_b_31_rdmux_q; + end + end + + // redist28_expY_uid12_fpDivTest_b_31_mem(DUALMEM,316) + assign redist28_expY_uid12_fpDivTest_b_31_mem_ia = redist27_expY_uid12_fpDivTest_b_24_q; + assign redist28_expY_uid12_fpDivTest_b_31_mem_aa = redist28_expY_uid12_fpDivTest_b_31_wraddr_q; + assign redist28_expY_uid12_fpDivTest_b_31_mem_ab = redist28_expY_uid12_fpDivTest_b_31_rdmux_q; + assign redist28_expY_uid12_fpDivTest_b_31_mem_reset0 = areset; + altera_syncram #( + .ram_block_type("MLAB"), + .operation_mode("DUAL_PORT"), + .width_a(8), + .widthad_a(3), + .numwords_a(5), + .width_b(8), + .widthad_b(3), + .numwords_b(5), + .lpm_type("altera_syncram"), + .width_byteena_a(1), + .address_reg_b("CLOCK0"), + .indata_reg_b("CLOCK0"), + .rdcontrol_reg_b("CLOCK0"), + .byteena_reg_b("CLOCK0"), + .outdata_reg_b("CLOCK1"), + .outdata_sclr_b("SCLEAR"), + .clock_enable_input_a("NORMAL"), + .clock_enable_input_b("NORMAL"), + .clock_enable_output_b("NORMAL"), + .read_during_write_mode_mixed_ports("DONT_CARE"), + .power_up_uninitialized("TRUE"), + .intended_device_family("Stratix 10") + ) redist28_expY_uid12_fpDivTest_b_31_mem_dmem ( + .clocken1(redist28_expY_uid12_fpDivTest_b_31_mem_enaOr_rst), + .clocken0(VCC_q[0]), + .clock0(clk), + .sclr(redist28_expY_uid12_fpDivTest_b_31_mem_reset0), + .clock1(clk), + .address_a(redist28_expY_uid12_fpDivTest_b_31_mem_aa), + .data_a(redist28_expY_uid12_fpDivTest_b_31_mem_ia), + .wren_a(en[0]), + .address_b(redist28_expY_uid12_fpDivTest_b_31_mem_ab), + .q_b(redist28_expY_uid12_fpDivTest_b_31_mem_iq), + .wren_b(), + .rden_a(), + .rden_b(), + .data_b(), + .clocken2(), + .clocken3(), + .aclr0(), + .aclr1(), + .addressstall_a(), + .addressstall_b(), + .byteena_a(), + .byteena_b(), + .eccencbypass(), + .eccencparity(), + .address2_a(), + .address2_b(), + .q_a(), + .eccstatus() + ); + assign redist28_expY_uid12_fpDivTest_b_31_mem_q = redist28_expY_uid12_fpDivTest_b_31_mem_iq[7:0]; + assign redist28_expY_uid12_fpDivTest_b_31_mem_enaOr_rst = redist28_expY_uid12_fpDivTest_b_31_enaAnd_q[0] | redist28_expY_uid12_fpDivTest_b_31_mem_reset0; + + // redist28_expY_uid12_fpDivTest_b_31_outputreg0(DELAY,315) + always @ (posedge clk) + begin + if (areset) + begin + redist28_expY_uid12_fpDivTest_b_31_outputreg0_q <= '0; + end + else if (en == 1'b1) + begin + redist28_expY_uid12_fpDivTest_b_31_outputreg0_q <= redist28_expY_uid12_fpDivTest_b_31_mem_q; + end + end + + // qDivProdExp_opA_uid94_fpDivTest(ADD,93)@31 + assign qDivProdExp_opA_uid94_fpDivTest_a = {1'b0, redist28_expY_uid12_fpDivTest_b_31_outputreg0_q}; + assign qDivProdExp_opA_uid94_fpDivTest_b = {1'b0, expPostRndF_uid82_fpDivTest_q}; + assign qDivProdExp_opA_uid94_fpDivTest_o = $unsigned(qDivProdExp_opA_uid94_fpDivTest_a) + $unsigned(qDivProdExp_opA_uid94_fpDivTest_b); + assign qDivProdExp_opA_uid94_fpDivTest_q = qDivProdExp_opA_uid94_fpDivTest_o[8:0]; + + // qDivProdExp_uid96_fpDivTest(SUB,95)@31 + assign qDivProdExp_uid96_fpDivTest_a = {3'b000, qDivProdExp_opA_uid94_fpDivTest_q}; + assign qDivProdExp_uid96_fpDivTest_b = {{3{qDivProdExp_opBs_uid95_fpDivTest_q[8]}}, qDivProdExp_opBs_uid95_fpDivTest_q}; + assign qDivProdExp_uid96_fpDivTest_o = $signed(qDivProdExp_uid96_fpDivTest_a) - $signed(qDivProdExp_uid96_fpDivTest_b); + assign qDivProdExp_uid96_fpDivTest_q = qDivProdExp_uid96_fpDivTest_o[10:0]; + + // qDivProdLTX_opA_uid98_fpDivTest(BITSELECT,97)@31 + assign qDivProdLTX_opA_uid98_fpDivTest_in = qDivProdExp_uid96_fpDivTest_q[7:0]; + assign qDivProdLTX_opA_uid98_fpDivTest_b = qDivProdLTX_opA_uid98_fpDivTest_in[7:0]; + + // redist6_qDivProdLTX_opA_uid98_fpDivTest_b_1(DELAY,192) + always @ (posedge clk) + begin + if (areset) + begin + redist6_qDivProdLTX_opA_uid98_fpDivTest_b_1_q <= '0; + end + else if (en == 1'b1) + begin + redist6_qDivProdLTX_opA_uid98_fpDivTest_b_1_q <= qDivProdLTX_opA_uid98_fpDivTest_b; + end + end + + // qDivProdFracHigh_uid91_fpDivTest(BITSELECT,90)@31 + assign qDivProdFracHigh_uid91_fpDivTest_in = qDivProd_uid89_fpDivTest_cma_q[47:0]; + assign qDivProdFracHigh_uid91_fpDivTest_b = qDivProdFracHigh_uid91_fpDivTest_in[47:24]; + + // qDivProdFracLow_uid92_fpDivTest(BITSELECT,91)@31 + assign qDivProdFracLow_uid92_fpDivTest_in = qDivProd_uid89_fpDivTest_cma_q[46:0]; + assign qDivProdFracLow_uid92_fpDivTest_b = qDivProdFracLow_uid92_fpDivTest_in[46:23]; + + // qDivProdFrac_uid93_fpDivTest(MUX,92)@31 + assign qDivProdFrac_uid93_fpDivTest_s = qDivProdNorm_uid90_fpDivTest_b; + always @(qDivProdFrac_uid93_fpDivTest_s or en or qDivProdFracLow_uid92_fpDivTest_b or qDivProdFracHigh_uid91_fpDivTest_b) + begin + unique case (qDivProdFrac_uid93_fpDivTest_s) + 1'b0 : qDivProdFrac_uid93_fpDivTest_q = qDivProdFracLow_uid92_fpDivTest_b; + 1'b1 : qDivProdFrac_uid93_fpDivTest_q = qDivProdFracHigh_uid91_fpDivTest_b; + default : qDivProdFrac_uid93_fpDivTest_q = 24'b0; + endcase + end + + // qDivProdFracWF_uid97_fpDivTest(BITSELECT,96)@31 + assign qDivProdFracWF_uid97_fpDivTest_b = qDivProdFrac_uid93_fpDivTest_q[23:1]; + + // redist7_qDivProdFracWF_uid97_fpDivTest_b_1(DELAY,193) + always @ (posedge clk) + begin + if (areset) + begin + redist7_qDivProdFracWF_uid97_fpDivTest_b_1_q <= '0; + end + else if (en == 1'b1) + begin + redist7_qDivProdFracWF_uid97_fpDivTest_b_1_q <= qDivProdFracWF_uid97_fpDivTest_b; + end + end + + // qDivProdLTX_opA_uid99_fpDivTest(BITJOIN,98)@32 + assign qDivProdLTX_opA_uid99_fpDivTest_q = {redist6_qDivProdLTX_opA_uid98_fpDivTest_b_1_q, redist7_qDivProdFracWF_uid97_fpDivTest_b_1_q}; + + // qDividerProdLTX_uid101_fpDivTest(COMPARE,100)@32 + assign qDividerProdLTX_uid101_fpDivTest_a = {2'b00, qDivProdLTX_opA_uid99_fpDivTest_q}; + assign qDividerProdLTX_uid101_fpDivTest_b = {2'b00, qDivProdLTX_opB_uid100_fpDivTest_q}; + assign qDividerProdLTX_uid101_fpDivTest_o = $unsigned(qDividerProdLTX_uid101_fpDivTest_a) - $unsigned(qDividerProdLTX_uid101_fpDivTest_b); + assign qDividerProdLTX_uid101_fpDivTest_c[0] = qDividerProdLTX_uid101_fpDivTest_o[32]; + + // extraUlp_uid103_fpDivTest(LOGICAL,102)@32 + 1 + assign extraUlp_uid103_fpDivTest_qi = qDividerProdLTX_uid101_fpDivTest_c & redist5_betweenFPwF_uid102_fpDivTest_b_7_q; + dspba_delay_ver #( .width(1), .depth(1), .reset_kind("SYNC"), .phase(0), .modulus(1) ) + extraUlp_uid103_fpDivTest_delay ( .xin(extraUlp_uid103_fpDivTest_qi), .xout(extraUlp_uid103_fpDivTest_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // expRPreExc_uid112_fpDivTest(MUX,111)@33 + 1 + assign expRPreExc_uid112_fpDivTest_s = extraUlp_uid103_fpDivTest_q; + always @ (posedge clk) + begin + if (areset) + begin + expRPreExc_uid112_fpDivTest_q <= 8'b0; + end + else if (en == 1'b1) + begin + unique case (expRPreExc_uid112_fpDivTest_s) + 1'b0 : expRPreExc_uid112_fpDivTest_q <= redist9_expPostRndFR_uid81_fpDivTest_b_9_q; + 1'b1 : expRPreExc_uid112_fpDivTest_q <= expFracPostRndR_uid111_fpDivTest_b; + default : expRPreExc_uid112_fpDivTest_q <= 8'b0; + endcase + end + end + + // invExpXIsMax_uid43_fpDivTest(LOGICAL,42)@25 + assign invExpXIsMax_uid43_fpDivTest_q = ~ (expXIsMax_uid38_fpDivTest_q); + + // InvExpXIsZero_uid44_fpDivTest(LOGICAL,43)@25 + assign InvExpXIsZero_uid44_fpDivTest_q = ~ (excZ_y_uid37_fpDivTest_q); + + // excR_y_uid45_fpDivTest(LOGICAL,44)@25 + assign excR_y_uid45_fpDivTest_q = InvExpXIsZero_uid44_fpDivTest_q & invExpXIsMax_uid43_fpDivTest_q; + + // excXIYR_uid127_fpDivTest(LOGICAL,126)@25 + assign excXIYR_uid127_fpDivTest_q = excI_x_uid27_fpDivTest_q & excR_y_uid45_fpDivTest_q; + + // excXIYZ_uid126_fpDivTest(LOGICAL,125)@25 + assign excXIYZ_uid126_fpDivTest_q = excI_x_uid27_fpDivTest_q & excZ_y_uid37_fpDivTest_q; + + // expRExt_uid114_fpDivTest(BITSELECT,113)@24 + assign expRExt_uid114_fpDivTest_b = expFracPostRnd_uid76_fpDivTest_q[35:25]; + + // expOvf_uid118_fpDivTest(COMPARE,117)@24 + 1 + assign expOvf_uid118_fpDivTest_a = {{2{expRExt_uid114_fpDivTest_b[10]}}, expRExt_uid114_fpDivTest_b}; + assign expOvf_uid118_fpDivTest_b = {5'b00000, cstAllOWE_uid18_fpDivTest_q}; + always @ (posedge clk) + begin + if (areset) + begin + expOvf_uid118_fpDivTest_o <= 13'b0; + end + else if (en == 1'b1) + begin + expOvf_uid118_fpDivTest_o <= $signed(expOvf_uid118_fpDivTest_a) - $signed(expOvf_uid118_fpDivTest_b); + end + end + assign expOvf_uid118_fpDivTest_n[0] = ~ (expOvf_uid118_fpDivTest_o[12]); + + // invExpXIsMax_uid29_fpDivTest(LOGICAL,28)@24 + assign invExpXIsMax_uid29_fpDivTest_q = ~ (expXIsMax_uid24_fpDivTest_q); + + // InvExpXIsZero_uid30_fpDivTest(LOGICAL,29)@24 + assign InvExpXIsZero_uid30_fpDivTest_q = ~ (excZ_x_uid23_fpDivTest_q); + + // excR_x_uid31_fpDivTest(LOGICAL,30)@24 + 1 + assign excR_x_uid31_fpDivTest_qi = InvExpXIsZero_uid30_fpDivTest_q & invExpXIsMax_uid29_fpDivTest_q; + dspba_delay_ver #( .width(1), .depth(1), .reset_kind("SYNC"), .phase(0), .modulus(1) ) + excR_x_uid31_fpDivTest_delay ( .xin(excR_x_uid31_fpDivTest_qi), .xout(excR_x_uid31_fpDivTest_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // excXRYROvf_uid125_fpDivTest(LOGICAL,124)@25 + assign excXRYROvf_uid125_fpDivTest_q = excR_x_uid31_fpDivTest_q & excR_y_uid45_fpDivTest_q & expOvf_uid118_fpDivTest_n; + + // excXRYZ_uid124_fpDivTest(LOGICAL,123)@25 + assign excXRYZ_uid124_fpDivTest_q = excR_x_uid31_fpDivTest_q & excZ_y_uid37_fpDivTest_q; + + // excRInf_uid128_fpDivTest(LOGICAL,127)@25 + assign excRInf_uid128_fpDivTest_q = excXRYZ_uid124_fpDivTest_q | excXRYROvf_uid125_fpDivTest_q | excXIYZ_uid126_fpDivTest_q | excXIYR_uid127_fpDivTest_q; + + // xRegOrZero_uid121_fpDivTest(LOGICAL,120)@25 + assign xRegOrZero_uid121_fpDivTest_q = excR_x_uid31_fpDivTest_q | redist22_excZ_x_uid23_fpDivTest_q_1_q; + + // regOrZeroOverInf_uid122_fpDivTest(LOGICAL,121)@25 + assign regOrZeroOverInf_uid122_fpDivTest_q = xRegOrZero_uid121_fpDivTest_q & excI_y_uid41_fpDivTest_q; + + // expUdf_uid115_fpDivTest(COMPARE,114)@24 + 1 + assign expUdf_uid115_fpDivTest_a = {12'b000000000000, GND_q}; + assign expUdf_uid115_fpDivTest_b = {{2{expRExt_uid114_fpDivTest_b[10]}}, expRExt_uid114_fpDivTest_b}; + always @ (posedge clk) + begin + if (areset) + begin + expUdf_uid115_fpDivTest_o <= 13'b0; + end + else if (en == 1'b1) + begin + expUdf_uid115_fpDivTest_o <= $signed(expUdf_uid115_fpDivTest_a) - $signed(expUdf_uid115_fpDivTest_b); + end + end + assign expUdf_uid115_fpDivTest_n[0] = ~ (expUdf_uid115_fpDivTest_o[12]); + + // regOverRegWithUf_uid120_fpDivTest(LOGICAL,119)@25 + assign regOverRegWithUf_uid120_fpDivTest_q = expUdf_uid115_fpDivTest_n & excR_x_uid31_fpDivTest_q & excR_y_uid45_fpDivTest_q; + + // zeroOverReg_uid119_fpDivTest(LOGICAL,118)@25 + assign zeroOverReg_uid119_fpDivTest_q = redist22_excZ_x_uid23_fpDivTest_q_1_q & excR_y_uid45_fpDivTest_q; + + // excRZero_uid123_fpDivTest(LOGICAL,122)@25 + assign excRZero_uid123_fpDivTest_q = zeroOverReg_uid119_fpDivTest_q | regOverRegWithUf_uid120_fpDivTest_q | regOrZeroOverInf_uid122_fpDivTest_q; + + // concExc_uid132_fpDivTest(BITJOIN,131)@25 + assign concExc_uid132_fpDivTest_q = {excRNaN_uid131_fpDivTest_q, excRInf_uid128_fpDivTest_q, excRZero_uid123_fpDivTest_q}; + + // excREnc_uid133_fpDivTest(LOOKUP,132)@25 + 1 + always @ (posedge clk) + begin + if (areset) + begin + excREnc_uid133_fpDivTest_q <= 2'b01; + end + else if (en == 1'b1) + begin + unique case (concExc_uid132_fpDivTest_q) + 3'b000 : excREnc_uid133_fpDivTest_q <= 2'b01; + 3'b001 : excREnc_uid133_fpDivTest_q <= 2'b00; + 3'b010 : excREnc_uid133_fpDivTest_q <= 2'b10; + 3'b011 : excREnc_uid133_fpDivTest_q <= 2'b00; + 3'b100 : excREnc_uid133_fpDivTest_q <= 2'b11; + 3'b101 : excREnc_uid133_fpDivTest_q <= 2'b00; + 3'b110 : excREnc_uid133_fpDivTest_q <= 2'b00; + 3'b111 : excREnc_uid133_fpDivTest_q <= 2'b00; + default : begin + // unreachable + excREnc_uid133_fpDivTest_q <= 2'bxx; + end + endcase + end + end + + // redist3_excREnc_uid133_fpDivTest_q_9(DELAY,189) + dspba_delay_ver #( .width(2), .depth(8), .reset_kind("SYNC"), .phase(0), .modulus(1) ) + redist3_excREnc_uid133_fpDivTest_q_9 ( .xin(excREnc_uid133_fpDivTest_q), .xout(redist3_excREnc_uid133_fpDivTest_q_9_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // expRPostExc_uid141_fpDivTest(MUX,140)@34 + assign expRPostExc_uid141_fpDivTest_s = redist3_excREnc_uid133_fpDivTest_q_9_q; + always @(expRPostExc_uid141_fpDivTest_s or en or cstAllZWE_uid20_fpDivTest_q or expRPreExc_uid112_fpDivTest_q or cstAllOWE_uid18_fpDivTest_q) + begin + unique case (expRPostExc_uid141_fpDivTest_s) + 2'b00 : expRPostExc_uid141_fpDivTest_q = cstAllZWE_uid20_fpDivTest_q; + 2'b01 : expRPostExc_uid141_fpDivTest_q = expRPreExc_uid112_fpDivTest_q; + 2'b10 : expRPostExc_uid141_fpDivTest_q = cstAllOWE_uid18_fpDivTest_q; + 2'b11 : expRPostExc_uid141_fpDivTest_q = cstAllOWE_uid18_fpDivTest_q; + default : expRPostExc_uid141_fpDivTest_q = 8'b0; + endcase + end + + // oneFracRPostExc2_uid134_fpDivTest(CONSTANT,133) + assign oneFracRPostExc2_uid134_fpDivTest_q = 23'b00000000000000000000001; + + // fracPostRndFPostUlp_uid106_fpDivTest(BITSELECT,105)@33 + assign fracPostRndFPostUlp_uid106_fpDivTest_in = fracRPreExcExt_uid105_fpDivTest_q[22:0]; + assign fracPostRndFPostUlp_uid106_fpDivTest_b = fracPostRndFPostUlp_uid106_fpDivTest_in[22:0]; + + // fracRPreExc_uid107_fpDivTest(MUX,106)@33 + 1 + assign fracRPreExc_uid107_fpDivTest_s = extraUlp_uid103_fpDivTest_q; + always @ (posedge clk) + begin + if (areset) + begin + fracRPreExc_uid107_fpDivTest_q <= 23'b0; + end + else if (en == 1'b1) + begin + unique case (fracRPreExc_uid107_fpDivTest_s) + 1'b0 : fracRPreExc_uid107_fpDivTest_q <= redist4_fracPostRndFT_uid104_fpDivTest_b_8_mem_q; + 1'b1 : fracRPreExc_uid107_fpDivTest_q <= fracPostRndFPostUlp_uid106_fpDivTest_b; + default : fracRPreExc_uid107_fpDivTest_q <= 23'b0; + endcase + end + end + + // fracRPostExc_uid137_fpDivTest(MUX,136)@34 + assign fracRPostExc_uid137_fpDivTest_s = redist3_excREnc_uid133_fpDivTest_q_9_q; + always @(fracRPostExc_uid137_fpDivTest_s or en or paddingY_uid15_fpDivTest_q or fracRPreExc_uid107_fpDivTest_q or oneFracRPostExc2_uid134_fpDivTest_q) + begin + unique case (fracRPostExc_uid137_fpDivTest_s) + 2'b00 : fracRPostExc_uid137_fpDivTest_q = paddingY_uid15_fpDivTest_q; + 2'b01 : fracRPostExc_uid137_fpDivTest_q = fracRPreExc_uid107_fpDivTest_q; + 2'b10 : fracRPostExc_uid137_fpDivTest_q = paddingY_uid15_fpDivTest_q; + 2'b11 : fracRPostExc_uid137_fpDivTest_q = oneFracRPostExc2_uid134_fpDivTest_q; + default : fracRPostExc_uid137_fpDivTest_q = 23'b0; + endcase + end + + // divR_uid144_fpDivTest(BITJOIN,143)@34 + assign divR_uid144_fpDivTest_q = {redist2_sRPostExc_uid143_fpDivTest_q_9_q, expRPostExc_uid141_fpDivTest_q, fracRPostExc_uid137_fpDivTest_q}; + + // xOut(GPOUT,4)@34 + assign q = divR_uid144_fpDivTest_q; + +endmodule diff --git a/hw/rtl/fp_cores/altera/stratix10/acl_fdiv_memoryC0_uid146_invTables_lutmem.hex b/hw/rtl/fp_cores/altera/stratix10/acl_fdiv_memoryC0_uid146_invTables_lutmem.hex new file mode 100644 index 00000000..915d30cb --- /dev/null +++ b/hw/rtl/fp_cores/altera/stratix10/acl_fdiv_memoryC0_uid146_invTables_lutmem.hex @@ -0,0 +1,514 @@ +:020000040000FA +:0400000040000004B8 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+:0201EE00021BF2 +:0201EF00021BF1 +:0201F0000218F3 +:0201F1000217F3 +:0201F2000216F3 +:0201F3000214F4 +:0201F4000212F5 +:0201F5000211F5 +:0201F600020FF6 +:0201F700020EF6 +:0201F800020CF7 +:0201F900020CF6 +:0201FA00020AF7 +:0201FB000207F9 +:0201FC000206F9 +:0201FD000205F9 +:0201FE000204F9 +:0201FF0001FFFE +:00000001ff diff --git a/hw/rtl/fp_cores/altera/stratix10/acl_fmadd.sv b/hw/rtl/fp_cores/altera/stratix10/acl_fmadd.sv new file mode 100644 index 00000000..c081092f --- /dev/null +++ b/hw/rtl/fp_cores/altera/stratix10/acl_fmadd.sv @@ -0,0 +1,74 @@ +// ------------------------------------------------------------------------- +// High Level Design Compiler for Intel(R) FPGAs Version 18.1 (Release Build #277) +// Quartus Prime development tool and MATLAB/Simulink Interface +// +// Legal Notice: Copyright 2019 Intel Corporation. All rights reserved. +// Your use of Intel Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly +// subject to the terms and conditions of the Intel FPGA Software License +// Agreement, Intel MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for +// the sole purpose of programming logic devices manufactured by Intel +// and sold by Intel or its authorized distributors. Please refer to the +// applicable agreement for further details. +// --------------------------------------------------------------------------- + +// SystemVerilog created from acl_fmadd +// SystemVerilog created on Sun Dec 27 09:48:58 2020 + + +(* altera_attribute = "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410; -name MESSAGE_DISABLE 113007; -name MESSAGE_DISABLE 10958" *) +module acl_fmadd ( + input wire [31:0] a, + input wire [31:0] b, + input wire [31:0] c, + input wire [0:0] en, + output wire [31:0] q, + input wire clk, + input wire areset + ); + + wire fpMultAddTest_impl_reset0; + wire fpMultAddTest_impl_ena0; + wire [31:0] fpMultAddTest_impl_ax0; + wire [31:0] fpMultAddTest_impl_ay0; + wire [31:0] fpMultAddTest_impl_az0; + wire [31:0] fpMultAddTest_impl_q0; + + + // fpMultAddTest_impl(FPCOLUMN,5)@0 + // out q0@4 + assign fpMultAddTest_impl_ax0 = c; + assign fpMultAddTest_impl_ay0 = b; + assign fpMultAddTest_impl_az0 = a; + assign fpMultAddTest_impl_reset0 = areset; + assign fpMultAddTest_impl_ena0 = en[0] | fpMultAddTest_impl_reset0; + fourteennm_fp_mac #( + .operation_mode("sp_mult_add"), + .ax_clock("0"), + .ay_clock("0"), + .az_clock("0"), + .mult_2nd_pipeline_clock("0"), + .adder_input_clock("0"), + .ax_chainin_pl_clock("0"), + .output_clock("0"), + .clear_type("sclr") + ) fpMultAddTest_impl_DSP0 ( + .clk({1'b0,1'b0,clk}), + .ena({ 1'b0, 1'b0, fpMultAddTest_impl_ena0 }), + .clr({ fpMultAddTest_impl_reset0, fpMultAddTest_impl_reset0 }), + .ax(fpMultAddTest_impl_ax0), + .ay(fpMultAddTest_impl_ay0), + .az(fpMultAddTest_impl_az0), + .resulta(fpMultAddTest_impl_q0), + .accumulate(), + .chainin(), + .chainout() + ); + + // xOut(GPOUT,4)@4 + assign q = fpMultAddTest_impl_q0; + +endmodule diff --git a/hw/rtl/fp_cores/altera/stratix10/acl_fmsub.sv b/hw/rtl/fp_cores/altera/stratix10/acl_fmsub.sv new file mode 100644 index 00000000..0c78f71e --- /dev/null +++ b/hw/rtl/fp_cores/altera/stratix10/acl_fmsub.sv @@ -0,0 +1,75 @@ +// ------------------------------------------------------------------------- +// High Level Design Compiler for Intel(R) FPGAs Version 18.1 (Release Build #277) +// Quartus Prime development tool and MATLAB/Simulink Interface +// +// Legal Notice: Copyright 2019 Intel Corporation. All rights reserved. +// Your use of Intel Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly +// subject to the terms and conditions of the Intel FPGA Software License +// Agreement, Intel MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for +// the sole purpose of programming logic devices manufactured by Intel +// and sold by Intel or its authorized distributors. Please refer to the +// applicable agreement for further details. +// --------------------------------------------------------------------------- + +// SystemVerilog created from acl_fmsub +// SystemVerilog created on Sun Dec 27 07:06:39 2020 + + +(* altera_attribute = "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410; -name MESSAGE_DISABLE 113007; -name MESSAGE_DISABLE 10958" *) +module acl_fmsub ( + input wire [31:0] a, + input wire [31:0] b, + input wire [31:0] c, + input wire [0:0] en, + output wire [31:0] q, + input wire clk, + input wire areset + ); + + wire fpMultAddTest_impl_reset0; + wire fpMultAddTest_impl_ena0; + wire [31:0] fpMultAddTest_impl_ax0; + wire [31:0] fpMultAddTest_impl_ay0; + wire [31:0] fpMultAddTest_impl_az0; + wire [31:0] fpMultAddTest_impl_q0; + + + // fpMultAddTest_impl(FPCOLUMN,5)@0 + // out q0@4 + assign fpMultAddTest_impl_ax0 = c; + assign fpMultAddTest_impl_ay0 = b; + assign fpMultAddTest_impl_az0 = a; + assign fpMultAddTest_impl_reset0 = areset; + assign fpMultAddTest_impl_ena0 = en[0] | fpMultAddTest_impl_reset0; + fourteennm_fp_mac #( + .operation_mode("sp_mult_add"), + .adder_subtract("true"), + .ax_clock("0"), + .ay_clock("0"), + .az_clock("0"), + .mult_2nd_pipeline_clock("0"), + .adder_input_clock("0"), + .ax_chainin_pl_clock("0"), + .output_clock("0"), + .clear_type("sclr") + ) fpMultAddTest_impl_DSP0 ( + .clk({1'b0,1'b0,clk}), + .ena({ 1'b0, 1'b0, fpMultAddTest_impl_ena0 }), + .clr({ fpMultAddTest_impl_reset0, fpMultAddTest_impl_reset0 }), + .ax(fpMultAddTest_impl_ax0), + .ay(fpMultAddTest_impl_ay0), + .az(fpMultAddTest_impl_az0), + .resulta(fpMultAddTest_impl_q0), + .accumulate(), + .chainin(), + .chainout() + ); + + // xOut(GPOUT,4)@4 + assign q = fpMultAddTest_impl_q0; + +endmodule diff --git a/hw/rtl/fp_cores/altera/stratix10/acl_fmul.sv b/hw/rtl/fp_cores/altera/stratix10/acl_fmul.sv new file mode 100644 index 00000000..fc45decd --- /dev/null +++ b/hw/rtl/fp_cores/altera/stratix10/acl_fmul.sv @@ -0,0 +1,68 @@ +// ------------------------------------------------------------------------- +// High Level Design Compiler for Intel(R) FPGAs Version 18.1 (Release Build #277) +// Quartus Prime development tool and MATLAB/Simulink Interface +// +// Legal Notice: Copyright 2019 Intel Corporation. All rights reserved. +// Your use of Intel Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly +// subject to the terms and conditions of the Intel FPGA Software License +// Agreement, Intel MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for +// the sole purpose of programming logic devices manufactured by Intel +// and sold by Intel or its authorized distributors. Please refer to the +// applicable agreement for further details. +// --------------------------------------------------------------------------- + +// SystemVerilog created from acl_fmul +// SystemVerilog created on Sun Dec 27 09:48:57 2020 + + +(* altera_attribute = "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410; -name MESSAGE_DISABLE 113007; -name MESSAGE_DISABLE 10958" *) +module acl_fmul ( + input wire [31:0] a, + input wire [31:0] b, + input wire [0:0] en, + output wire [31:0] q, + input wire clk, + input wire areset + ); + + wire fpMulTest_impl_reset0; + wire fpMulTest_impl_ena0; + wire [31:0] fpMulTest_impl_ay0; + wire [31:0] fpMulTest_impl_az0; + wire [31:0] fpMulTest_impl_q0; + + + // fpMulTest_impl(FPCOLUMN,5)@0 + // out q0@3 + assign fpMulTest_impl_ay0 = b; + assign fpMulTest_impl_az0 = a; + assign fpMulTest_impl_reset0 = areset; + assign fpMulTest_impl_ena0 = en[0] | fpMulTest_impl_reset0; + fourteennm_fp_mac #( + .operation_mode("sp_mult"), + .ay_clock("0"), + .az_clock("0"), + .mult_2nd_pipeline_clock("0"), + .output_clock("0"), + .clear_type("sclr") + ) fpMulTest_impl_DSP0 ( + .clk({1'b0,1'b0,clk}), + .ena({ 1'b0, 1'b0, fpMulTest_impl_ena0 }), + .clr({ fpMulTest_impl_reset0, fpMulTest_impl_reset0 }), + .ay(fpMulTest_impl_ay0), + .az(fpMulTest_impl_az0), + .resulta(fpMulTest_impl_q0), + .accumulate(), + .ax(), + .chainin(), + .chainout() + ); + + // xOut(GPOUT,4)@3 + assign q = fpMulTest_impl_q0; + +endmodule diff --git a/hw/rtl/fp_cores/altera/stratix10/acl_fsqrt.sv b/hw/rtl/fp_cores/altera/stratix10/acl_fsqrt.sv new file mode 100644 index 00000000..738d4c81 --- /dev/null +++ b/hw/rtl/fp_cores/altera/stratix10/acl_fsqrt.sv @@ -0,0 +1,2116 @@ +// ------------------------------------------------------------------------- +// High Level Design Compiler for Intel(R) FPGAs Version 18.1 (Release Build #277) +// Quartus Prime development tool and MATLAB/Simulink Interface +// +// Legal Notice: Copyright 2019 Intel Corporation. All rights reserved. +// Your use of Intel Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly +// subject to the terms and conditions of the Intel FPGA Software License +// Agreement, Intel MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for +// the sole purpose of programming logic devices manufactured by Intel +// and sold by Intel or its authorized distributors. Please refer to the +// applicable agreement for further details. +// --------------------------------------------------------------------------- + +// SystemVerilog created from acl_fsqrt +// SystemVerilog created on Sun Dec 27 09:48:58 2020 + + +(* altera_attribute = "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410; -name MESSAGE_DISABLE 113007; -name MESSAGE_DISABLE 10958" *) +module acl_fsqrt ( + input wire [31:0] a, + input wire [0:0] en, + output wire [31:0] q, + input wire clk, + input wire areset + ); + + wire [0:0] GND_q; + wire [0:0] VCC_q; + wire [7:0] expX_uid6_fpSqrtTest_b; + wire [0:0] signX_uid7_fpSqrtTest_b; + wire [7:0] cstAllOWE_uid8_fpSqrtTest_q; + wire [22:0] cstZeroWF_uid9_fpSqrtTest_q; + wire [7:0] cstAllZWE_uid10_fpSqrtTest_q; + wire [22:0] frac_x_uid12_fpSqrtTest_b; + wire [0:0] excZ_x_uid13_fpSqrtTest_qi; + reg [0:0] excZ_x_uid13_fpSqrtTest_q; + wire [0:0] expXIsMax_uid14_fpSqrtTest_qi; + reg [0:0] expXIsMax_uid14_fpSqrtTest_q; + wire [0:0] fracXIsZero_uid15_fpSqrtTest_qi; + reg [0:0] fracXIsZero_uid15_fpSqrtTest_q; + wire [0:0] fracXIsNotZero_uid16_fpSqrtTest_q; + wire [0:0] excI_x_uid17_fpSqrtTest_q; + wire [0:0] excN_x_uid18_fpSqrtTest_q; + wire [0:0] invExpXIsMax_uid19_fpSqrtTest_q; + wire [0:0] InvExpXIsZero_uid20_fpSqrtTest_q; + wire [0:0] excR_x_uid21_fpSqrtTest_q; + wire [7:0] sBias_uid22_fpSqrtTest_q; + wire [8:0] expEvenSig_uid24_fpSqrtTest_a; + wire [8:0] expEvenSig_uid24_fpSqrtTest_b; + logic [8:0] expEvenSig_uid24_fpSqrtTest_o; + wire [8:0] expEvenSig_uid24_fpSqrtTest_q; + wire [7:0] expREven_uid25_fpSqrtTest_b; + wire [7:0] sBiasM1_uid26_fpSqrtTest_q; + wire [8:0] expOddSig_uid27_fpSqrtTest_a; + wire [8:0] expOddSig_uid27_fpSqrtTest_b; + logic [8:0] expOddSig_uid27_fpSqrtTest_o; + wire [8:0] expOddSig_uid27_fpSqrtTest_q; + wire [7:0] expROdd_uid28_fpSqrtTest_b; + wire [0:0] expX0PS_uid29_fpSqrtTest_in; + wire [0:0] expX0PS_uid29_fpSqrtTest_b; + wire [0:0] expOddSelect_uid30_fpSqrtTest_q; + wire [0:0] expRMux_uid31_fpSqrtTest_s; + reg [7:0] expRMux_uid31_fpSqrtTest_q; + wire [23:0] addrFull_uid33_fpSqrtTest_q; + wire [7:0] yAddr_uid35_fpSqrtTest_b; + wire [15:0] yForPe_uid36_fpSqrtTest_in; + wire [15:0] yForPe_uid36_fpSqrtTest_b; + wire [30:0] expIncPEOnly_uid38_fpSqrtTest_in; + wire [0:0] expIncPEOnly_uid38_fpSqrtTest_b; + wire [28:0] fracRPreCR_uid39_fpSqrtTest_in; + wire [23:0] fracRPreCR_uid39_fpSqrtTest_b; + wire [24:0] fracPaddingOne_uid41_fpSqrtTest_q; + wire [23:0] oFracX_uid44_fpSqrtTest_q; + wire [24:0] oFracXZ_mergedSignalTM_uid47_fpSqrtTest_q; + wire [24:0] oFracXSignExt_mergedSignalTM_uid52_fpSqrtTest_q; + wire [0:0] normalizedXForComp_uid54_fpSqrtTest_s; + reg [24:0] normalizedXForComp_uid54_fpSqrtTest_q; + wire [24:0] paddingY_uid55_fpSqrtTest_q; + wire [49:0] updatedY_uid56_fpSqrtTest_q; + wire [51:0] squaredResultGTEIn_uid55_fpSqrtTest_a; + wire [51:0] squaredResultGTEIn_uid55_fpSqrtTest_b; + logic [51:0] squaredResultGTEIn_uid55_fpSqrtTest_o; + wire [0:0] squaredResultGTEIn_uid55_fpSqrtTest_n; + wire [0:0] pLTOne_uid58_fpSqrtTest_q; + wire [24:0] fxpSqrtResPostUpdateE_uid60_fpSqrtTest_a; + wire [24:0] fxpSqrtResPostUpdateE_uid60_fpSqrtTest_b; + logic [24:0] fxpSqrtResPostUpdateE_uid60_fpSqrtTest_o; + wire [24:0] fxpSqrtResPostUpdateE_uid60_fpSqrtTest_q; + wire [0:0] fracPENotOne_uid62_fpSqrtTest_q; + wire [0:0] fracPENotOneAndCRRoundsExp_uid63_fpSqrtTest_q; + wire [0:0] expInc_uid64_fpSqrtTest_qi; + reg [0:0] expInc_uid64_fpSqrtTest_q; + wire [8:0] expR_uid66_fpSqrtTest_a; + wire [8:0] expR_uid66_fpSqrtTest_b; + logic [8:0] expR_uid66_fpSqrtTest_o; + wire [8:0] expR_uid66_fpSqrtTest_q; + wire [0:0] invSignX_uid67_fpSqrtTest_q; + wire [0:0] inInfAndNotNeg_uid68_fpSqrtTest_q; + wire [0:0] minReg_uid69_fpSqrtTest_q; + wire [0:0] minInf_uid70_fpSqrtTest_q; + wire [0:0] excRNaN_uid71_fpSqrtTest_q; + wire [2:0] excConc_uid72_fpSqrtTest_q; + wire [3:0] fracSelIn_uid73_fpSqrtTest_q; + reg [1:0] fracSel_uid74_fpSqrtTest_q; + wire [7:0] expRR_uid77_fpSqrtTest_in; + wire [7:0] expRR_uid77_fpSqrtTest_b; + wire [1:0] expRPostExc_uid79_fpSqrtTest_s; + reg [7:0] expRPostExc_uid79_fpSqrtTest_q; + wire [22:0] fracNaN_uid80_fpSqrtTest_q; + wire [1:0] fracRPostExc_uid84_fpSqrtTest_s; + reg [22:0] fracRPostExc_uid84_fpSqrtTest_q; + wire [0:0] negZero_uid85_fpSqrtTest_qi; + reg [0:0] negZero_uid85_fpSqrtTest_q; + wire [31:0] RSqrt_uid86_fpSqrtTest_q; + wire [11:0] yT1_uid100_invPolyEval_b; + wire [0:0] lowRangeB_uid102_invPolyEval_in; + wire [0:0] lowRangeB_uid102_invPolyEval_b; + wire [11:0] highBBits_uid103_invPolyEval_b; + wire [21:0] s1sumAHighB_uid104_invPolyEval_a; + wire [21:0] s1sumAHighB_uid104_invPolyEval_b; + logic [21:0] s1sumAHighB_uid104_invPolyEval_o; + wire [21:0] s1sumAHighB_uid104_invPolyEval_q; + wire [22:0] s1_uid105_invPolyEval_q; + wire [1:0] lowRangeB_uid108_invPolyEval_in; + wire [1:0] lowRangeB_uid108_invPolyEval_b; + wire [21:0] highBBits_uid109_invPolyEval_b; + wire [29:0] s2sumAHighB_uid110_invPolyEval_a; + wire [29:0] s2sumAHighB_uid110_invPolyEval_b; + logic [29:0] s2sumAHighB_uid110_invPolyEval_o; + wire [29:0] s2sumAHighB_uid110_invPolyEval_q; + wire [31:0] s2_uid111_invPolyEval_q; + wire [12:0] osig_uid114_pT1_uid101_invPolyEval_b; + wire [23:0] osig_uid117_pT2_uid107_invPolyEval_b; + wire memoryC0_uid88_sqrtTables_lutmem_reset0; + wire [28:0] memoryC0_uid88_sqrtTables_lutmem_ia; + wire [7:0] memoryC0_uid88_sqrtTables_lutmem_aa; + wire [7:0] memoryC0_uid88_sqrtTables_lutmem_ab; + wire [28:0] memoryC0_uid88_sqrtTables_lutmem_ir; + wire [28:0] memoryC0_uid88_sqrtTables_lutmem_r; + wire memoryC0_uid88_sqrtTables_lutmem_enaOr_rst; + wire memoryC1_uid91_sqrtTables_lutmem_reset0; + wire [20:0] memoryC1_uid91_sqrtTables_lutmem_ia; + wire [7:0] memoryC1_uid91_sqrtTables_lutmem_aa; + wire [7:0] memoryC1_uid91_sqrtTables_lutmem_ab; + wire [20:0] memoryC1_uid91_sqrtTables_lutmem_ir; + wire [20:0] memoryC1_uid91_sqrtTables_lutmem_r; + wire memoryC1_uid91_sqrtTables_lutmem_enaOr_rst; + wire memoryC2_uid94_sqrtTables_lutmem_reset0; + wire [11:0] memoryC2_uid94_sqrtTables_lutmem_ia; + wire [7:0] memoryC2_uid94_sqrtTables_lutmem_aa; + wire [7:0] memoryC2_uid94_sqrtTables_lutmem_ab; + wire [11:0] memoryC2_uid94_sqrtTables_lutmem_ir; + wire [11:0] memoryC2_uid94_sqrtTables_lutmem_r; + wire memoryC2_uid94_sqrtTables_lutmem_enaOr_rst; + wire squaredResult_uid42_fpSqrtTest_cma_reset; + (* preserve_syn_only *) reg [24:0] squaredResult_uid42_fpSqrtTest_cma_ah [0:0]; + (* preserve_syn_only *) reg [24:0] squaredResult_uid42_fpSqrtTest_cma_ch [0:0]; + wire [24:0] squaredResult_uid42_fpSqrtTest_cma_a0; + wire [24:0] squaredResult_uid42_fpSqrtTest_cma_c0; + wire [49:0] squaredResult_uid42_fpSqrtTest_cma_s0; + wire [49:0] squaredResult_uid42_fpSqrtTest_cma_qq; + reg [49:0] squaredResult_uid42_fpSqrtTest_cma_q; + wire squaredResult_uid42_fpSqrtTest_cma_ena0; + wire squaredResult_uid42_fpSqrtTest_cma_ena1; + wire squaredResult_uid42_fpSqrtTest_cma_ena2; + wire prodXY_uid113_pT1_uid101_invPolyEval_cma_reset; + (* preserve_syn_only *) reg [11:0] prodXY_uid113_pT1_uid101_invPolyEval_cma_ah [0:0]; + (* preserve_syn_only *) reg signed [11:0] prodXY_uid113_pT1_uid101_invPolyEval_cma_ch [0:0]; + wire [11:0] prodXY_uid113_pT1_uid101_invPolyEval_cma_a0; + wire [11:0] prodXY_uid113_pT1_uid101_invPolyEval_cma_c0; + wire [23:0] prodXY_uid113_pT1_uid101_invPolyEval_cma_s0; + wire [23:0] prodXY_uid113_pT1_uid101_invPolyEval_cma_qq; + reg [23:0] prodXY_uid113_pT1_uid101_invPolyEval_cma_q; + wire prodXY_uid113_pT1_uid101_invPolyEval_cma_ena0; + wire prodXY_uid113_pT1_uid101_invPolyEval_cma_ena1; + wire prodXY_uid113_pT1_uid101_invPolyEval_cma_ena2; + wire prodXY_uid116_pT2_uid107_invPolyEval_cma_reset; + (* preserve_syn_only *) reg [15:0] prodXY_uid116_pT2_uid107_invPolyEval_cma_ah [0:0]; + (* preserve_syn_only *) reg signed [22:0] prodXY_uid116_pT2_uid107_invPolyEval_cma_ch [0:0]; + wire [15:0] prodXY_uid116_pT2_uid107_invPolyEval_cma_a0; + wire [22:0] prodXY_uid116_pT2_uid107_invPolyEval_cma_c0; + wire [38:0] prodXY_uid116_pT2_uid107_invPolyEval_cma_s0; + wire [38:0] prodXY_uid116_pT2_uid107_invPolyEval_cma_qq; + reg [38:0] prodXY_uid116_pT2_uid107_invPolyEval_cma_q; + wire prodXY_uid116_pT2_uid107_invPolyEval_cma_ena0; + wire prodXY_uid116_pT2_uid107_invPolyEval_cma_ena1; + wire prodXY_uid116_pT2_uid107_invPolyEval_cma_ena2; + wire [0:0] expUpdateCRU_uid61_fpSqrtTest_merged_bit_select_b; + wire [22:0] expUpdateCRU_uid61_fpSqrtTest_merged_bit_select_c; + reg [22:0] redist0_expUpdateCRU_uid61_fpSqrtTest_merged_bit_select_c_1_q; + reg [11:0] redist1_memoryC2_uid94_sqrtTables_lutmem_r_1_q; + reg [0:0] redist2_lowRangeB_uid102_invPolyEval_b_1_q; + reg [23:0] redist3_fracRPreCR_uid39_fpSqrtTest_b_1_q; + reg [0:0] redist5_expIncPEOnly_uid38_fpSqrtTest_b_8_q; + reg [7:0] redist9_expRMux_uid31_fpSqrtTest_q_2_q; + reg [0:0] redist10_expOddSelect_uid30_fpSqrtTest_q_23_q; + reg [22:0] redist11_frac_x_uid12_fpSqrtTest_b_3_q; + reg [22:0] redist11_frac_x_uid12_fpSqrtTest_b_3_delay_0; + reg [22:0] redist11_frac_x_uid12_fpSqrtTest_b_3_delay_1; + reg [0:0] redist13_signX_uid7_fpSqrtTest_b_24_q; + wire redist4_fracRPreCR_uid39_fpSqrtTest_b_8_mem_reset0; + wire [23:0] redist4_fracRPreCR_uid39_fpSqrtTest_b_8_mem_ia; + wire [2:0] redist4_fracRPreCR_uid39_fpSqrtTest_b_8_mem_aa; + wire [2:0] redist4_fracRPreCR_uid39_fpSqrtTest_b_8_mem_ab; + wire [23:0] redist4_fracRPreCR_uid39_fpSqrtTest_b_8_mem_iq; + wire [23:0] redist4_fracRPreCR_uid39_fpSqrtTest_b_8_mem_q; + wire redist4_fracRPreCR_uid39_fpSqrtTest_b_8_mem_enaOr_rst; + wire [2:0] redist4_fracRPreCR_uid39_fpSqrtTest_b_8_rdcnt_q; + (* preserve_syn_only *) reg [2:0] redist4_fracRPreCR_uid39_fpSqrtTest_b_8_rdcnt_i; + (* preserve_syn_only *) reg redist4_fracRPreCR_uid39_fpSqrtTest_b_8_rdcnt_eq; + wire [0:0] redist4_fracRPreCR_uid39_fpSqrtTest_b_8_rdmux_s; + reg [2:0] redist4_fracRPreCR_uid39_fpSqrtTest_b_8_rdmux_q; + reg [2:0] redist4_fracRPreCR_uid39_fpSqrtTest_b_8_wraddr_q; + wire [3:0] redist4_fracRPreCR_uid39_fpSqrtTest_b_8_mem_last_q; + wire [3:0] redist4_fracRPreCR_uid39_fpSqrtTest_b_8_cmp_b; + wire [0:0] redist4_fracRPreCR_uid39_fpSqrtTest_b_8_cmp_q; + reg [0:0] redist4_fracRPreCR_uid39_fpSqrtTest_b_8_cmpReg_q; + wire [0:0] redist4_fracRPreCR_uid39_fpSqrtTest_b_8_notEnable_q; + wire [0:0] redist4_fracRPreCR_uid39_fpSqrtTest_b_8_nor_q; + (* preserve_syn_only *) reg [0:0] redist4_fracRPreCR_uid39_fpSqrtTest_b_8_sticky_ena_q; + wire [0:0] redist4_fracRPreCR_uid39_fpSqrtTest_b_8_enaAnd_q; + reg [15:0] redist6_yForPe_uid36_fpSqrtTest_b_7_outputreg0_q; + wire redist6_yForPe_uid36_fpSqrtTest_b_7_mem_reset0; + wire [15:0] redist6_yForPe_uid36_fpSqrtTest_b_7_mem_ia; + wire [2:0] redist6_yForPe_uid36_fpSqrtTest_b_7_mem_aa; + wire [2:0] redist6_yForPe_uid36_fpSqrtTest_b_7_mem_ab; + wire [15:0] redist6_yForPe_uid36_fpSqrtTest_b_7_mem_iq; + wire [15:0] redist6_yForPe_uid36_fpSqrtTest_b_7_mem_q; + wire redist6_yForPe_uid36_fpSqrtTest_b_7_mem_enaOr_rst; + wire [2:0] redist6_yForPe_uid36_fpSqrtTest_b_7_rdcnt_q; + (* preserve_syn_only *) reg [2:0] redist6_yForPe_uid36_fpSqrtTest_b_7_rdcnt_i; + (* preserve_syn_only *) reg redist6_yForPe_uid36_fpSqrtTest_b_7_rdcnt_eq; + wire [0:0] redist6_yForPe_uid36_fpSqrtTest_b_7_rdmux_s; + reg [2:0] redist6_yForPe_uid36_fpSqrtTest_b_7_rdmux_q; + reg [2:0] redist6_yForPe_uid36_fpSqrtTest_b_7_wraddr_q; + wire [2:0] redist6_yForPe_uid36_fpSqrtTest_b_7_mem_last_q; + wire [0:0] redist6_yForPe_uid36_fpSqrtTest_b_7_cmp_q; + reg [0:0] redist6_yForPe_uid36_fpSqrtTest_b_7_cmpReg_q; + wire [0:0] redist6_yForPe_uid36_fpSqrtTest_b_7_notEnable_q; + wire [0:0] redist6_yForPe_uid36_fpSqrtTest_b_7_nor_q; + (* preserve_syn_only *) reg [0:0] redist6_yForPe_uid36_fpSqrtTest_b_7_sticky_ena_q; + wire [0:0] redist6_yForPe_uid36_fpSqrtTest_b_7_enaAnd_q; + reg [7:0] redist7_yAddr_uid35_fpSqrtTest_b_7_outputreg0_q; + wire redist7_yAddr_uid35_fpSqrtTest_b_7_mem_reset0; + wire [7:0] redist7_yAddr_uid35_fpSqrtTest_b_7_mem_ia; + wire [2:0] redist7_yAddr_uid35_fpSqrtTest_b_7_mem_aa; + wire [2:0] redist7_yAddr_uid35_fpSqrtTest_b_7_mem_ab; + wire [7:0] redist7_yAddr_uid35_fpSqrtTest_b_7_mem_iq; + wire [7:0] redist7_yAddr_uid35_fpSqrtTest_b_7_mem_q; + wire redist7_yAddr_uid35_fpSqrtTest_b_7_mem_enaOr_rst; + wire [2:0] redist7_yAddr_uid35_fpSqrtTest_b_7_rdcnt_q; + (* preserve_syn_only *) reg [2:0] redist7_yAddr_uid35_fpSqrtTest_b_7_rdcnt_i; + (* preserve_syn_only *) reg redist7_yAddr_uid35_fpSqrtTest_b_7_rdcnt_eq; + wire [0:0] redist7_yAddr_uid35_fpSqrtTest_b_7_rdmux_s; + reg [2:0] redist7_yAddr_uid35_fpSqrtTest_b_7_rdmux_q; + reg [2:0] redist7_yAddr_uid35_fpSqrtTest_b_7_wraddr_q; + wire [2:0] redist7_yAddr_uid35_fpSqrtTest_b_7_mem_last_q; + wire [0:0] redist7_yAddr_uid35_fpSqrtTest_b_7_cmp_q; + reg [0:0] redist7_yAddr_uid35_fpSqrtTest_b_7_cmpReg_q; + wire [0:0] redist7_yAddr_uid35_fpSqrtTest_b_7_notEnable_q; + wire [0:0] redist7_yAddr_uid35_fpSqrtTest_b_7_nor_q; + (* preserve_syn_only *) reg [0:0] redist7_yAddr_uid35_fpSqrtTest_b_7_sticky_ena_q; + wire [0:0] redist7_yAddr_uid35_fpSqrtTest_b_7_enaAnd_q; + reg [7:0] redist8_yAddr_uid35_fpSqrtTest_b_14_outputreg0_q; + wire redist8_yAddr_uid35_fpSqrtTest_b_14_mem_reset0; + wire [7:0] redist8_yAddr_uid35_fpSqrtTest_b_14_mem_ia; + wire [2:0] redist8_yAddr_uid35_fpSqrtTest_b_14_mem_aa; + wire [2:0] redist8_yAddr_uid35_fpSqrtTest_b_14_mem_ab; + wire [7:0] redist8_yAddr_uid35_fpSqrtTest_b_14_mem_iq; + wire [7:0] redist8_yAddr_uid35_fpSqrtTest_b_14_mem_q; + wire redist8_yAddr_uid35_fpSqrtTest_b_14_mem_enaOr_rst; + wire [2:0] redist8_yAddr_uid35_fpSqrtTest_b_14_rdcnt_q; + (* preserve_syn_only *) reg [2:0] redist8_yAddr_uid35_fpSqrtTest_b_14_rdcnt_i; + (* preserve_syn_only *) reg redist8_yAddr_uid35_fpSqrtTest_b_14_rdcnt_eq; + wire [0:0] redist8_yAddr_uid35_fpSqrtTest_b_14_rdmux_s; + reg [2:0] redist8_yAddr_uid35_fpSqrtTest_b_14_rdmux_q; + reg [2:0] redist8_yAddr_uid35_fpSqrtTest_b_14_wraddr_q; + wire [2:0] redist8_yAddr_uid35_fpSqrtTest_b_14_mem_last_q; + wire [0:0] redist8_yAddr_uid35_fpSqrtTest_b_14_cmp_q; + reg [0:0] redist8_yAddr_uid35_fpSqrtTest_b_14_cmpReg_q; + wire [0:0] redist8_yAddr_uid35_fpSqrtTest_b_14_notEnable_q; + wire [0:0] redist8_yAddr_uid35_fpSqrtTest_b_14_nor_q; + (* preserve_syn_only *) reg [0:0] redist8_yAddr_uid35_fpSqrtTest_b_14_sticky_ena_q; + wire [0:0] redist8_yAddr_uid35_fpSqrtTest_b_14_enaAnd_q; + wire redist12_frac_x_uid12_fpSqrtTest_b_23_mem_reset0; + wire [22:0] redist12_frac_x_uid12_fpSqrtTest_b_23_mem_ia; + wire [4:0] redist12_frac_x_uid12_fpSqrtTest_b_23_mem_aa; + wire [4:0] redist12_frac_x_uid12_fpSqrtTest_b_23_mem_ab; + wire [22:0] redist12_frac_x_uid12_fpSqrtTest_b_23_mem_iq; + wire [22:0] redist12_frac_x_uid12_fpSqrtTest_b_23_mem_q; + wire redist12_frac_x_uid12_fpSqrtTest_b_23_mem_enaOr_rst; + wire [4:0] redist12_frac_x_uid12_fpSqrtTest_b_23_rdcnt_q; + (* preserve_syn_only *) reg [4:0] redist12_frac_x_uid12_fpSqrtTest_b_23_rdcnt_i; + (* preserve_syn_only *) reg redist12_frac_x_uid12_fpSqrtTest_b_23_rdcnt_eq; + wire [0:0] redist12_frac_x_uid12_fpSqrtTest_b_23_rdmux_s; + reg [4:0] redist12_frac_x_uid12_fpSqrtTest_b_23_rdmux_q; + reg [4:0] redist12_frac_x_uid12_fpSqrtTest_b_23_wraddr_q; + wire [5:0] redist12_frac_x_uid12_fpSqrtTest_b_23_mem_last_q; + wire [5:0] redist12_frac_x_uid12_fpSqrtTest_b_23_cmp_b; + wire [0:0] redist12_frac_x_uid12_fpSqrtTest_b_23_cmp_q; + reg [0:0] redist12_frac_x_uid12_fpSqrtTest_b_23_cmpReg_q; + wire [0:0] redist12_frac_x_uid12_fpSqrtTest_b_23_notEnable_q; + wire [0:0] redist12_frac_x_uid12_fpSqrtTest_b_23_nor_q; + (* preserve_syn_only *) reg [0:0] redist12_frac_x_uid12_fpSqrtTest_b_23_sticky_ena_q; + wire [0:0] redist12_frac_x_uid12_fpSqrtTest_b_23_enaAnd_q; + wire redist14_expX_uid6_fpSqrtTest_b_23_mem_reset0; + wire [7:0] redist14_expX_uid6_fpSqrtTest_b_23_mem_ia; + wire [4:0] redist14_expX_uid6_fpSqrtTest_b_23_mem_aa; + wire [4:0] redist14_expX_uid6_fpSqrtTest_b_23_mem_ab; + wire [7:0] redist14_expX_uid6_fpSqrtTest_b_23_mem_iq; + wire [7:0] redist14_expX_uid6_fpSqrtTest_b_23_mem_q; + wire redist14_expX_uid6_fpSqrtTest_b_23_mem_enaOr_rst; + wire [4:0] redist14_expX_uid6_fpSqrtTest_b_23_rdcnt_q; + (* preserve_syn_only *) reg [4:0] redist14_expX_uid6_fpSqrtTest_b_23_rdcnt_i; + (* preserve_syn_only *) reg redist14_expX_uid6_fpSqrtTest_b_23_rdcnt_eq; + wire [0:0] redist14_expX_uid6_fpSqrtTest_b_23_rdmux_s; + reg [4:0] redist14_expX_uid6_fpSqrtTest_b_23_rdmux_q; + reg [4:0] redist14_expX_uid6_fpSqrtTest_b_23_wraddr_q; + wire [5:0] redist14_expX_uid6_fpSqrtTest_b_23_mem_last_q; + wire [5:0] redist14_expX_uid6_fpSqrtTest_b_23_cmp_b; + wire [0:0] redist14_expX_uid6_fpSqrtTest_b_23_cmp_q; + reg [0:0] redist14_expX_uid6_fpSqrtTest_b_23_cmpReg_q; + wire [0:0] redist14_expX_uid6_fpSqrtTest_b_23_notEnable_q; + wire [0:0] redist14_expX_uid6_fpSqrtTest_b_23_nor_q; + (* preserve_syn_only *) reg [0:0] redist14_expX_uid6_fpSqrtTest_b_23_sticky_ena_q; + wire [0:0] redist14_expX_uid6_fpSqrtTest_b_23_enaAnd_q; + + + // signX_uid7_fpSqrtTest(BITSELECT,6)@0 + assign signX_uid7_fpSqrtTest_b = a[31:31]; + + // redist13_signX_uid7_fpSqrtTest_b_24(DELAY,138) + dspba_delay_ver #( .width(1), .depth(24), .reset_kind("SYNC"), .phase(0), .modulus(1) ) + redist13_signX_uid7_fpSqrtTest_b_24 ( .xin(signX_uid7_fpSqrtTest_b), .xout(redist13_signX_uid7_fpSqrtTest_b_24_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // cstAllZWE_uid10_fpSqrtTest(CONSTANT,9) + assign cstAllZWE_uid10_fpSqrtTest_q = 8'b00000000; + + // redist14_expX_uid6_fpSqrtTest_b_23_notEnable(LOGICAL,205) + assign redist14_expX_uid6_fpSqrtTest_b_23_notEnable_q = ~ (en); + + // redist14_expX_uid6_fpSqrtTest_b_23_nor(LOGICAL,206) + assign redist14_expX_uid6_fpSqrtTest_b_23_nor_q = ~ (redist14_expX_uid6_fpSqrtTest_b_23_notEnable_q | redist14_expX_uid6_fpSqrtTest_b_23_sticky_ena_q); + + // redist14_expX_uid6_fpSqrtTest_b_23_mem_last(CONSTANT,202) + assign redist14_expX_uid6_fpSqrtTest_b_23_mem_last_q = 6'b010100; + + // redist14_expX_uid6_fpSqrtTest_b_23_cmp(LOGICAL,203) + assign redist14_expX_uid6_fpSqrtTest_b_23_cmp_b = {1'b0, redist14_expX_uid6_fpSqrtTest_b_23_rdmux_q}; + assign redist14_expX_uid6_fpSqrtTest_b_23_cmp_q = redist14_expX_uid6_fpSqrtTest_b_23_mem_last_q == redist14_expX_uid6_fpSqrtTest_b_23_cmp_b ? 1'b1 : 1'b0; + + // redist14_expX_uid6_fpSqrtTest_b_23_cmpReg(REG,204) + always @ (posedge clk) + begin + if (areset) + begin + redist14_expX_uid6_fpSqrtTest_b_23_cmpReg_q <= 1'b0; + end + else if (en == 1'b1) + begin + redist14_expX_uid6_fpSqrtTest_b_23_cmpReg_q <= redist14_expX_uid6_fpSqrtTest_b_23_cmp_q; + end + end + + // redist14_expX_uid6_fpSqrtTest_b_23_sticky_ena(REG,207) + always @ (posedge clk) + begin + if (areset) + begin + redist14_expX_uid6_fpSqrtTest_b_23_sticky_ena_q <= 1'b0; + end + else if (redist14_expX_uid6_fpSqrtTest_b_23_nor_q == 1'b1) + begin + redist14_expX_uid6_fpSqrtTest_b_23_sticky_ena_q <= redist14_expX_uid6_fpSqrtTest_b_23_cmpReg_q; + end + end + + // redist14_expX_uid6_fpSqrtTest_b_23_enaAnd(LOGICAL,208) + assign redist14_expX_uid6_fpSqrtTest_b_23_enaAnd_q = redist14_expX_uid6_fpSqrtTest_b_23_sticky_ena_q & en; + + // redist14_expX_uid6_fpSqrtTest_b_23_rdcnt(COUNTER,199) + // low=0, high=21, step=1, init=0 + always @ (posedge clk) + begin + if (areset) + begin + redist14_expX_uid6_fpSqrtTest_b_23_rdcnt_i <= 5'd0; + redist14_expX_uid6_fpSqrtTest_b_23_rdcnt_eq <= 1'b0; + end + else if (en == 1'b1) + begin + if (redist14_expX_uid6_fpSqrtTest_b_23_rdcnt_i == 5'd20) + begin + redist14_expX_uid6_fpSqrtTest_b_23_rdcnt_eq <= 1'b1; + end + else + begin + redist14_expX_uid6_fpSqrtTest_b_23_rdcnt_eq <= 1'b0; + end + if (redist14_expX_uid6_fpSqrtTest_b_23_rdcnt_eq == 1'b1) + begin + redist14_expX_uid6_fpSqrtTest_b_23_rdcnt_i <= $unsigned(redist14_expX_uid6_fpSqrtTest_b_23_rdcnt_i) + $unsigned(5'd11); + end + else + begin + redist14_expX_uid6_fpSqrtTest_b_23_rdcnt_i <= $unsigned(redist14_expX_uid6_fpSqrtTest_b_23_rdcnt_i) + $unsigned(5'd1); + end + end + end + assign redist14_expX_uid6_fpSqrtTest_b_23_rdcnt_q = redist14_expX_uid6_fpSqrtTest_b_23_rdcnt_i[4:0]; + + // redist14_expX_uid6_fpSqrtTest_b_23_rdmux(MUX,200) + assign redist14_expX_uid6_fpSqrtTest_b_23_rdmux_s = en; + always @(redist14_expX_uid6_fpSqrtTest_b_23_rdmux_s or redist14_expX_uid6_fpSqrtTest_b_23_wraddr_q or redist14_expX_uid6_fpSqrtTest_b_23_rdcnt_q) + begin + unique case (redist14_expX_uid6_fpSqrtTest_b_23_rdmux_s) + 1'b0 : redist14_expX_uid6_fpSqrtTest_b_23_rdmux_q = redist14_expX_uid6_fpSqrtTest_b_23_wraddr_q; + 1'b1 : redist14_expX_uid6_fpSqrtTest_b_23_rdmux_q = redist14_expX_uid6_fpSqrtTest_b_23_rdcnt_q; + default : redist14_expX_uid6_fpSqrtTest_b_23_rdmux_q = 5'b0; + endcase + end + + // VCC(CONSTANT,1) + assign VCC_q = 1'b1; + + // expX_uid6_fpSqrtTest(BITSELECT,5)@0 + assign expX_uid6_fpSqrtTest_b = a[30:23]; + + // redist14_expX_uid6_fpSqrtTest_b_23_wraddr(REG,201) + always @ (posedge clk) + begin + if (areset) + begin + redist14_expX_uid6_fpSqrtTest_b_23_wraddr_q <= 5'b10101; + end + else + begin + redist14_expX_uid6_fpSqrtTest_b_23_wraddr_q <= redist14_expX_uid6_fpSqrtTest_b_23_rdmux_q; + end + end + + // redist14_expX_uid6_fpSqrtTest_b_23_mem(DUALMEM,198) + assign redist14_expX_uid6_fpSqrtTest_b_23_mem_ia = expX_uid6_fpSqrtTest_b; + assign redist14_expX_uid6_fpSqrtTest_b_23_mem_aa = redist14_expX_uid6_fpSqrtTest_b_23_wraddr_q; + assign redist14_expX_uid6_fpSqrtTest_b_23_mem_ab = redist14_expX_uid6_fpSqrtTest_b_23_rdmux_q; + assign redist14_expX_uid6_fpSqrtTest_b_23_mem_reset0 = areset; + altera_syncram #( + .ram_block_type("MLAB"), + .operation_mode("DUAL_PORT"), + .width_a(8), + .widthad_a(5), + .numwords_a(22), + .width_b(8), + .widthad_b(5), + .numwords_b(22), + .lpm_type("altera_syncram"), + .width_byteena_a(1), + .address_reg_b("CLOCK0"), + .indata_reg_b("CLOCK0"), + .rdcontrol_reg_b("CLOCK0"), + .byteena_reg_b("CLOCK0"), + .outdata_reg_b("CLOCK1"), + .outdata_sclr_b("SCLEAR"), + .clock_enable_input_a("NORMAL"), + .clock_enable_input_b("NORMAL"), + .clock_enable_output_b("NORMAL"), + .read_during_write_mode_mixed_ports("DONT_CARE"), + .power_up_uninitialized("TRUE"), + .intended_device_family("Stratix 10") + ) redist14_expX_uid6_fpSqrtTest_b_23_mem_dmem ( + .clocken1(redist14_expX_uid6_fpSqrtTest_b_23_mem_enaOr_rst), + .clocken0(VCC_q[0]), + .clock0(clk), + .sclr(redist14_expX_uid6_fpSqrtTest_b_23_mem_reset0), + .clock1(clk), + .address_a(redist14_expX_uid6_fpSqrtTest_b_23_mem_aa), + .data_a(redist14_expX_uid6_fpSqrtTest_b_23_mem_ia), + .wren_a(en[0]), + .address_b(redist14_expX_uid6_fpSqrtTest_b_23_mem_ab), + .q_b(redist14_expX_uid6_fpSqrtTest_b_23_mem_iq), + .wren_b(), + .rden_a(), + .rden_b(), + .data_b(), + .clocken2(), + .clocken3(), + .aclr0(), + .aclr1(), + .addressstall_a(), + .addressstall_b(), + .byteena_a(), + .byteena_b(), + .eccencbypass(), + .eccencparity(), + .address2_a(), + .address2_b(), + .q_a(), + .eccstatus() + ); + assign redist14_expX_uid6_fpSqrtTest_b_23_mem_q = redist14_expX_uid6_fpSqrtTest_b_23_mem_iq[7:0]; + assign redist14_expX_uid6_fpSqrtTest_b_23_mem_enaOr_rst = redist14_expX_uid6_fpSqrtTest_b_23_enaAnd_q[0] | redist14_expX_uid6_fpSqrtTest_b_23_mem_reset0; + + // excZ_x_uid13_fpSqrtTest(LOGICAL,12)@23 + 1 + assign excZ_x_uid13_fpSqrtTest_qi = redist14_expX_uid6_fpSqrtTest_b_23_mem_q == cstAllZWE_uid10_fpSqrtTest_q ? 1'b1 : 1'b0; + dspba_delay_ver #( .width(1), .depth(1), .reset_kind("SYNC"), .phase(0), .modulus(1) ) + excZ_x_uid13_fpSqrtTest_delay ( .xin(excZ_x_uid13_fpSqrtTest_qi), .xout(excZ_x_uid13_fpSqrtTest_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // negZero_uid85_fpSqrtTest(LOGICAL,84)@24 + 1 + assign negZero_uid85_fpSqrtTest_qi = excZ_x_uid13_fpSqrtTest_q & redist13_signX_uid7_fpSqrtTest_b_24_q; + dspba_delay_ver #( .width(1), .depth(1), .reset_kind("SYNC"), .phase(0), .modulus(1) ) + negZero_uid85_fpSqrtTest_delay ( .xin(negZero_uid85_fpSqrtTest_qi), .xout(negZero_uid85_fpSqrtTest_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // cstAllOWE_uid8_fpSqrtTest(CONSTANT,7) + assign cstAllOWE_uid8_fpSqrtTest_q = 8'b11111111; + + // GND(CONSTANT,0) + assign GND_q = 1'b0; + + // redist12_frac_x_uid12_fpSqrtTest_b_23_notEnable(LOGICAL,194) + assign redist12_frac_x_uid12_fpSqrtTest_b_23_notEnable_q = ~ (en); + + // redist12_frac_x_uid12_fpSqrtTest_b_23_nor(LOGICAL,195) + assign redist12_frac_x_uid12_fpSqrtTest_b_23_nor_q = ~ (redist12_frac_x_uid12_fpSqrtTest_b_23_notEnable_q | redist12_frac_x_uid12_fpSqrtTest_b_23_sticky_ena_q); + + // redist12_frac_x_uid12_fpSqrtTest_b_23_mem_last(CONSTANT,191) + assign redist12_frac_x_uid12_fpSqrtTest_b_23_mem_last_q = 6'b010001; + + // redist12_frac_x_uid12_fpSqrtTest_b_23_cmp(LOGICAL,192) + assign redist12_frac_x_uid12_fpSqrtTest_b_23_cmp_b = {1'b0, redist12_frac_x_uid12_fpSqrtTest_b_23_rdmux_q}; + assign redist12_frac_x_uid12_fpSqrtTest_b_23_cmp_q = redist12_frac_x_uid12_fpSqrtTest_b_23_mem_last_q == redist12_frac_x_uid12_fpSqrtTest_b_23_cmp_b ? 1'b1 : 1'b0; + + // redist12_frac_x_uid12_fpSqrtTest_b_23_cmpReg(REG,193) + always @ (posedge clk) + begin + if (areset) + begin + redist12_frac_x_uid12_fpSqrtTest_b_23_cmpReg_q <= 1'b0; + end + else if (en == 1'b1) + begin + redist12_frac_x_uid12_fpSqrtTest_b_23_cmpReg_q <= redist12_frac_x_uid12_fpSqrtTest_b_23_cmp_q; + end + end + + // redist12_frac_x_uid12_fpSqrtTest_b_23_sticky_ena(REG,196) + always @ (posedge clk) + begin + if (areset) + begin + redist12_frac_x_uid12_fpSqrtTest_b_23_sticky_ena_q <= 1'b0; + end + else if (redist12_frac_x_uid12_fpSqrtTest_b_23_nor_q == 1'b1) + begin + redist12_frac_x_uid12_fpSqrtTest_b_23_sticky_ena_q <= redist12_frac_x_uid12_fpSqrtTest_b_23_cmpReg_q; + end + end + + // redist12_frac_x_uid12_fpSqrtTest_b_23_enaAnd(LOGICAL,197) + assign redist12_frac_x_uid12_fpSqrtTest_b_23_enaAnd_q = redist12_frac_x_uid12_fpSqrtTest_b_23_sticky_ena_q & en; + + // redist12_frac_x_uid12_fpSqrtTest_b_23_rdcnt(COUNTER,188) + // low=0, high=18, step=1, init=0 + always @ (posedge clk) + begin + if (areset) + begin + redist12_frac_x_uid12_fpSqrtTest_b_23_rdcnt_i <= 5'd0; + redist12_frac_x_uid12_fpSqrtTest_b_23_rdcnt_eq <= 1'b0; + end + else if (en == 1'b1) + begin + if (redist12_frac_x_uid12_fpSqrtTest_b_23_rdcnt_i == 5'd17) + begin + redist12_frac_x_uid12_fpSqrtTest_b_23_rdcnt_eq <= 1'b1; + end + else + begin + redist12_frac_x_uid12_fpSqrtTest_b_23_rdcnt_eq <= 1'b0; + end + if (redist12_frac_x_uid12_fpSqrtTest_b_23_rdcnt_eq == 1'b1) + begin + redist12_frac_x_uid12_fpSqrtTest_b_23_rdcnt_i <= $unsigned(redist12_frac_x_uid12_fpSqrtTest_b_23_rdcnt_i) + $unsigned(5'd14); + end + else + begin + redist12_frac_x_uid12_fpSqrtTest_b_23_rdcnt_i <= $unsigned(redist12_frac_x_uid12_fpSqrtTest_b_23_rdcnt_i) + $unsigned(5'd1); + end + end + end + assign redist12_frac_x_uid12_fpSqrtTest_b_23_rdcnt_q = redist12_frac_x_uid12_fpSqrtTest_b_23_rdcnt_i[4:0]; + + // redist12_frac_x_uid12_fpSqrtTest_b_23_rdmux(MUX,189) + assign redist12_frac_x_uid12_fpSqrtTest_b_23_rdmux_s = en; + always @(redist12_frac_x_uid12_fpSqrtTest_b_23_rdmux_s or redist12_frac_x_uid12_fpSqrtTest_b_23_wraddr_q or redist12_frac_x_uid12_fpSqrtTest_b_23_rdcnt_q) + begin + unique case (redist12_frac_x_uid12_fpSqrtTest_b_23_rdmux_s) + 1'b0 : redist12_frac_x_uid12_fpSqrtTest_b_23_rdmux_q = redist12_frac_x_uid12_fpSqrtTest_b_23_wraddr_q; + 1'b1 : redist12_frac_x_uid12_fpSqrtTest_b_23_rdmux_q = redist12_frac_x_uid12_fpSqrtTest_b_23_rdcnt_q; + default : redist12_frac_x_uid12_fpSqrtTest_b_23_rdmux_q = 5'b0; + endcase + end + + // frac_x_uid12_fpSqrtTest(BITSELECT,11)@0 + assign frac_x_uid12_fpSqrtTest_b = a[22:0]; + + // redist11_frac_x_uid12_fpSqrtTest_b_3(DELAY,136) + always @ (posedge clk) + begin + if (areset) + begin + redist11_frac_x_uid12_fpSqrtTest_b_3_delay_0 <= '0; + redist11_frac_x_uid12_fpSqrtTest_b_3_delay_1 <= '0; + redist11_frac_x_uid12_fpSqrtTest_b_3_q <= '0; + end + else if (en == 1'b1) + begin + redist11_frac_x_uid12_fpSqrtTest_b_3_delay_0 <= frac_x_uid12_fpSqrtTest_b; + redist11_frac_x_uid12_fpSqrtTest_b_3_delay_1 <= redist11_frac_x_uid12_fpSqrtTest_b_3_delay_0; + redist11_frac_x_uid12_fpSqrtTest_b_3_q <= redist11_frac_x_uid12_fpSqrtTest_b_3_delay_1; + end + end + + // redist12_frac_x_uid12_fpSqrtTest_b_23_wraddr(REG,190) + always @ (posedge clk) + begin + if (areset) + begin + redist12_frac_x_uid12_fpSqrtTest_b_23_wraddr_q <= 5'b10010; + end + else + begin + redist12_frac_x_uid12_fpSqrtTest_b_23_wraddr_q <= redist12_frac_x_uid12_fpSqrtTest_b_23_rdmux_q; + end + end + + // redist12_frac_x_uid12_fpSqrtTest_b_23_mem(DUALMEM,187) + assign redist12_frac_x_uid12_fpSqrtTest_b_23_mem_ia = redist11_frac_x_uid12_fpSqrtTest_b_3_q; + assign redist12_frac_x_uid12_fpSqrtTest_b_23_mem_aa = redist12_frac_x_uid12_fpSqrtTest_b_23_wraddr_q; + assign redist12_frac_x_uid12_fpSqrtTest_b_23_mem_ab = redist12_frac_x_uid12_fpSqrtTest_b_23_rdmux_q; + assign redist12_frac_x_uid12_fpSqrtTest_b_23_mem_reset0 = areset; + altera_syncram #( + .ram_block_type("MLAB"), + .operation_mode("DUAL_PORT"), + .width_a(23), + .widthad_a(5), + .numwords_a(19), + .width_b(23), + .widthad_b(5), + .numwords_b(19), + .lpm_type("altera_syncram"), + .width_byteena_a(1), + .address_reg_b("CLOCK0"), + .indata_reg_b("CLOCK0"), + .rdcontrol_reg_b("CLOCK0"), + .byteena_reg_b("CLOCK0"), + .outdata_reg_b("CLOCK1"), + .outdata_sclr_b("SCLEAR"), + .clock_enable_input_a("NORMAL"), + .clock_enable_input_b("NORMAL"), + .clock_enable_output_b("NORMAL"), + .read_during_write_mode_mixed_ports("DONT_CARE"), + .power_up_uninitialized("TRUE"), + .intended_device_family("Stratix 10") + ) redist12_frac_x_uid12_fpSqrtTest_b_23_mem_dmem ( + .clocken1(redist12_frac_x_uid12_fpSqrtTest_b_23_mem_enaOr_rst), + .clocken0(VCC_q[0]), + .clock0(clk), + .sclr(redist12_frac_x_uid12_fpSqrtTest_b_23_mem_reset0), + .clock1(clk), + .address_a(redist12_frac_x_uid12_fpSqrtTest_b_23_mem_aa), + .data_a(redist12_frac_x_uid12_fpSqrtTest_b_23_mem_ia), + .wren_a(en[0]), + .address_b(redist12_frac_x_uid12_fpSqrtTest_b_23_mem_ab), + .q_b(redist12_frac_x_uid12_fpSqrtTest_b_23_mem_iq), + .wren_b(), + .rden_a(), + .rden_b(), + .data_b(), + .clocken2(), + .clocken3(), + .aclr0(), + .aclr1(), + .addressstall_a(), + .addressstall_b(), + .byteena_a(), + .byteena_b(), + .eccencbypass(), + .eccencparity(), + .address2_a(), + .address2_b(), + .q_a(), + .eccstatus() + ); + assign redist12_frac_x_uid12_fpSqrtTest_b_23_mem_q = redist12_frac_x_uid12_fpSqrtTest_b_23_mem_iq[22:0]; + assign redist12_frac_x_uid12_fpSqrtTest_b_23_mem_enaOr_rst = redist12_frac_x_uid12_fpSqrtTest_b_23_enaAnd_q[0] | redist12_frac_x_uid12_fpSqrtTest_b_23_mem_reset0; + + // oFracX_uid44_fpSqrtTest(BITJOIN,43)@23 + assign oFracX_uid44_fpSqrtTest_q = {VCC_q, redist12_frac_x_uid12_fpSqrtTest_b_23_mem_q}; + + // oFracXZ_mergedSignalTM_uid47_fpSqrtTest(BITJOIN,46)@23 + assign oFracXZ_mergedSignalTM_uid47_fpSqrtTest_q = {oFracX_uid44_fpSqrtTest_q, GND_q}; + + // oFracXSignExt_mergedSignalTM_uid52_fpSqrtTest(BITJOIN,51)@23 + assign oFracXSignExt_mergedSignalTM_uid52_fpSqrtTest_q = {GND_q, oFracX_uid44_fpSqrtTest_q}; + + // expX0PS_uid29_fpSqrtTest(BITSELECT,28)@0 + assign expX0PS_uid29_fpSqrtTest_in = expX_uid6_fpSqrtTest_b[0:0]; + assign expX0PS_uid29_fpSqrtTest_b = expX0PS_uid29_fpSqrtTest_in[0:0]; + + // expOddSelect_uid30_fpSqrtTest(LOGICAL,29)@0 + assign expOddSelect_uid30_fpSqrtTest_q = ~ (expX0PS_uid29_fpSqrtTest_b); + + // redist10_expOddSelect_uid30_fpSqrtTest_q_23(DELAY,135) + dspba_delay_ver #( .width(1), .depth(23), .reset_kind("SYNC"), .phase(0), .modulus(1) ) + redist10_expOddSelect_uid30_fpSqrtTest_q_23 ( .xin(expOddSelect_uid30_fpSqrtTest_q), .xout(redist10_expOddSelect_uid30_fpSqrtTest_q_23_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // normalizedXForComp_uid54_fpSqrtTest(MUX,53)@23 + assign normalizedXForComp_uid54_fpSqrtTest_s = redist10_expOddSelect_uid30_fpSqrtTest_q_23_q; + always @(normalizedXForComp_uid54_fpSqrtTest_s or en or oFracXSignExt_mergedSignalTM_uid52_fpSqrtTest_q or oFracXZ_mergedSignalTM_uid47_fpSqrtTest_q) + begin + unique case (normalizedXForComp_uid54_fpSqrtTest_s) + 1'b0 : normalizedXForComp_uid54_fpSqrtTest_q = oFracXSignExt_mergedSignalTM_uid52_fpSqrtTest_q; + 1'b1 : normalizedXForComp_uid54_fpSqrtTest_q = oFracXZ_mergedSignalTM_uid47_fpSqrtTest_q; + default : normalizedXForComp_uid54_fpSqrtTest_q = 25'b0; + endcase + end + + // paddingY_uid55_fpSqrtTest(CONSTANT,54) + assign paddingY_uid55_fpSqrtTest_q = 25'b0000000000000000000000000; + + // updatedY_uid56_fpSqrtTest(BITJOIN,55)@23 + assign updatedY_uid56_fpSqrtTest_q = {normalizedXForComp_uid54_fpSqrtTest_q, paddingY_uid55_fpSqrtTest_q}; + + // addrFull_uid33_fpSqrtTest(BITJOIN,32)@0 + assign addrFull_uid33_fpSqrtTest_q = {expOddSelect_uid30_fpSqrtTest_q, frac_x_uid12_fpSqrtTest_b}; + + // yAddr_uid35_fpSqrtTest(BITSELECT,34)@0 + assign yAddr_uid35_fpSqrtTest_b = addrFull_uid33_fpSqrtTest_q[23:16]; + + // memoryC2_uid94_sqrtTables_lutmem(DUALMEM,120)@0 + 2 + // in j@20000000 + assign memoryC2_uid94_sqrtTables_lutmem_aa = yAddr_uid35_fpSqrtTest_b; + assign memoryC2_uid94_sqrtTables_lutmem_reset0 = areset; + altera_syncram #( + .ram_block_type("M20K"), + .operation_mode("ROM"), + .width_a(12), + .widthad_a(8), + .numwords_a(256), + .lpm_type("altera_syncram"), + .width_byteena_a(1), + .outdata_reg_a("CLOCK0"), + .outdata_sclr_a("SCLEAR"), + .clock_enable_input_a("NORMAL"), + .power_up_uninitialized("FALSE"), + .init_file("acl_fsqrt_memoryC2_uid94_sqrtTables_lutmem.hex"), + .init_file_layout("PORT_A"), + .intended_device_family("Stratix 10") + ) memoryC2_uid94_sqrtTables_lutmem_dmem ( + .clocken0(en[0]), + .sclr(memoryC2_uid94_sqrtTables_lutmem_reset0), + .clock0(clk), + .address_a(memoryC2_uid94_sqrtTables_lutmem_aa), + .q_a(memoryC2_uid94_sqrtTables_lutmem_ir), + .wren_a(), + .wren_b(), + .rden_a(), + .rden_b(), + .data_a(), + .data_b(), + .address_b(), + .clock1(), + .clocken1(), + .clocken2(), + .clocken3(), + .aclr0(), + .aclr1(), + .addressstall_a(), + .addressstall_b(), + .byteena_a(), + .byteena_b(), + .eccencbypass(), + .eccencparity(), + .address2_a(), + .address2_b(), + .q_b(), + .eccstatus() + ); + assign memoryC2_uid94_sqrtTables_lutmem_r = memoryC2_uid94_sqrtTables_lutmem_ir[11:0]; + assign memoryC2_uid94_sqrtTables_lutmem_enaOr_rst = en[0] | memoryC2_uid94_sqrtTables_lutmem_reset0; + + // redist1_memoryC2_uid94_sqrtTables_lutmem_r_1(DELAY,126) + always @ (posedge clk) + begin + if (areset) + begin + redist1_memoryC2_uid94_sqrtTables_lutmem_r_1_q <= '0; + end + else if (en == 1'b1) + begin + redist1_memoryC2_uid94_sqrtTables_lutmem_r_1_q <= memoryC2_uid94_sqrtTables_lutmem_r; + end + end + + // yForPe_uid36_fpSqrtTest(BITSELECT,35)@3 + assign yForPe_uid36_fpSqrtTest_in = redist11_frac_x_uid12_fpSqrtTest_b_3_q[15:0]; + assign yForPe_uid36_fpSqrtTest_b = yForPe_uid36_fpSqrtTest_in[15:0]; + + // yT1_uid100_invPolyEval(BITSELECT,99)@3 + assign yT1_uid100_invPolyEval_b = yForPe_uid36_fpSqrtTest_b[15:4]; + + // prodXY_uid113_pT1_uid101_invPolyEval_cma(CHAINMULTADD,122)@3 + 5 + // out q@9 + assign prodXY_uid113_pT1_uid101_invPolyEval_cma_reset = areset; + assign prodXY_uid113_pT1_uid101_invPolyEval_cma_ena0 = en[0] | prodXY_uid113_pT1_uid101_invPolyEval_cma_reset; + assign prodXY_uid113_pT1_uid101_invPolyEval_cma_ena1 = prodXY_uid113_pT1_uid101_invPolyEval_cma_ena0; + assign prodXY_uid113_pT1_uid101_invPolyEval_cma_ena2 = prodXY_uid113_pT1_uid101_invPolyEval_cma_ena0; + always @ (posedge clk) + begin + if (0) + begin + end + else + begin + if (en == 1'b1) + begin + prodXY_uid113_pT1_uid101_invPolyEval_cma_ah[0] <= yT1_uid100_invPolyEval_b; + prodXY_uid113_pT1_uid101_invPolyEval_cma_ch[0] <= redist1_memoryC2_uid94_sqrtTables_lutmem_r_1_q; + end + end + end + + assign prodXY_uid113_pT1_uid101_invPolyEval_cma_a0 = prodXY_uid113_pT1_uid101_invPolyEval_cma_ah[0]; + assign prodXY_uid113_pT1_uid101_invPolyEval_cma_c0 = prodXY_uid113_pT1_uid101_invPolyEval_cma_ch[0]; + fourteennm_mac #( + .operation_mode("m18x18_full"), + .clear_type("sclr"), + .ay_scan_in_clock("0"), + .ay_scan_in_width(12), + .ax_clock("0"), + .ax_width(12), + .signed_may("false"), + .signed_max("true"), + .input_pipeline_clock("2"), + .second_pipeline_clock("2"), + .output_clock("1"), + .result_a_width(24) + ) prodXY_uid113_pT1_uid101_invPolyEval_cma_DSP0 ( + .clk({clk,clk,clk}), + .ena({ prodXY_uid113_pT1_uid101_invPolyEval_cma_ena2, prodXY_uid113_pT1_uid101_invPolyEval_cma_ena1, prodXY_uid113_pT1_uid101_invPolyEval_cma_ena0 }), + .clr({ prodXY_uid113_pT1_uid101_invPolyEval_cma_reset, prodXY_uid113_pT1_uid101_invPolyEval_cma_reset }), + .ay(prodXY_uid113_pT1_uid101_invPolyEval_cma_a0), + .ax(prodXY_uid113_pT1_uid101_invPolyEval_cma_c0), + .resulta(prodXY_uid113_pT1_uid101_invPolyEval_cma_s0), + .accumulate(), + .loadconst(), + .negate(), + .sub(), + .az(), + .coefsela(), + .bx(), + .by(), + .bz(), + .coefselb(), + .scanin(), + .scanout(), + .chainin(), + .chainout(), + .resultb(), + .dfxlfsrena(), + .dfxmisrena(), + .dftout() + ); + dspba_delay_ver #( .width(24), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1) ) + prodXY_uid113_pT1_uid101_invPolyEval_cma_delay ( .xin(prodXY_uid113_pT1_uid101_invPolyEval_cma_s0), .xout(prodXY_uid113_pT1_uid101_invPolyEval_cma_qq), .ena(en[0]), .clk(clk), .aclr(areset) ); + assign prodXY_uid113_pT1_uid101_invPolyEval_cma_q = prodXY_uid113_pT1_uid101_invPolyEval_cma_qq[23:0]; + + // osig_uid114_pT1_uid101_invPolyEval(BITSELECT,113)@9 + assign osig_uid114_pT1_uid101_invPolyEval_b = prodXY_uid113_pT1_uid101_invPolyEval_cma_q[23:11]; + + // highBBits_uid103_invPolyEval(BITSELECT,102)@9 + assign highBBits_uid103_invPolyEval_b = osig_uid114_pT1_uid101_invPolyEval_b[12:1]; + + // redist7_yAddr_uid35_fpSqrtTest_b_7_notEnable(LOGICAL,171) + assign redist7_yAddr_uid35_fpSqrtTest_b_7_notEnable_q = ~ (en); + + // redist7_yAddr_uid35_fpSqrtTest_b_7_nor(LOGICAL,172) + assign redist7_yAddr_uid35_fpSqrtTest_b_7_nor_q = ~ (redist7_yAddr_uid35_fpSqrtTest_b_7_notEnable_q | redist7_yAddr_uid35_fpSqrtTest_b_7_sticky_ena_q); + + // redist7_yAddr_uid35_fpSqrtTest_b_7_mem_last(CONSTANT,168) + assign redist7_yAddr_uid35_fpSqrtTest_b_7_mem_last_q = 3'b011; + + // redist7_yAddr_uid35_fpSqrtTest_b_7_cmp(LOGICAL,169) + assign redist7_yAddr_uid35_fpSqrtTest_b_7_cmp_q = redist7_yAddr_uid35_fpSqrtTest_b_7_mem_last_q == redist7_yAddr_uid35_fpSqrtTest_b_7_rdmux_q ? 1'b1 : 1'b0; + + // redist7_yAddr_uid35_fpSqrtTest_b_7_cmpReg(REG,170) + always @ (posedge clk) + begin + if (areset) + begin + redist7_yAddr_uid35_fpSqrtTest_b_7_cmpReg_q <= 1'b0; + end + else if (en == 1'b1) + begin + redist7_yAddr_uid35_fpSqrtTest_b_7_cmpReg_q <= redist7_yAddr_uid35_fpSqrtTest_b_7_cmp_q; + end + end + + // redist7_yAddr_uid35_fpSqrtTest_b_7_sticky_ena(REG,173) + always @ (posedge clk) + begin + if (areset) + begin + redist7_yAddr_uid35_fpSqrtTest_b_7_sticky_ena_q <= 1'b0; + end + else if (redist7_yAddr_uid35_fpSqrtTest_b_7_nor_q == 1'b1) + begin + redist7_yAddr_uid35_fpSqrtTest_b_7_sticky_ena_q <= redist7_yAddr_uid35_fpSqrtTest_b_7_cmpReg_q; + end + end + + // redist7_yAddr_uid35_fpSqrtTest_b_7_enaAnd(LOGICAL,174) + assign redist7_yAddr_uid35_fpSqrtTest_b_7_enaAnd_q = redist7_yAddr_uid35_fpSqrtTest_b_7_sticky_ena_q & en; + + // redist7_yAddr_uid35_fpSqrtTest_b_7_rdcnt(COUNTER,165) + // low=0, high=4, step=1, init=0 + always @ (posedge clk) + begin + if (areset) + begin + redist7_yAddr_uid35_fpSqrtTest_b_7_rdcnt_i <= 3'd0; + redist7_yAddr_uid35_fpSqrtTest_b_7_rdcnt_eq <= 1'b0; + end + else if (en == 1'b1) + begin + if (redist7_yAddr_uid35_fpSqrtTest_b_7_rdcnt_i == 3'd3) + begin + redist7_yAddr_uid35_fpSqrtTest_b_7_rdcnt_eq <= 1'b1; + end + else + begin + redist7_yAddr_uid35_fpSqrtTest_b_7_rdcnt_eq <= 1'b0; + end + if (redist7_yAddr_uid35_fpSqrtTest_b_7_rdcnt_eq == 1'b1) + begin + redist7_yAddr_uid35_fpSqrtTest_b_7_rdcnt_i <= $unsigned(redist7_yAddr_uid35_fpSqrtTest_b_7_rdcnt_i) + $unsigned(3'd4); + end + else + begin + redist7_yAddr_uid35_fpSqrtTest_b_7_rdcnt_i <= $unsigned(redist7_yAddr_uid35_fpSqrtTest_b_7_rdcnt_i) + $unsigned(3'd1); + end + end + end + assign redist7_yAddr_uid35_fpSqrtTest_b_7_rdcnt_q = redist7_yAddr_uid35_fpSqrtTest_b_7_rdcnt_i[2:0]; + + // redist7_yAddr_uid35_fpSqrtTest_b_7_rdmux(MUX,166) + assign redist7_yAddr_uid35_fpSqrtTest_b_7_rdmux_s = en; + always @(redist7_yAddr_uid35_fpSqrtTest_b_7_rdmux_s or redist7_yAddr_uid35_fpSqrtTest_b_7_wraddr_q or redist7_yAddr_uid35_fpSqrtTest_b_7_rdcnt_q) + begin + unique case (redist7_yAddr_uid35_fpSqrtTest_b_7_rdmux_s) + 1'b0 : redist7_yAddr_uid35_fpSqrtTest_b_7_rdmux_q = redist7_yAddr_uid35_fpSqrtTest_b_7_wraddr_q; + 1'b1 : redist7_yAddr_uid35_fpSqrtTest_b_7_rdmux_q = redist7_yAddr_uid35_fpSqrtTest_b_7_rdcnt_q; + default : redist7_yAddr_uid35_fpSqrtTest_b_7_rdmux_q = 3'b0; + endcase + end + + // redist7_yAddr_uid35_fpSqrtTest_b_7_wraddr(REG,167) + always @ (posedge clk) + begin + if (areset) + begin + redist7_yAddr_uid35_fpSqrtTest_b_7_wraddr_q <= 3'b100; + end + else + begin + redist7_yAddr_uid35_fpSqrtTest_b_7_wraddr_q <= redist7_yAddr_uid35_fpSqrtTest_b_7_rdmux_q; + end + end + + // redist7_yAddr_uid35_fpSqrtTest_b_7_mem(DUALMEM,164) + assign redist7_yAddr_uid35_fpSqrtTest_b_7_mem_ia = yAddr_uid35_fpSqrtTest_b; + assign redist7_yAddr_uid35_fpSqrtTest_b_7_mem_aa = redist7_yAddr_uid35_fpSqrtTest_b_7_wraddr_q; + assign redist7_yAddr_uid35_fpSqrtTest_b_7_mem_ab = redist7_yAddr_uid35_fpSqrtTest_b_7_rdmux_q; + assign redist7_yAddr_uid35_fpSqrtTest_b_7_mem_reset0 = areset; + altera_syncram #( + .ram_block_type("MLAB"), + .operation_mode("DUAL_PORT"), + .width_a(8), + .widthad_a(3), + .numwords_a(5), + .width_b(8), + .widthad_b(3), + .numwords_b(5), + .lpm_type("altera_syncram"), + .width_byteena_a(1), + .address_reg_b("CLOCK0"), + .indata_reg_b("CLOCK0"), + .rdcontrol_reg_b("CLOCK0"), + .byteena_reg_b("CLOCK0"), + .outdata_reg_b("CLOCK1"), + .outdata_sclr_b("SCLEAR"), + .clock_enable_input_a("NORMAL"), + .clock_enable_input_b("NORMAL"), + .clock_enable_output_b("NORMAL"), + .read_during_write_mode_mixed_ports("DONT_CARE"), + .power_up_uninitialized("TRUE"), + .intended_device_family("Stratix 10") + ) redist7_yAddr_uid35_fpSqrtTest_b_7_mem_dmem ( + .clocken1(redist7_yAddr_uid35_fpSqrtTest_b_7_mem_enaOr_rst), + .clocken0(VCC_q[0]), + .clock0(clk), + .sclr(redist7_yAddr_uid35_fpSqrtTest_b_7_mem_reset0), + .clock1(clk), + .address_a(redist7_yAddr_uid35_fpSqrtTest_b_7_mem_aa), + .data_a(redist7_yAddr_uid35_fpSqrtTest_b_7_mem_ia), + .wren_a(en[0]), + .address_b(redist7_yAddr_uid35_fpSqrtTest_b_7_mem_ab), + .q_b(redist7_yAddr_uid35_fpSqrtTest_b_7_mem_iq), + .wren_b(), + .rden_a(), + .rden_b(), + .data_b(), + .clocken2(), + .clocken3(), + .aclr0(), + .aclr1(), + .addressstall_a(), + .addressstall_b(), + .byteena_a(), + .byteena_b(), + .eccencbypass(), + .eccencparity(), + .address2_a(), + .address2_b(), + .q_a(), + .eccstatus() + ); + assign redist7_yAddr_uid35_fpSqrtTest_b_7_mem_q = redist7_yAddr_uid35_fpSqrtTest_b_7_mem_iq[7:0]; + assign redist7_yAddr_uid35_fpSqrtTest_b_7_mem_enaOr_rst = redist7_yAddr_uid35_fpSqrtTest_b_7_enaAnd_q[0] | redist7_yAddr_uid35_fpSqrtTest_b_7_mem_reset0; + + // redist7_yAddr_uid35_fpSqrtTest_b_7_outputreg0(DELAY,163) + always @ (posedge clk) + begin + if (areset) + begin + redist7_yAddr_uid35_fpSqrtTest_b_7_outputreg0_q <= '0; + end + else if (en == 1'b1) + begin + redist7_yAddr_uid35_fpSqrtTest_b_7_outputreg0_q <= redist7_yAddr_uid35_fpSqrtTest_b_7_mem_q; + end + end + + // memoryC1_uid91_sqrtTables_lutmem(DUALMEM,119)@7 + 2 + // in j@20000000 + assign memoryC1_uid91_sqrtTables_lutmem_aa = redist7_yAddr_uid35_fpSqrtTest_b_7_outputreg0_q; + assign memoryC1_uid91_sqrtTables_lutmem_reset0 = areset; + altera_syncram #( + .ram_block_type("M20K"), + .operation_mode("ROM"), + .width_a(21), + .widthad_a(8), + .numwords_a(256), + .lpm_type("altera_syncram"), + .width_byteena_a(1), + .outdata_reg_a("CLOCK0"), + .outdata_sclr_a("SCLEAR"), + .clock_enable_input_a("NORMAL"), + .power_up_uninitialized("FALSE"), + .init_file("acl_fsqrt_memoryC1_uid91_sqrtTables_lutmem.hex"), + .init_file_layout("PORT_A"), + .intended_device_family("Stratix 10") + ) memoryC1_uid91_sqrtTables_lutmem_dmem ( + .clocken0(en[0]), + .sclr(memoryC1_uid91_sqrtTables_lutmem_reset0), + .clock0(clk), + .address_a(memoryC1_uid91_sqrtTables_lutmem_aa), + .q_a(memoryC1_uid91_sqrtTables_lutmem_ir), + .wren_a(), + .wren_b(), + .rden_a(), + .rden_b(), + .data_a(), + .data_b(), + .address_b(), + .clock1(), + .clocken1(), + .clocken2(), + .clocken3(), + .aclr0(), + .aclr1(), + .addressstall_a(), + .addressstall_b(), + .byteena_a(), + .byteena_b(), + .eccencbypass(), + .eccencparity(), + .address2_a(), + .address2_b(), + .q_b(), + .eccstatus() + ); + assign memoryC1_uid91_sqrtTables_lutmem_r = memoryC1_uid91_sqrtTables_lutmem_ir[20:0]; + assign memoryC1_uid91_sqrtTables_lutmem_enaOr_rst = en[0] | memoryC1_uid91_sqrtTables_lutmem_reset0; + + // s1sumAHighB_uid104_invPolyEval(ADD,103)@9 + 1 + assign s1sumAHighB_uid104_invPolyEval_a = {{1{memoryC1_uid91_sqrtTables_lutmem_r[20]}}, memoryC1_uid91_sqrtTables_lutmem_r}; + assign s1sumAHighB_uid104_invPolyEval_b = {{10{highBBits_uid103_invPolyEval_b[11]}}, highBBits_uid103_invPolyEval_b}; + always @ (posedge clk) + begin + if (areset) + begin + s1sumAHighB_uid104_invPolyEval_o <= 22'b0; + end + else if (en == 1'b1) + begin + s1sumAHighB_uid104_invPolyEval_o <= $signed(s1sumAHighB_uid104_invPolyEval_a) + $signed(s1sumAHighB_uid104_invPolyEval_b); + end + end + assign s1sumAHighB_uid104_invPolyEval_q = s1sumAHighB_uid104_invPolyEval_o[21:0]; + + // lowRangeB_uid102_invPolyEval(BITSELECT,101)@9 + assign lowRangeB_uid102_invPolyEval_in = osig_uid114_pT1_uid101_invPolyEval_b[0:0]; + assign lowRangeB_uid102_invPolyEval_b = lowRangeB_uid102_invPolyEval_in[0:0]; + + // redist2_lowRangeB_uid102_invPolyEval_b_1(DELAY,127) + always @ (posedge clk) + begin + if (areset) + begin + redist2_lowRangeB_uid102_invPolyEval_b_1_q <= '0; + end + else if (en == 1'b1) + begin + redist2_lowRangeB_uid102_invPolyEval_b_1_q <= lowRangeB_uid102_invPolyEval_b; + end + end + + // s1_uid105_invPolyEval(BITJOIN,104)@10 + assign s1_uid105_invPolyEval_q = {s1sumAHighB_uid104_invPolyEval_q, redist2_lowRangeB_uid102_invPolyEval_b_1_q}; + + // redist6_yForPe_uid36_fpSqrtTest_b_7_notEnable(LOGICAL,159) + assign redist6_yForPe_uid36_fpSqrtTest_b_7_notEnable_q = ~ (en); + + // redist6_yForPe_uid36_fpSqrtTest_b_7_nor(LOGICAL,160) + assign redist6_yForPe_uid36_fpSqrtTest_b_7_nor_q = ~ (redist6_yForPe_uid36_fpSqrtTest_b_7_notEnable_q | redist6_yForPe_uid36_fpSqrtTest_b_7_sticky_ena_q); + + // redist6_yForPe_uid36_fpSqrtTest_b_7_mem_last(CONSTANT,156) + assign redist6_yForPe_uid36_fpSqrtTest_b_7_mem_last_q = 3'b011; + + // redist6_yForPe_uid36_fpSqrtTest_b_7_cmp(LOGICAL,157) + assign redist6_yForPe_uid36_fpSqrtTest_b_7_cmp_q = redist6_yForPe_uid36_fpSqrtTest_b_7_mem_last_q == redist6_yForPe_uid36_fpSqrtTest_b_7_rdmux_q ? 1'b1 : 1'b0; + + // redist6_yForPe_uid36_fpSqrtTest_b_7_cmpReg(REG,158) + always @ (posedge clk) + begin + if (areset) + begin + redist6_yForPe_uid36_fpSqrtTest_b_7_cmpReg_q <= 1'b0; + end + else if (en == 1'b1) + begin + redist6_yForPe_uid36_fpSqrtTest_b_7_cmpReg_q <= redist6_yForPe_uid36_fpSqrtTest_b_7_cmp_q; + end + end + + // redist6_yForPe_uid36_fpSqrtTest_b_7_sticky_ena(REG,161) + always @ (posedge clk) + begin + if (areset) + begin + redist6_yForPe_uid36_fpSqrtTest_b_7_sticky_ena_q <= 1'b0; + end + else if (redist6_yForPe_uid36_fpSqrtTest_b_7_nor_q == 1'b1) + begin + redist6_yForPe_uid36_fpSqrtTest_b_7_sticky_ena_q <= redist6_yForPe_uid36_fpSqrtTest_b_7_cmpReg_q; + end + end + + // redist6_yForPe_uid36_fpSqrtTest_b_7_enaAnd(LOGICAL,162) + assign redist6_yForPe_uid36_fpSqrtTest_b_7_enaAnd_q = redist6_yForPe_uid36_fpSqrtTest_b_7_sticky_ena_q & en; + + // redist6_yForPe_uid36_fpSqrtTest_b_7_rdcnt(COUNTER,153) + // low=0, high=4, step=1, init=0 + always @ (posedge clk) + begin + if (areset) + begin + redist6_yForPe_uid36_fpSqrtTest_b_7_rdcnt_i <= 3'd0; + redist6_yForPe_uid36_fpSqrtTest_b_7_rdcnt_eq <= 1'b0; + end + else if (en == 1'b1) + begin + if (redist6_yForPe_uid36_fpSqrtTest_b_7_rdcnt_i == 3'd3) + begin + redist6_yForPe_uid36_fpSqrtTest_b_7_rdcnt_eq <= 1'b1; + end + else + begin + redist6_yForPe_uid36_fpSqrtTest_b_7_rdcnt_eq <= 1'b0; + end + if (redist6_yForPe_uid36_fpSqrtTest_b_7_rdcnt_eq == 1'b1) + begin + redist6_yForPe_uid36_fpSqrtTest_b_7_rdcnt_i <= $unsigned(redist6_yForPe_uid36_fpSqrtTest_b_7_rdcnt_i) + $unsigned(3'd4); + end + else + begin + redist6_yForPe_uid36_fpSqrtTest_b_7_rdcnt_i <= $unsigned(redist6_yForPe_uid36_fpSqrtTest_b_7_rdcnt_i) + $unsigned(3'd1); + end + end + end + assign redist6_yForPe_uid36_fpSqrtTest_b_7_rdcnt_q = redist6_yForPe_uid36_fpSqrtTest_b_7_rdcnt_i[2:0]; + + // redist6_yForPe_uid36_fpSqrtTest_b_7_rdmux(MUX,154) + assign redist6_yForPe_uid36_fpSqrtTest_b_7_rdmux_s = en; + always @(redist6_yForPe_uid36_fpSqrtTest_b_7_rdmux_s or redist6_yForPe_uid36_fpSqrtTest_b_7_wraddr_q or redist6_yForPe_uid36_fpSqrtTest_b_7_rdcnt_q) + begin + unique case (redist6_yForPe_uid36_fpSqrtTest_b_7_rdmux_s) + 1'b0 : redist6_yForPe_uid36_fpSqrtTest_b_7_rdmux_q = redist6_yForPe_uid36_fpSqrtTest_b_7_wraddr_q; + 1'b1 : redist6_yForPe_uid36_fpSqrtTest_b_7_rdmux_q = redist6_yForPe_uid36_fpSqrtTest_b_7_rdcnt_q; + default : redist6_yForPe_uid36_fpSqrtTest_b_7_rdmux_q = 3'b0; + endcase + end + + // redist6_yForPe_uid36_fpSqrtTest_b_7_wraddr(REG,155) + always @ (posedge clk) + begin + if (areset) + begin + redist6_yForPe_uid36_fpSqrtTest_b_7_wraddr_q <= 3'b100; + end + else + begin + redist6_yForPe_uid36_fpSqrtTest_b_7_wraddr_q <= redist6_yForPe_uid36_fpSqrtTest_b_7_rdmux_q; + end + end + + // redist6_yForPe_uid36_fpSqrtTest_b_7_mem(DUALMEM,152) + assign redist6_yForPe_uid36_fpSqrtTest_b_7_mem_ia = yForPe_uid36_fpSqrtTest_b; + assign redist6_yForPe_uid36_fpSqrtTest_b_7_mem_aa = redist6_yForPe_uid36_fpSqrtTest_b_7_wraddr_q; + assign redist6_yForPe_uid36_fpSqrtTest_b_7_mem_ab = redist6_yForPe_uid36_fpSqrtTest_b_7_rdmux_q; + assign redist6_yForPe_uid36_fpSqrtTest_b_7_mem_reset0 = areset; + altera_syncram #( + .ram_block_type("MLAB"), + .operation_mode("DUAL_PORT"), + .width_a(16), + .widthad_a(3), + .numwords_a(5), + .width_b(16), + .widthad_b(3), + .numwords_b(5), + .lpm_type("altera_syncram"), + .width_byteena_a(1), + .address_reg_b("CLOCK0"), + .indata_reg_b("CLOCK0"), + .rdcontrol_reg_b("CLOCK0"), + .byteena_reg_b("CLOCK0"), + .outdata_reg_b("CLOCK1"), + .outdata_sclr_b("SCLEAR"), + .clock_enable_input_a("NORMAL"), + .clock_enable_input_b("NORMAL"), + .clock_enable_output_b("NORMAL"), + .read_during_write_mode_mixed_ports("DONT_CARE"), + .power_up_uninitialized("TRUE"), + .intended_device_family("Stratix 10") + ) redist6_yForPe_uid36_fpSqrtTest_b_7_mem_dmem ( + .clocken1(redist6_yForPe_uid36_fpSqrtTest_b_7_mem_enaOr_rst), + .clocken0(VCC_q[0]), + .clock0(clk), + .sclr(redist6_yForPe_uid36_fpSqrtTest_b_7_mem_reset0), + .clock1(clk), + .address_a(redist6_yForPe_uid36_fpSqrtTest_b_7_mem_aa), + .data_a(redist6_yForPe_uid36_fpSqrtTest_b_7_mem_ia), + .wren_a(en[0]), + .address_b(redist6_yForPe_uid36_fpSqrtTest_b_7_mem_ab), + .q_b(redist6_yForPe_uid36_fpSqrtTest_b_7_mem_iq), + .wren_b(), + .rden_a(), + .rden_b(), + .data_b(), + .clocken2(), + .clocken3(), + .aclr0(), + .aclr1(), + .addressstall_a(), + .addressstall_b(), + .byteena_a(), + .byteena_b(), + .eccencbypass(), + .eccencparity(), + .address2_a(), + .address2_b(), + .q_a(), + .eccstatus() + ); + assign redist6_yForPe_uid36_fpSqrtTest_b_7_mem_q = redist6_yForPe_uid36_fpSqrtTest_b_7_mem_iq[15:0]; + assign redist6_yForPe_uid36_fpSqrtTest_b_7_mem_enaOr_rst = redist6_yForPe_uid36_fpSqrtTest_b_7_enaAnd_q[0] | redist6_yForPe_uid36_fpSqrtTest_b_7_mem_reset0; + + // redist6_yForPe_uid36_fpSqrtTest_b_7_outputreg0(DELAY,151) + always @ (posedge clk) + begin + if (areset) + begin + redist6_yForPe_uid36_fpSqrtTest_b_7_outputreg0_q <= '0; + end + else if (en == 1'b1) + begin + redist6_yForPe_uid36_fpSqrtTest_b_7_outputreg0_q <= redist6_yForPe_uid36_fpSqrtTest_b_7_mem_q; + end + end + + // prodXY_uid116_pT2_uid107_invPolyEval_cma(CHAINMULTADD,123)@10 + 5 + // out q@16 + assign prodXY_uid116_pT2_uid107_invPolyEval_cma_reset = areset; + assign prodXY_uid116_pT2_uid107_invPolyEval_cma_ena0 = en[0] | prodXY_uid116_pT2_uid107_invPolyEval_cma_reset; + assign prodXY_uid116_pT2_uid107_invPolyEval_cma_ena1 = prodXY_uid116_pT2_uid107_invPolyEval_cma_ena0; + assign prodXY_uid116_pT2_uid107_invPolyEval_cma_ena2 = prodXY_uid116_pT2_uid107_invPolyEval_cma_ena0; + always @ (posedge clk) + begin + if (0) + begin + end + else + begin + if (en == 1'b1) + begin + prodXY_uid116_pT2_uid107_invPolyEval_cma_ah[0] <= redist6_yForPe_uid36_fpSqrtTest_b_7_outputreg0_q; + prodXY_uid116_pT2_uid107_invPolyEval_cma_ch[0] <= s1_uid105_invPolyEval_q; + end + end + end + + assign prodXY_uid116_pT2_uid107_invPolyEval_cma_a0 = prodXY_uid116_pT2_uid107_invPolyEval_cma_ah[0]; + assign prodXY_uid116_pT2_uid107_invPolyEval_cma_c0 = prodXY_uid116_pT2_uid107_invPolyEval_cma_ch[0]; + fourteennm_mac #( + .operation_mode("m27x27"), + .clear_type("sclr"), + .use_chainadder("false"), + .ay_scan_in_clock("0"), + .ay_scan_in_width(16), + .ax_clock("0"), + .ax_width(23), + .signed_may("false"), + .signed_max("true"), + .input_pipeline_clock("2"), + .second_pipeline_clock("2"), + .output_clock("1"), + .result_a_width(39) + ) prodXY_uid116_pT2_uid107_invPolyEval_cma_DSP0 ( + .clk({clk,clk,clk}), + .ena({ prodXY_uid116_pT2_uid107_invPolyEval_cma_ena2, prodXY_uid116_pT2_uid107_invPolyEval_cma_ena1, prodXY_uid116_pT2_uid107_invPolyEval_cma_ena0 }), + .clr({ prodXY_uid116_pT2_uid107_invPolyEval_cma_reset, prodXY_uid116_pT2_uid107_invPolyEval_cma_reset }), + .ay(prodXY_uid116_pT2_uid107_invPolyEval_cma_a0), + .ax(prodXY_uid116_pT2_uid107_invPolyEval_cma_c0), + .resulta(prodXY_uid116_pT2_uid107_invPolyEval_cma_s0), + .accumulate(), + .loadconst(), + .negate(), + .sub(), + .az(), + .coefsela(), + .bx(), + .by(), + .bz(), + .coefselb(), + .scanin(), + .scanout(), + .chainin(), + .chainout(), + .resultb(), + .dfxlfsrena(), + .dfxmisrena(), + .dftout() + ); + dspba_delay_ver #( .width(39), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1) ) + prodXY_uid116_pT2_uid107_invPolyEval_cma_delay ( .xin(prodXY_uid116_pT2_uid107_invPolyEval_cma_s0), .xout(prodXY_uid116_pT2_uid107_invPolyEval_cma_qq), .ena(en[0]), .clk(clk), .aclr(areset) ); + assign prodXY_uid116_pT2_uid107_invPolyEval_cma_q = prodXY_uid116_pT2_uid107_invPolyEval_cma_qq[38:0]; + + // osig_uid117_pT2_uid107_invPolyEval(BITSELECT,116)@16 + assign osig_uid117_pT2_uid107_invPolyEval_b = prodXY_uid116_pT2_uid107_invPolyEval_cma_q[38:15]; + + // highBBits_uid109_invPolyEval(BITSELECT,108)@16 + assign highBBits_uid109_invPolyEval_b = osig_uid117_pT2_uid107_invPolyEval_b[23:2]; + + // redist8_yAddr_uid35_fpSqrtTest_b_14_notEnable(LOGICAL,183) + assign redist8_yAddr_uid35_fpSqrtTest_b_14_notEnable_q = ~ (en); + + // redist8_yAddr_uid35_fpSqrtTest_b_14_nor(LOGICAL,184) + assign redist8_yAddr_uid35_fpSqrtTest_b_14_nor_q = ~ (redist8_yAddr_uid35_fpSqrtTest_b_14_notEnable_q | redist8_yAddr_uid35_fpSqrtTest_b_14_sticky_ena_q); + + // redist8_yAddr_uid35_fpSqrtTest_b_14_mem_last(CONSTANT,180) + assign redist8_yAddr_uid35_fpSqrtTest_b_14_mem_last_q = 3'b011; + + // redist8_yAddr_uid35_fpSqrtTest_b_14_cmp(LOGICAL,181) + assign redist8_yAddr_uid35_fpSqrtTest_b_14_cmp_q = redist8_yAddr_uid35_fpSqrtTest_b_14_mem_last_q == redist8_yAddr_uid35_fpSqrtTest_b_14_rdmux_q ? 1'b1 : 1'b0; + + // redist8_yAddr_uid35_fpSqrtTest_b_14_cmpReg(REG,182) + always @ (posedge clk) + begin + if (areset) + begin + redist8_yAddr_uid35_fpSqrtTest_b_14_cmpReg_q <= 1'b0; + end + else if (en == 1'b1) + begin + redist8_yAddr_uid35_fpSqrtTest_b_14_cmpReg_q <= redist8_yAddr_uid35_fpSqrtTest_b_14_cmp_q; + end + end + + // redist8_yAddr_uid35_fpSqrtTest_b_14_sticky_ena(REG,185) + always @ (posedge clk) + begin + if (areset) + begin + redist8_yAddr_uid35_fpSqrtTest_b_14_sticky_ena_q <= 1'b0; + end + else if (redist8_yAddr_uid35_fpSqrtTest_b_14_nor_q == 1'b1) + begin + redist8_yAddr_uid35_fpSqrtTest_b_14_sticky_ena_q <= redist8_yAddr_uid35_fpSqrtTest_b_14_cmpReg_q; + end + end + + // redist8_yAddr_uid35_fpSqrtTest_b_14_enaAnd(LOGICAL,186) + assign redist8_yAddr_uid35_fpSqrtTest_b_14_enaAnd_q = redist8_yAddr_uid35_fpSqrtTest_b_14_sticky_ena_q & en; + + // redist8_yAddr_uid35_fpSqrtTest_b_14_rdcnt(COUNTER,177) + // low=0, high=4, step=1, init=0 + always @ (posedge clk) + begin + if (areset) + begin + redist8_yAddr_uid35_fpSqrtTest_b_14_rdcnt_i <= 3'd0; + redist8_yAddr_uid35_fpSqrtTest_b_14_rdcnt_eq <= 1'b0; + end + else if (en == 1'b1) + begin + if (redist8_yAddr_uid35_fpSqrtTest_b_14_rdcnt_i == 3'd3) + begin + redist8_yAddr_uid35_fpSqrtTest_b_14_rdcnt_eq <= 1'b1; + end + else + begin + redist8_yAddr_uid35_fpSqrtTest_b_14_rdcnt_eq <= 1'b0; + end + if (redist8_yAddr_uid35_fpSqrtTest_b_14_rdcnt_eq == 1'b1) + begin + redist8_yAddr_uid35_fpSqrtTest_b_14_rdcnt_i <= $unsigned(redist8_yAddr_uid35_fpSqrtTest_b_14_rdcnt_i) + $unsigned(3'd4); + end + else + begin + redist8_yAddr_uid35_fpSqrtTest_b_14_rdcnt_i <= $unsigned(redist8_yAddr_uid35_fpSqrtTest_b_14_rdcnt_i) + $unsigned(3'd1); + end + end + end + assign redist8_yAddr_uid35_fpSqrtTest_b_14_rdcnt_q = redist8_yAddr_uid35_fpSqrtTest_b_14_rdcnt_i[2:0]; + + // redist8_yAddr_uid35_fpSqrtTest_b_14_rdmux(MUX,178) + assign redist8_yAddr_uid35_fpSqrtTest_b_14_rdmux_s = en; + always @(redist8_yAddr_uid35_fpSqrtTest_b_14_rdmux_s or redist8_yAddr_uid35_fpSqrtTest_b_14_wraddr_q or redist8_yAddr_uid35_fpSqrtTest_b_14_rdcnt_q) + begin + unique case (redist8_yAddr_uid35_fpSqrtTest_b_14_rdmux_s) + 1'b0 : redist8_yAddr_uid35_fpSqrtTest_b_14_rdmux_q = redist8_yAddr_uid35_fpSqrtTest_b_14_wraddr_q; + 1'b1 : redist8_yAddr_uid35_fpSqrtTest_b_14_rdmux_q = redist8_yAddr_uid35_fpSqrtTest_b_14_rdcnt_q; + default : redist8_yAddr_uid35_fpSqrtTest_b_14_rdmux_q = 3'b0; + endcase + end + + // redist8_yAddr_uid35_fpSqrtTest_b_14_wraddr(REG,179) + always @ (posedge clk) + begin + if (areset) + begin + redist8_yAddr_uid35_fpSqrtTest_b_14_wraddr_q <= 3'b100; + end + else + begin + redist8_yAddr_uid35_fpSqrtTest_b_14_wraddr_q <= redist8_yAddr_uid35_fpSqrtTest_b_14_rdmux_q; + end + end + + // redist8_yAddr_uid35_fpSqrtTest_b_14_mem(DUALMEM,176) + assign redist8_yAddr_uid35_fpSqrtTest_b_14_mem_ia = redist7_yAddr_uid35_fpSqrtTest_b_7_outputreg0_q; + assign redist8_yAddr_uid35_fpSqrtTest_b_14_mem_aa = redist8_yAddr_uid35_fpSqrtTest_b_14_wraddr_q; + assign redist8_yAddr_uid35_fpSqrtTest_b_14_mem_ab = redist8_yAddr_uid35_fpSqrtTest_b_14_rdmux_q; + assign redist8_yAddr_uid35_fpSqrtTest_b_14_mem_reset0 = areset; + altera_syncram #( + .ram_block_type("MLAB"), + .operation_mode("DUAL_PORT"), + .width_a(8), + .widthad_a(3), + .numwords_a(5), + .width_b(8), + .widthad_b(3), + .numwords_b(5), + .lpm_type("altera_syncram"), + .width_byteena_a(1), + .address_reg_b("CLOCK0"), + .indata_reg_b("CLOCK0"), + .rdcontrol_reg_b("CLOCK0"), + .byteena_reg_b("CLOCK0"), + .outdata_reg_b("CLOCK1"), + .outdata_sclr_b("SCLEAR"), + .clock_enable_input_a("NORMAL"), + .clock_enable_input_b("NORMAL"), + .clock_enable_output_b("NORMAL"), + .read_during_write_mode_mixed_ports("DONT_CARE"), + .power_up_uninitialized("TRUE"), + .intended_device_family("Stratix 10") + ) redist8_yAddr_uid35_fpSqrtTest_b_14_mem_dmem ( + .clocken1(redist8_yAddr_uid35_fpSqrtTest_b_14_mem_enaOr_rst), + .clocken0(VCC_q[0]), + .clock0(clk), + .sclr(redist8_yAddr_uid35_fpSqrtTest_b_14_mem_reset0), + .clock1(clk), + .address_a(redist8_yAddr_uid35_fpSqrtTest_b_14_mem_aa), + .data_a(redist8_yAddr_uid35_fpSqrtTest_b_14_mem_ia), + .wren_a(en[0]), + .address_b(redist8_yAddr_uid35_fpSqrtTest_b_14_mem_ab), + .q_b(redist8_yAddr_uid35_fpSqrtTest_b_14_mem_iq), + .wren_b(), + .rden_a(), + .rden_b(), + .data_b(), + .clocken2(), + .clocken3(), + .aclr0(), + .aclr1(), + .addressstall_a(), + .addressstall_b(), + .byteena_a(), + .byteena_b(), + .eccencbypass(), + .eccencparity(), + .address2_a(), + .address2_b(), + .q_a(), + .eccstatus() + ); + assign redist8_yAddr_uid35_fpSqrtTest_b_14_mem_q = redist8_yAddr_uid35_fpSqrtTest_b_14_mem_iq[7:0]; + assign redist8_yAddr_uid35_fpSqrtTest_b_14_mem_enaOr_rst = redist8_yAddr_uid35_fpSqrtTest_b_14_enaAnd_q[0] | redist8_yAddr_uid35_fpSqrtTest_b_14_mem_reset0; + + // redist8_yAddr_uid35_fpSqrtTest_b_14_outputreg0(DELAY,175) + always @ (posedge clk) + begin + if (areset) + begin + redist8_yAddr_uid35_fpSqrtTest_b_14_outputreg0_q <= '0; + end + else if (en == 1'b1) + begin + redist8_yAddr_uid35_fpSqrtTest_b_14_outputreg0_q <= redist8_yAddr_uid35_fpSqrtTest_b_14_mem_q; + end + end + + // memoryC0_uid88_sqrtTables_lutmem(DUALMEM,118)@14 + 2 + // in j@20000000 + assign memoryC0_uid88_sqrtTables_lutmem_aa = redist8_yAddr_uid35_fpSqrtTest_b_14_outputreg0_q; + assign memoryC0_uid88_sqrtTables_lutmem_reset0 = areset; + altera_syncram #( + .ram_block_type("M20K"), + .operation_mode("ROM"), + .width_a(29), + .widthad_a(8), + .numwords_a(256), + .lpm_type("altera_syncram"), + .width_byteena_a(1), + .outdata_reg_a("CLOCK0"), + .outdata_sclr_a("SCLEAR"), + .clock_enable_input_a("NORMAL"), + .power_up_uninitialized("FALSE"), + .init_file("acl_fsqrt_memoryC0_uid88_sqrtTables_lutmem.hex"), + .init_file_layout("PORT_A"), + .intended_device_family("Stratix 10") + ) memoryC0_uid88_sqrtTables_lutmem_dmem ( + .clocken0(en[0]), + .sclr(memoryC0_uid88_sqrtTables_lutmem_reset0), + .clock0(clk), + .address_a(memoryC0_uid88_sqrtTables_lutmem_aa), + .q_a(memoryC0_uid88_sqrtTables_lutmem_ir), + .wren_a(), + .wren_b(), + .rden_a(), + .rden_b(), + .data_a(), + .data_b(), + .address_b(), + .clock1(), + .clocken1(), + .clocken2(), + .clocken3(), + .aclr0(), + .aclr1(), + .addressstall_a(), + .addressstall_b(), + .byteena_a(), + .byteena_b(), + .eccencbypass(), + .eccencparity(), + .address2_a(), + .address2_b(), + .q_b(), + .eccstatus() + ); + assign memoryC0_uid88_sqrtTables_lutmem_r = memoryC0_uid88_sqrtTables_lutmem_ir[28:0]; + assign memoryC0_uid88_sqrtTables_lutmem_enaOr_rst = en[0] | memoryC0_uid88_sqrtTables_lutmem_reset0; + + // s2sumAHighB_uid110_invPolyEval(ADD,109)@16 + assign s2sumAHighB_uid110_invPolyEval_a = {{1{memoryC0_uid88_sqrtTables_lutmem_r[28]}}, memoryC0_uid88_sqrtTables_lutmem_r}; + assign s2sumAHighB_uid110_invPolyEval_b = {{8{highBBits_uid109_invPolyEval_b[21]}}, highBBits_uid109_invPolyEval_b}; + assign s2sumAHighB_uid110_invPolyEval_o = $signed(s2sumAHighB_uid110_invPolyEval_a) + $signed(s2sumAHighB_uid110_invPolyEval_b); + assign s2sumAHighB_uid110_invPolyEval_q = s2sumAHighB_uid110_invPolyEval_o[29:0]; + + // lowRangeB_uid108_invPolyEval(BITSELECT,107)@16 + assign lowRangeB_uid108_invPolyEval_in = osig_uid117_pT2_uid107_invPolyEval_b[1:0]; + assign lowRangeB_uid108_invPolyEval_b = lowRangeB_uid108_invPolyEval_in[1:0]; + + // s2_uid111_invPolyEval(BITJOIN,110)@16 + assign s2_uid111_invPolyEval_q = {s2sumAHighB_uid110_invPolyEval_q, lowRangeB_uid108_invPolyEval_b}; + + // fracRPreCR_uid39_fpSqrtTest(BITSELECT,38)@16 + assign fracRPreCR_uid39_fpSqrtTest_in = s2_uid111_invPolyEval_q[28:0]; + assign fracRPreCR_uid39_fpSqrtTest_b = fracRPreCR_uid39_fpSqrtTest_in[28:5]; + + // redist3_fracRPreCR_uid39_fpSqrtTest_b_1(DELAY,128) + always @ (posedge clk) + begin + if (areset) + begin + redist3_fracRPreCR_uid39_fpSqrtTest_b_1_q <= '0; + end + else if (en == 1'b1) + begin + redist3_fracRPreCR_uid39_fpSqrtTest_b_1_q <= fracRPreCR_uid39_fpSqrtTest_b; + end + end + + // fracPaddingOne_uid41_fpSqrtTest(BITJOIN,40)@17 + assign fracPaddingOne_uid41_fpSqrtTest_q = {VCC_q, redist3_fracRPreCR_uid39_fpSqrtTest_b_1_q}; + + // squaredResult_uid42_fpSqrtTest_cma(CHAINMULTADD,121)@17 + 5 + // out q@23 + assign squaredResult_uid42_fpSqrtTest_cma_reset = areset; + assign squaredResult_uid42_fpSqrtTest_cma_ena0 = en[0] | squaredResult_uid42_fpSqrtTest_cma_reset; + assign squaredResult_uid42_fpSqrtTest_cma_ena1 = squaredResult_uid42_fpSqrtTest_cma_ena0; + assign squaredResult_uid42_fpSqrtTest_cma_ena2 = squaredResult_uid42_fpSqrtTest_cma_ena0; + always @ (posedge clk) + begin + if (0) + begin + end + else + begin + if (en == 1'b1) + begin + squaredResult_uid42_fpSqrtTest_cma_ah[0] <= fracPaddingOne_uid41_fpSqrtTest_q; + squaredResult_uid42_fpSqrtTest_cma_ch[0] <= fracPaddingOne_uid41_fpSqrtTest_q; + end + end + end + + assign squaredResult_uid42_fpSqrtTest_cma_a0 = squaredResult_uid42_fpSqrtTest_cma_ah[0]; + assign squaredResult_uid42_fpSqrtTest_cma_c0 = squaredResult_uid42_fpSqrtTest_cma_ch[0]; + fourteennm_mac #( + .operation_mode("m27x27"), + .clear_type("sclr"), + .use_chainadder("false"), + .ay_scan_in_clock("0"), + .ay_scan_in_width(25), + .ax_clock("0"), + .ax_width(25), + .signed_may("false"), + .signed_max("false"), + .input_pipeline_clock("2"), + .second_pipeline_clock("2"), + .output_clock("1"), + .result_a_width(50) + ) squaredResult_uid42_fpSqrtTest_cma_DSP0 ( + .clk({clk,clk,clk}), + .ena({ squaredResult_uid42_fpSqrtTest_cma_ena2, squaredResult_uid42_fpSqrtTest_cma_ena1, squaredResult_uid42_fpSqrtTest_cma_ena0 }), + .clr({ squaredResult_uid42_fpSqrtTest_cma_reset, squaredResult_uid42_fpSqrtTest_cma_reset }), + .ay(squaredResult_uid42_fpSqrtTest_cma_a0), + .ax(squaredResult_uid42_fpSqrtTest_cma_c0), + .resulta(squaredResult_uid42_fpSqrtTest_cma_s0), + .accumulate(), + .loadconst(), + .negate(), + .sub(), + .az(), + .coefsela(), + .bx(), + .by(), + .bz(), + .coefselb(), + .scanin(), + .scanout(), + .chainin(), + .chainout(), + .resultb(), + .dfxlfsrena(), + .dfxmisrena(), + .dftout() + ); + dspba_delay_ver #( .width(50), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1) ) + squaredResult_uid42_fpSqrtTest_cma_delay ( .xin(squaredResult_uid42_fpSqrtTest_cma_s0), .xout(squaredResult_uid42_fpSqrtTest_cma_qq), .ena(en[0]), .clk(clk), .aclr(areset) ); + assign squaredResult_uid42_fpSqrtTest_cma_q = squaredResult_uid42_fpSqrtTest_cma_qq[49:0]; + + // squaredResultGTEIn_uid55_fpSqrtTest(COMPARE,56)@23 + 1 + assign squaredResultGTEIn_uid55_fpSqrtTest_a = {2'b00, squaredResult_uid42_fpSqrtTest_cma_q}; + assign squaredResultGTEIn_uid55_fpSqrtTest_b = {2'b00, updatedY_uid56_fpSqrtTest_q}; + always @ (posedge clk) + begin + if (areset) + begin + squaredResultGTEIn_uid55_fpSqrtTest_o <= 52'b0; + end + else if (en == 1'b1) + begin + squaredResultGTEIn_uid55_fpSqrtTest_o <= $unsigned(squaredResultGTEIn_uid55_fpSqrtTest_a) - $unsigned(squaredResultGTEIn_uid55_fpSqrtTest_b); + end + end + assign squaredResultGTEIn_uid55_fpSqrtTest_n[0] = ~ (squaredResultGTEIn_uid55_fpSqrtTest_o[51]); + + // pLTOne_uid58_fpSqrtTest(LOGICAL,57)@24 + assign pLTOne_uid58_fpSqrtTest_q = ~ (squaredResultGTEIn_uid55_fpSqrtTest_n); + + // redist4_fracRPreCR_uid39_fpSqrtTest_b_8_notEnable(LOGICAL,147) + assign redist4_fracRPreCR_uid39_fpSqrtTest_b_8_notEnable_q = ~ (en); + + // redist4_fracRPreCR_uid39_fpSqrtTest_b_8_nor(LOGICAL,148) + assign redist4_fracRPreCR_uid39_fpSqrtTest_b_8_nor_q = ~ (redist4_fracRPreCR_uid39_fpSqrtTest_b_8_notEnable_q | redist4_fracRPreCR_uid39_fpSqrtTest_b_8_sticky_ena_q); + + // redist4_fracRPreCR_uid39_fpSqrtTest_b_8_mem_last(CONSTANT,144) + assign redist4_fracRPreCR_uid39_fpSqrtTest_b_8_mem_last_q = 4'b0100; + + // redist4_fracRPreCR_uid39_fpSqrtTest_b_8_cmp(LOGICAL,145) + assign redist4_fracRPreCR_uid39_fpSqrtTest_b_8_cmp_b = {1'b0, redist4_fracRPreCR_uid39_fpSqrtTest_b_8_rdmux_q}; + assign redist4_fracRPreCR_uid39_fpSqrtTest_b_8_cmp_q = redist4_fracRPreCR_uid39_fpSqrtTest_b_8_mem_last_q == redist4_fracRPreCR_uid39_fpSqrtTest_b_8_cmp_b ? 1'b1 : 1'b0; + + // redist4_fracRPreCR_uid39_fpSqrtTest_b_8_cmpReg(REG,146) + always @ (posedge clk) + begin + if (areset) + begin + redist4_fracRPreCR_uid39_fpSqrtTest_b_8_cmpReg_q <= 1'b0; + end + else if (en == 1'b1) + begin + redist4_fracRPreCR_uid39_fpSqrtTest_b_8_cmpReg_q <= redist4_fracRPreCR_uid39_fpSqrtTest_b_8_cmp_q; + end + end + + // redist4_fracRPreCR_uid39_fpSqrtTest_b_8_sticky_ena(REG,149) + always @ (posedge clk) + begin + if (areset) + begin + redist4_fracRPreCR_uid39_fpSqrtTest_b_8_sticky_ena_q <= 1'b0; + end + else if (redist4_fracRPreCR_uid39_fpSqrtTest_b_8_nor_q == 1'b1) + begin + redist4_fracRPreCR_uid39_fpSqrtTest_b_8_sticky_ena_q <= redist4_fracRPreCR_uid39_fpSqrtTest_b_8_cmpReg_q; + end + end + + // redist4_fracRPreCR_uid39_fpSqrtTest_b_8_enaAnd(LOGICAL,150) + assign redist4_fracRPreCR_uid39_fpSqrtTest_b_8_enaAnd_q = redist4_fracRPreCR_uid39_fpSqrtTest_b_8_sticky_ena_q & en; + + // redist4_fracRPreCR_uid39_fpSqrtTest_b_8_rdcnt(COUNTER,141) + // low=0, high=5, step=1, init=0 + always @ (posedge clk) + begin + if (areset) + begin + redist4_fracRPreCR_uid39_fpSqrtTest_b_8_rdcnt_i <= 3'd0; + redist4_fracRPreCR_uid39_fpSqrtTest_b_8_rdcnt_eq <= 1'b0; + end + else if (en == 1'b1) + begin + if (redist4_fracRPreCR_uid39_fpSqrtTest_b_8_rdcnt_i == 3'd4) + begin + redist4_fracRPreCR_uid39_fpSqrtTest_b_8_rdcnt_eq <= 1'b1; + end + else + begin + redist4_fracRPreCR_uid39_fpSqrtTest_b_8_rdcnt_eq <= 1'b0; + end + if (redist4_fracRPreCR_uid39_fpSqrtTest_b_8_rdcnt_eq == 1'b1) + begin + redist4_fracRPreCR_uid39_fpSqrtTest_b_8_rdcnt_i <= $unsigned(redist4_fracRPreCR_uid39_fpSqrtTest_b_8_rdcnt_i) + $unsigned(3'd3); + end + else + begin + redist4_fracRPreCR_uid39_fpSqrtTest_b_8_rdcnt_i <= $unsigned(redist4_fracRPreCR_uid39_fpSqrtTest_b_8_rdcnt_i) + $unsigned(3'd1); + end + end + end + assign redist4_fracRPreCR_uid39_fpSqrtTest_b_8_rdcnt_q = redist4_fracRPreCR_uid39_fpSqrtTest_b_8_rdcnt_i[2:0]; + + // redist4_fracRPreCR_uid39_fpSqrtTest_b_8_rdmux(MUX,142) + assign redist4_fracRPreCR_uid39_fpSqrtTest_b_8_rdmux_s = en; + always @(redist4_fracRPreCR_uid39_fpSqrtTest_b_8_rdmux_s or redist4_fracRPreCR_uid39_fpSqrtTest_b_8_wraddr_q or redist4_fracRPreCR_uid39_fpSqrtTest_b_8_rdcnt_q) + begin + unique case (redist4_fracRPreCR_uid39_fpSqrtTest_b_8_rdmux_s) + 1'b0 : redist4_fracRPreCR_uid39_fpSqrtTest_b_8_rdmux_q = redist4_fracRPreCR_uid39_fpSqrtTest_b_8_wraddr_q; + 1'b1 : redist4_fracRPreCR_uid39_fpSqrtTest_b_8_rdmux_q = redist4_fracRPreCR_uid39_fpSqrtTest_b_8_rdcnt_q; + default : redist4_fracRPreCR_uid39_fpSqrtTest_b_8_rdmux_q = 3'b0; + endcase + end + + // redist4_fracRPreCR_uid39_fpSqrtTest_b_8_wraddr(REG,143) + always @ (posedge clk) + begin + if (areset) + begin + redist4_fracRPreCR_uid39_fpSqrtTest_b_8_wraddr_q <= 3'b101; + end + else + begin + redist4_fracRPreCR_uid39_fpSqrtTest_b_8_wraddr_q <= redist4_fracRPreCR_uid39_fpSqrtTest_b_8_rdmux_q; + end + end + + // redist4_fracRPreCR_uid39_fpSqrtTest_b_8_mem(DUALMEM,140) + assign redist4_fracRPreCR_uid39_fpSqrtTest_b_8_mem_ia = redist3_fracRPreCR_uid39_fpSqrtTest_b_1_q; + assign redist4_fracRPreCR_uid39_fpSqrtTest_b_8_mem_aa = redist4_fracRPreCR_uid39_fpSqrtTest_b_8_wraddr_q; + assign redist4_fracRPreCR_uid39_fpSqrtTest_b_8_mem_ab = redist4_fracRPreCR_uid39_fpSqrtTest_b_8_rdmux_q; + assign redist4_fracRPreCR_uid39_fpSqrtTest_b_8_mem_reset0 = areset; + altera_syncram #( + .ram_block_type("MLAB"), + .operation_mode("DUAL_PORT"), + .width_a(24), + .widthad_a(3), + .numwords_a(6), + .width_b(24), + .widthad_b(3), + .numwords_b(6), + .lpm_type("altera_syncram"), + .width_byteena_a(1), + .address_reg_b("CLOCK0"), + .indata_reg_b("CLOCK0"), + .rdcontrol_reg_b("CLOCK0"), + .byteena_reg_b("CLOCK0"), + .outdata_reg_b("CLOCK1"), + .outdata_sclr_b("SCLEAR"), + .clock_enable_input_a("NORMAL"), + .clock_enable_input_b("NORMAL"), + .clock_enable_output_b("NORMAL"), + .read_during_write_mode_mixed_ports("DONT_CARE"), + .power_up_uninitialized("TRUE"), + .intended_device_family("Stratix 10") + ) redist4_fracRPreCR_uid39_fpSqrtTest_b_8_mem_dmem ( + .clocken1(redist4_fracRPreCR_uid39_fpSqrtTest_b_8_mem_enaOr_rst), + .clocken0(VCC_q[0]), + .clock0(clk), + .sclr(redist4_fracRPreCR_uid39_fpSqrtTest_b_8_mem_reset0), + .clock1(clk), + .address_a(redist4_fracRPreCR_uid39_fpSqrtTest_b_8_mem_aa), + .data_a(redist4_fracRPreCR_uid39_fpSqrtTest_b_8_mem_ia), + .wren_a(en[0]), + .address_b(redist4_fracRPreCR_uid39_fpSqrtTest_b_8_mem_ab), + .q_b(redist4_fracRPreCR_uid39_fpSqrtTest_b_8_mem_iq), + .wren_b(), + .rden_a(), + .rden_b(), + .data_b(), + .clocken2(), + .clocken3(), + .aclr0(), + .aclr1(), + .addressstall_a(), + .addressstall_b(), + .byteena_a(), + .byteena_b(), + .eccencbypass(), + .eccencparity(), + .address2_a(), + .address2_b(), + .q_a(), + .eccstatus() + ); + assign redist4_fracRPreCR_uid39_fpSqrtTest_b_8_mem_q = redist4_fracRPreCR_uid39_fpSqrtTest_b_8_mem_iq[23:0]; + assign redist4_fracRPreCR_uid39_fpSqrtTest_b_8_mem_enaOr_rst = redist4_fracRPreCR_uid39_fpSqrtTest_b_8_enaAnd_q[0] | redist4_fracRPreCR_uid39_fpSqrtTest_b_8_mem_reset0; + + // fxpSqrtResPostUpdateE_uid60_fpSqrtTest(ADD,59)@24 + assign fxpSqrtResPostUpdateE_uid60_fpSqrtTest_a = {1'b0, redist4_fracRPreCR_uid39_fpSqrtTest_b_8_mem_q}; + assign fxpSqrtResPostUpdateE_uid60_fpSqrtTest_b = {24'b000000000000000000000000, pLTOne_uid58_fpSqrtTest_q}; + assign fxpSqrtResPostUpdateE_uid60_fpSqrtTest_o = $unsigned(fxpSqrtResPostUpdateE_uid60_fpSqrtTest_a) + $unsigned(fxpSqrtResPostUpdateE_uid60_fpSqrtTest_b); + assign fxpSqrtResPostUpdateE_uid60_fpSqrtTest_q = fxpSqrtResPostUpdateE_uid60_fpSqrtTest_o[24:0]; + + // expUpdateCRU_uid61_fpSqrtTest_merged_bit_select(BITSELECT,124)@24 + assign expUpdateCRU_uid61_fpSqrtTest_merged_bit_select_b = fxpSqrtResPostUpdateE_uid60_fpSqrtTest_q[24:24]; + assign expUpdateCRU_uid61_fpSqrtTest_merged_bit_select_c = fxpSqrtResPostUpdateE_uid60_fpSqrtTest_q[23:1]; + + // fracPENotOne_uid62_fpSqrtTest(LOGICAL,61)@24 + assign fracPENotOne_uid62_fpSqrtTest_q = ~ (redist5_expIncPEOnly_uid38_fpSqrtTest_b_8_q); + + // fracPENotOneAndCRRoundsExp_uid63_fpSqrtTest(LOGICAL,62)@24 + assign fracPENotOneAndCRRoundsExp_uid63_fpSqrtTest_q = fracPENotOne_uid62_fpSqrtTest_q & expUpdateCRU_uid61_fpSqrtTest_merged_bit_select_b; + + // expIncPEOnly_uid38_fpSqrtTest(BITSELECT,37)@16 + assign expIncPEOnly_uid38_fpSqrtTest_in = s2_uid111_invPolyEval_q[30:0]; + assign expIncPEOnly_uid38_fpSqrtTest_b = expIncPEOnly_uid38_fpSqrtTest_in[30:30]; + + // redist5_expIncPEOnly_uid38_fpSqrtTest_b_8(DELAY,130) + dspba_delay_ver #( .width(1), .depth(8), .reset_kind("SYNC"), .phase(0), .modulus(1) ) + redist5_expIncPEOnly_uid38_fpSqrtTest_b_8 ( .xin(expIncPEOnly_uid38_fpSqrtTest_b), .xout(redist5_expIncPEOnly_uid38_fpSqrtTest_b_8_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // expInc_uid64_fpSqrtTest(LOGICAL,63)@24 + 1 + assign expInc_uid64_fpSqrtTest_qi = redist5_expIncPEOnly_uid38_fpSqrtTest_b_8_q | fracPENotOneAndCRRoundsExp_uid63_fpSqrtTest_q; + dspba_delay_ver #( .width(1), .depth(1), .reset_kind("SYNC"), .phase(0), .modulus(1) ) + expInc_uid64_fpSqrtTest_delay ( .xin(expInc_uid64_fpSqrtTest_qi), .xout(expInc_uid64_fpSqrtTest_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // sBiasM1_uid26_fpSqrtTest(CONSTANT,25) + assign sBiasM1_uid26_fpSqrtTest_q = 8'b01111110; + + // expOddSig_uid27_fpSqrtTest(ADD,26)@23 + assign expOddSig_uid27_fpSqrtTest_a = {1'b0, redist14_expX_uid6_fpSqrtTest_b_23_mem_q}; + assign expOddSig_uid27_fpSqrtTest_b = {1'b0, sBiasM1_uid26_fpSqrtTest_q}; + assign expOddSig_uid27_fpSqrtTest_o = $unsigned(expOddSig_uid27_fpSqrtTest_a) + $unsigned(expOddSig_uid27_fpSqrtTest_b); + assign expOddSig_uid27_fpSqrtTest_q = expOddSig_uid27_fpSqrtTest_o[8:0]; + + // expROdd_uid28_fpSqrtTest(BITSELECT,27)@23 + assign expROdd_uid28_fpSqrtTest_b = expOddSig_uid27_fpSqrtTest_q[8:1]; + + // sBias_uid22_fpSqrtTest(CONSTANT,21) + assign sBias_uid22_fpSqrtTest_q = 8'b01111111; + + // expEvenSig_uid24_fpSqrtTest(ADD,23)@23 + assign expEvenSig_uid24_fpSqrtTest_a = {1'b0, redist14_expX_uid6_fpSqrtTest_b_23_mem_q}; + assign expEvenSig_uid24_fpSqrtTest_b = {1'b0, sBias_uid22_fpSqrtTest_q}; + assign expEvenSig_uid24_fpSqrtTest_o = $unsigned(expEvenSig_uid24_fpSqrtTest_a) + $unsigned(expEvenSig_uid24_fpSqrtTest_b); + assign expEvenSig_uid24_fpSqrtTest_q = expEvenSig_uid24_fpSqrtTest_o[8:0]; + + // expREven_uid25_fpSqrtTest(BITSELECT,24)@23 + assign expREven_uid25_fpSqrtTest_b = expEvenSig_uid24_fpSqrtTest_q[8:1]; + + // expRMux_uid31_fpSqrtTest(MUX,30)@23 + 1 + assign expRMux_uid31_fpSqrtTest_s = redist10_expOddSelect_uid30_fpSqrtTest_q_23_q; + always @ (posedge clk) + begin + if (areset) + begin + expRMux_uid31_fpSqrtTest_q <= 8'b0; + end + else if (en == 1'b1) + begin + unique case (expRMux_uid31_fpSqrtTest_s) + 1'b0 : expRMux_uid31_fpSqrtTest_q <= expREven_uid25_fpSqrtTest_b; + 1'b1 : expRMux_uid31_fpSqrtTest_q <= expROdd_uid28_fpSqrtTest_b; + default : expRMux_uid31_fpSqrtTest_q <= 8'b0; + endcase + end + end + + // redist9_expRMux_uid31_fpSqrtTest_q_2(DELAY,134) + always @ (posedge clk) + begin + if (areset) + begin + redist9_expRMux_uid31_fpSqrtTest_q_2_q <= '0; + end + else if (en == 1'b1) + begin + redist9_expRMux_uid31_fpSqrtTest_q_2_q <= expRMux_uid31_fpSqrtTest_q; + end + end + + // expR_uid66_fpSqrtTest(ADD,65)@25 + assign expR_uid66_fpSqrtTest_a = {1'b0, redist9_expRMux_uid31_fpSqrtTest_q_2_q}; + assign expR_uid66_fpSqrtTest_b = {8'b00000000, expInc_uid64_fpSqrtTest_q}; + assign expR_uid66_fpSqrtTest_o = $unsigned(expR_uid66_fpSqrtTest_a) + $unsigned(expR_uid66_fpSqrtTest_b); + assign expR_uid66_fpSqrtTest_q = expR_uid66_fpSqrtTest_o[8:0]; + + // expRR_uid77_fpSqrtTest(BITSELECT,76)@25 + assign expRR_uid77_fpSqrtTest_in = expR_uid66_fpSqrtTest_q[7:0]; + assign expRR_uid77_fpSqrtTest_b = expRR_uid77_fpSqrtTest_in[7:0]; + + // expXIsMax_uid14_fpSqrtTest(LOGICAL,13)@23 + 1 + assign expXIsMax_uid14_fpSqrtTest_qi = redist14_expX_uid6_fpSqrtTest_b_23_mem_q == cstAllOWE_uid8_fpSqrtTest_q ? 1'b1 : 1'b0; + dspba_delay_ver #( .width(1), .depth(1), .reset_kind("SYNC"), .phase(0), .modulus(1) ) + expXIsMax_uid14_fpSqrtTest_delay ( .xin(expXIsMax_uid14_fpSqrtTest_qi), .xout(expXIsMax_uid14_fpSqrtTest_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // invExpXIsMax_uid19_fpSqrtTest(LOGICAL,18)@24 + assign invExpXIsMax_uid19_fpSqrtTest_q = ~ (expXIsMax_uid14_fpSqrtTest_q); + + // InvExpXIsZero_uid20_fpSqrtTest(LOGICAL,19)@24 + assign InvExpXIsZero_uid20_fpSqrtTest_q = ~ (excZ_x_uid13_fpSqrtTest_q); + + // excR_x_uid21_fpSqrtTest(LOGICAL,20)@24 + assign excR_x_uid21_fpSqrtTest_q = InvExpXIsZero_uid20_fpSqrtTest_q & invExpXIsMax_uid19_fpSqrtTest_q; + + // minReg_uid69_fpSqrtTest(LOGICAL,68)@24 + assign minReg_uid69_fpSqrtTest_q = excR_x_uid21_fpSqrtTest_q & redist13_signX_uid7_fpSqrtTest_b_24_q; + + // cstZeroWF_uid9_fpSqrtTest(CONSTANT,8) + assign cstZeroWF_uid9_fpSqrtTest_q = 23'b00000000000000000000000; + + // fracXIsZero_uid15_fpSqrtTest(LOGICAL,14)@23 + 1 + assign fracXIsZero_uid15_fpSqrtTest_qi = cstZeroWF_uid9_fpSqrtTest_q == redist12_frac_x_uid12_fpSqrtTest_b_23_mem_q ? 1'b1 : 1'b0; + dspba_delay_ver #( .width(1), .depth(1), .reset_kind("SYNC"), .phase(0), .modulus(1) ) + fracXIsZero_uid15_fpSqrtTest_delay ( .xin(fracXIsZero_uid15_fpSqrtTest_qi), .xout(fracXIsZero_uid15_fpSqrtTest_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // excI_x_uid17_fpSqrtTest(LOGICAL,16)@24 + assign excI_x_uid17_fpSqrtTest_q = expXIsMax_uid14_fpSqrtTest_q & fracXIsZero_uid15_fpSqrtTest_q; + + // minInf_uid70_fpSqrtTest(LOGICAL,69)@24 + assign minInf_uid70_fpSqrtTest_q = excI_x_uid17_fpSqrtTest_q & redist13_signX_uid7_fpSqrtTest_b_24_q; + + // fracXIsNotZero_uid16_fpSqrtTest(LOGICAL,15)@24 + assign fracXIsNotZero_uid16_fpSqrtTest_q = ~ (fracXIsZero_uid15_fpSqrtTest_q); + + // excN_x_uid18_fpSqrtTest(LOGICAL,17)@24 + assign excN_x_uid18_fpSqrtTest_q = expXIsMax_uid14_fpSqrtTest_q & fracXIsNotZero_uid16_fpSqrtTest_q; + + // excRNaN_uid71_fpSqrtTest(LOGICAL,70)@24 + assign excRNaN_uid71_fpSqrtTest_q = excN_x_uid18_fpSqrtTest_q | minInf_uid70_fpSqrtTest_q | minReg_uid69_fpSqrtTest_q; + + // invSignX_uid67_fpSqrtTest(LOGICAL,66)@24 + assign invSignX_uid67_fpSqrtTest_q = ~ (redist13_signX_uid7_fpSqrtTest_b_24_q); + + // inInfAndNotNeg_uid68_fpSqrtTest(LOGICAL,67)@24 + assign inInfAndNotNeg_uid68_fpSqrtTest_q = excI_x_uid17_fpSqrtTest_q & invSignX_uid67_fpSqrtTest_q; + + // excConc_uid72_fpSqrtTest(BITJOIN,71)@24 + assign excConc_uid72_fpSqrtTest_q = {excRNaN_uid71_fpSqrtTest_q, inInfAndNotNeg_uid68_fpSqrtTest_q, excZ_x_uid13_fpSqrtTest_q}; + + // fracSelIn_uid73_fpSqrtTest(BITJOIN,72)@24 + assign fracSelIn_uid73_fpSqrtTest_q = {redist13_signX_uid7_fpSqrtTest_b_24_q, excConc_uid72_fpSqrtTest_q}; + + // fracSel_uid74_fpSqrtTest(LOOKUP,73)@24 + 1 + always @ (posedge clk) + begin + if (areset) + begin + fracSel_uid74_fpSqrtTest_q <= 2'b01; + end + else if (en == 1'b1) + begin + unique case (fracSelIn_uid73_fpSqrtTest_q) + 4'b0000 : fracSel_uid74_fpSqrtTest_q <= 2'b01; + 4'b0001 : fracSel_uid74_fpSqrtTest_q <= 2'b00; + 4'b0010 : fracSel_uid74_fpSqrtTest_q <= 2'b10; + 4'b0011 : fracSel_uid74_fpSqrtTest_q <= 2'b00; + 4'b0100 : fracSel_uid74_fpSqrtTest_q <= 2'b11; + 4'b0101 : fracSel_uid74_fpSqrtTest_q <= 2'b00; + 4'b0110 : fracSel_uid74_fpSqrtTest_q <= 2'b10; + 4'b0111 : fracSel_uid74_fpSqrtTest_q <= 2'b00; + 4'b1000 : fracSel_uid74_fpSqrtTest_q <= 2'b11; + 4'b1001 : fracSel_uid74_fpSqrtTest_q <= 2'b00; + 4'b1010 : fracSel_uid74_fpSqrtTest_q <= 2'b11; + 4'b1011 : fracSel_uid74_fpSqrtTest_q <= 2'b11; + 4'b1100 : fracSel_uid74_fpSqrtTest_q <= 2'b11; + 4'b1101 : fracSel_uid74_fpSqrtTest_q <= 2'b11; + 4'b1110 : fracSel_uid74_fpSqrtTest_q <= 2'b11; + 4'b1111 : fracSel_uid74_fpSqrtTest_q <= 2'b11; + default : begin + // unreachable + fracSel_uid74_fpSqrtTest_q <= 2'bxx; + end + endcase + end + end + + // expRPostExc_uid79_fpSqrtTest(MUX,78)@25 + assign expRPostExc_uid79_fpSqrtTest_s = fracSel_uid74_fpSqrtTest_q; + always @(expRPostExc_uid79_fpSqrtTest_s or en or cstAllZWE_uid10_fpSqrtTest_q or expRR_uid77_fpSqrtTest_b or cstAllOWE_uid8_fpSqrtTest_q) + begin + unique case (expRPostExc_uid79_fpSqrtTest_s) + 2'b00 : expRPostExc_uid79_fpSqrtTest_q = cstAllZWE_uid10_fpSqrtTest_q; + 2'b01 : expRPostExc_uid79_fpSqrtTest_q = expRR_uid77_fpSqrtTest_b; + 2'b10 : expRPostExc_uid79_fpSqrtTest_q = cstAllOWE_uid8_fpSqrtTest_q; + 2'b11 : expRPostExc_uid79_fpSqrtTest_q = cstAllOWE_uid8_fpSqrtTest_q; + default : expRPostExc_uid79_fpSqrtTest_q = 8'b0; + endcase + end + + // fracNaN_uid80_fpSqrtTest(CONSTANT,79) + assign fracNaN_uid80_fpSqrtTest_q = 23'b00000000000000000000001; + + // redist0_expUpdateCRU_uid61_fpSqrtTest_merged_bit_select_c_1(DELAY,125) + always @ (posedge clk) + begin + if (areset) + begin + redist0_expUpdateCRU_uid61_fpSqrtTest_merged_bit_select_c_1_q <= '0; + end + else if (en == 1'b1) + begin + redist0_expUpdateCRU_uid61_fpSqrtTest_merged_bit_select_c_1_q <= expUpdateCRU_uid61_fpSqrtTest_merged_bit_select_c; + end + end + + // fracRPostExc_uid84_fpSqrtTest(MUX,83)@25 + assign fracRPostExc_uid84_fpSqrtTest_s = fracSel_uid74_fpSqrtTest_q; + always @(fracRPostExc_uid84_fpSqrtTest_s or en or cstZeroWF_uid9_fpSqrtTest_q or redist0_expUpdateCRU_uid61_fpSqrtTest_merged_bit_select_c_1_q or fracNaN_uid80_fpSqrtTest_q) + begin + unique case (fracRPostExc_uid84_fpSqrtTest_s) + 2'b00 : fracRPostExc_uid84_fpSqrtTest_q = cstZeroWF_uid9_fpSqrtTest_q; + 2'b01 : fracRPostExc_uid84_fpSqrtTest_q = redist0_expUpdateCRU_uid61_fpSqrtTest_merged_bit_select_c_1_q; + 2'b10 : fracRPostExc_uid84_fpSqrtTest_q = cstZeroWF_uid9_fpSqrtTest_q; + 2'b11 : fracRPostExc_uid84_fpSqrtTest_q = fracNaN_uid80_fpSqrtTest_q; + default : fracRPostExc_uid84_fpSqrtTest_q = 23'b0; + endcase + end + + // RSqrt_uid86_fpSqrtTest(BITJOIN,85)@25 + assign RSqrt_uid86_fpSqrtTest_q = {negZero_uid85_fpSqrtTest_q, expRPostExc_uid79_fpSqrtTest_q, fracRPostExc_uid84_fpSqrtTest_q}; + + // xOut(GPOUT,4)@25 + assign q = RSqrt_uid86_fpSqrtTest_q; + +endmodule diff --git a/hw/rtl/fp_cores/altera/stratix10/acl_fsqrt_memoryC0_uid88_sqrtTables_lutmem.hex b/hw/rtl/fp_cores/altera/stratix10/acl_fsqrt_memoryC0_uid88_sqrtTables_lutmem.hex new file mode 100644 index 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Level Design Compiler for Intel(R) FPGAs Version 18.1 (Release Build #277) +// Quartus Prime development tool and MATLAB/Simulink Interface +// +// Legal Notice: Copyright 2019 Intel Corporation. All rights reserved. +// Your use of Intel Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly +// subject to the terms and conditions of the Intel FPGA Software License +// Agreement, Intel MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for +// the sole purpose of programming logic devices manufactured by Intel +// and sold by Intel or its authorized distributors. Please refer to the +// applicable agreement for further details. +// --------------------------------------------------------------------------- + +// SystemVerilog created from acl_fsub +// SystemVerilog created on Sun Dec 27 09:48:57 2020 + + +(* altera_attribute = "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410; -name MESSAGE_DISABLE 113007; -name MESSAGE_DISABLE 10958" *) +module acl_fsub ( + input wire [31:0] a, + input wire [31:0] b, + input wire [0:0] en, + output wire [31:0] q, + input wire clk, + input wire areset + ); + + wire fpSubTest_impl_reset0; + wire fpSubTest_impl_ena0; + wire [31:0] fpSubTest_impl_ax0; + wire [31:0] fpSubTest_impl_ay0; + wire [31:0] fpSubTest_impl_q0; + + + // fpSubTest_impl(FPCOLUMN,5)@0 + // out q0@3 + assign fpSubTest_impl_ax0 = b; + assign fpSubTest_impl_ay0 = a; + assign fpSubTest_impl_reset0 = areset; + assign fpSubTest_impl_ena0 = en[0] | fpSubTest_impl_reset0; + fourteennm_fp_mac #( + .operation_mode("sp_add"), + .adder_subtract("true"), + .ax_clock("0"), + .ay_clock("0"), + .adder_input_clock("0"), + .output_clock("0"), + .clear_type("sclr") + ) fpSubTest_impl_DSP0 ( + .clk({1'b0,1'b0,clk}), + .ena({ 1'b0, 1'b0, fpSubTest_impl_ena0 }), + .clr({ fpSubTest_impl_reset0, fpSubTest_impl_reset0 }), + .ax(fpSubTest_impl_ax0), + .ay(fpSubTest_impl_ay0), + .resulta(fpSubTest_impl_q0), + .accumulate(), + .az(), + .chainin(), + .chainout() + ); + + // xOut(GPOUT,4)@3 + assign q = fpSubTest_impl_q0; + +endmodule diff --git a/hw/rtl/fp_cores/altera/stratix10/acl_ftoi.sv b/hw/rtl/fp_cores/altera/stratix10/acl_ftoi.sv new file mode 100644 index 00000000..01b08c53 --- /dev/null +++ b/hw/rtl/fp_cores/altera/stratix10/acl_ftoi.sv @@ -0,0 +1,586 @@ +// ------------------------------------------------------------------------- +// High Level Design Compiler for Intel(R) FPGAs Version 18.1 (Release Build #277) +// Quartus Prime development tool and MATLAB/Simulink Interface +// +// Legal Notice: Copyright 2019 Intel Corporation. All rights reserved. +// Your use of Intel Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly +// subject to the terms and conditions of the Intel FPGA Software License +// Agreement, Intel MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for +// the sole purpose of programming logic devices manufactured by Intel +// and sold by Intel or its authorized distributors. Please refer to the +// applicable agreement for further details. +// --------------------------------------------------------------------------- + +// SystemVerilog created from acl_ftoi +// SystemVerilog created on Sun Dec 27 09:48:58 2020 + + +(* altera_attribute = "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410; -name MESSAGE_DISABLE 113007; -name MESSAGE_DISABLE 10958" *) +module acl_ftoi ( + input wire [31:0] a, + input wire [0:0] en, + output wire [31:0] q, + input wire clk, + input wire areset + ); + + wire [0:0] GND_q; + wire [7:0] cstAllOWE_uid6_fpToFxPTest_q; + wire [22:0] cstZeroWF_uid7_fpToFxPTest_q; + wire [7:0] cstAllZWE_uid8_fpToFxPTest_q; + wire [7:0] exp_x_uid9_fpToFxPTest_b; + wire [22:0] frac_x_uid10_fpToFxPTest_b; + wire [0:0] excZ_x_uid11_fpToFxPTest_q; + wire [0:0] expXIsMax_uid12_fpToFxPTest_q; + wire [0:0] fracXIsZero_uid13_fpToFxPTest_q; + wire [0:0] fracXIsNotZero_uid14_fpToFxPTest_q; + wire [0:0] excI_x_uid15_fpToFxPTest_qi; + reg [0:0] excI_x_uid15_fpToFxPTest_q; + wire [0:0] excN_x_uid16_fpToFxPTest_q; + wire [0:0] fracPostZ_uid23_fpToFxPTest_s; + reg [22:0] fracPostZ_uid23_fpToFxPTest_q; + wire [0:0] invExcXZ_uid24_fpToFxPTest_qi; + reg [0:0] invExcXZ_uid24_fpToFxPTest_q; + wire [23:0] oFracX_uid25_fpToFxPTest_q; + wire [0:0] signX_uid27_fpToFxPTest_b; + wire [0:0] notNan_uid28_fpToFxPTest_q; + wire [0:0] signX_uid29_fpToFxPTest_qi; + reg [0:0] signX_uid29_fpToFxPTest_q; + wire [8:0] ovfExpVal_uid30_fpToFxPTest_q; + wire [10:0] ovfExpRange_uid31_fpToFxPTest_a; + wire [10:0] ovfExpRange_uid31_fpToFxPTest_b; + logic [10:0] ovfExpRange_uid31_fpToFxPTest_o; + wire [0:0] ovfExpRange_uid31_fpToFxPTest_n; + wire [7:0] udfExpVal_uid32_fpToFxPTest_q; + wire [10:0] udf_uid33_fpToFxPTest_a; + wire [10:0] udf_uid33_fpToFxPTest_b; + logic [10:0] udf_uid33_fpToFxPTest_o; + wire [0:0] udf_uid33_fpToFxPTest_n; + wire [8:0] ovfExpVal_uid34_fpToFxPTest_q; + wire [10:0] shiftValE_uid35_fpToFxPTest_a; + wire [10:0] shiftValE_uid35_fpToFxPTest_b; + logic [10:0] shiftValE_uid35_fpToFxPTest_o; + wire [9:0] shiftValE_uid35_fpToFxPTest_q; + wire [5:0] shiftValRaw_uid36_fpToFxPTest_in; + wire [5:0] shiftValRaw_uid36_fpToFxPTest_b; + wire [5:0] maxShiftCst_uid37_fpToFxPTest_q; + wire [11:0] shiftOutOfRange_uid38_fpToFxPTest_a; + wire [11:0] shiftOutOfRange_uid38_fpToFxPTest_b; + logic [11:0] shiftOutOfRange_uid38_fpToFxPTest_o; + wire [0:0] shiftOutOfRange_uid38_fpToFxPTest_n; + wire [0:0] shiftVal_uid39_fpToFxPTest_s; + reg [5:0] shiftVal_uid39_fpToFxPTest_q; + wire [31:0] shifterIn_uid41_fpToFxPTest_q; + wire [31:0] maxPosValueS_uid43_fpToFxPTest_q; + wire [31:0] maxNegValueS_uid44_fpToFxPTest_q; + wire [32:0] zRightShiferNoStickyOut_uid45_fpToFxPTest_q; + wire [32:0] xXorSignE_uid46_fpToFxPTest_b; + wire [32:0] xXorSignE_uid46_fpToFxPTest_qi; + reg [32:0] xXorSignE_uid46_fpToFxPTest_q; + wire [2:0] d0_uid47_fpToFxPTest_q; + wire [33:0] sPostRndFull_uid48_fpToFxPTest_a; + wire [33:0] sPostRndFull_uid48_fpToFxPTest_b; + logic [33:0] sPostRndFull_uid48_fpToFxPTest_o; + wire [33:0] sPostRndFull_uid48_fpToFxPTest_q; + wire [32:0] sPostRnd_uid49_fpToFxPTest_in; + wire [31:0] sPostRnd_uid49_fpToFxPTest_b; + wire [34:0] sPostRnd_uid50_fpToFxPTest_in; + wire [33:0] sPostRnd_uid50_fpToFxPTest_b; + wire [35:0] rndOvfPos_uid51_fpToFxPTest_a; + wire [35:0] rndOvfPos_uid51_fpToFxPTest_b; + logic [35:0] rndOvfPos_uid51_fpToFxPTest_o; + wire [0:0] rndOvfPos_uid51_fpToFxPTest_c; + wire [0:0] ovfPostRnd_uid52_fpToFxPTest_q; + wire [2:0] muxSelConc_uid53_fpToFxPTest_q; + reg [1:0] muxSel_uid54_fpToFxPTest_q; + wire [31:0] maxNegValueU_uid55_fpToFxPTest_q; + wire [1:0] finalOut_uid56_fpToFxPTest_s; + reg [31:0] finalOut_uid56_fpToFxPTest_q; + wire [30:0] rightShiftStage0Idx1Rng1_uid60_rightShiferNoStickyOut_uid42_fpToFxPTest_b; + wire [31:0] rightShiftStage0Idx1_uid62_rightShiferNoStickyOut_uid42_fpToFxPTest_q; + wire [29:0] rightShiftStage0Idx2Rng2_uid63_rightShiferNoStickyOut_uid42_fpToFxPTest_b; + wire [1:0] rightShiftStage0Idx2Pad2_uid64_rightShiferNoStickyOut_uid42_fpToFxPTest_q; + wire [31:0] rightShiftStage0Idx2_uid65_rightShiferNoStickyOut_uid42_fpToFxPTest_q; + wire [28:0] rightShiftStage0Idx3Rng3_uid66_rightShiferNoStickyOut_uid42_fpToFxPTest_b; + wire [2:0] rightShiftStage0Idx3Pad3_uid67_rightShiferNoStickyOut_uid42_fpToFxPTest_q; + wire [31:0] rightShiftStage0Idx3_uid68_rightShiferNoStickyOut_uid42_fpToFxPTest_q; + wire [1:0] rightShiftStage0_uid70_rightShiferNoStickyOut_uid42_fpToFxPTest_s; + reg [31:0] rightShiftStage0_uid70_rightShiferNoStickyOut_uid42_fpToFxPTest_q; + wire [27:0] rightShiftStage1Idx1Rng4_uid71_rightShiferNoStickyOut_uid42_fpToFxPTest_b; + wire [3:0] rightShiftStage1Idx1Pad4_uid72_rightShiferNoStickyOut_uid42_fpToFxPTest_q; + wire [31:0] rightShiftStage1Idx1_uid73_rightShiferNoStickyOut_uid42_fpToFxPTest_q; + wire [23:0] rightShiftStage1Idx2Rng8_uid74_rightShiferNoStickyOut_uid42_fpToFxPTest_b; + wire [31:0] rightShiftStage1Idx2_uid76_rightShiferNoStickyOut_uid42_fpToFxPTest_q; + wire [19:0] rightShiftStage1Idx3Rng12_uid77_rightShiferNoStickyOut_uid42_fpToFxPTest_b; + wire [11:0] rightShiftStage1Idx3Pad12_uid78_rightShiferNoStickyOut_uid42_fpToFxPTest_q; + wire [31:0] rightShiftStage1Idx3_uid79_rightShiferNoStickyOut_uid42_fpToFxPTest_q; + wire [1:0] rightShiftStage1_uid81_rightShiferNoStickyOut_uid42_fpToFxPTest_s; + reg [31:0] rightShiftStage1_uid81_rightShiferNoStickyOut_uid42_fpToFxPTest_q; + wire [15:0] rightShiftStage2Idx1Rng16_uid82_rightShiferNoStickyOut_uid42_fpToFxPTest_b; + wire [15:0] rightShiftStage2Idx1Pad16_uid83_rightShiferNoStickyOut_uid42_fpToFxPTest_q; + wire [31:0] rightShiftStage2Idx1_uid84_rightShiferNoStickyOut_uid42_fpToFxPTest_q; + wire [1:0] rightShiftStage2_uid88_rightShiferNoStickyOut_uid42_fpToFxPTest_s; + reg [31:0] rightShiftStage2_uid88_rightShiferNoStickyOut_uid42_fpToFxPTest_q; + wire [1:0] rightShiftStageSel0Dto0_uid69_rightShiferNoStickyOut_uid42_fpToFxPTest_merged_bit_select_b; + wire [1:0] rightShiftStageSel0Dto0_uid69_rightShiferNoStickyOut_uid42_fpToFxPTest_merged_bit_select_c; + wire [1:0] rightShiftStageSel0Dto0_uid69_rightShiferNoStickyOut_uid42_fpToFxPTest_merged_bit_select_d; + reg [31:0] redist0_sPostRnd_uid49_fpToFxPTest_b_1_q; + reg [0:0] redist1_udf_uid33_fpToFxPTest_n_3_q; + reg [0:0] redist1_udf_uid33_fpToFxPTest_n_3_delay_0; + reg [0:0] redist2_ovfExpRange_uid31_fpToFxPTest_n_3_q; + reg [0:0] redist2_ovfExpRange_uid31_fpToFxPTest_n_3_delay_0; + reg [0:0] redist3_signX_uid29_fpToFxPTest_q_3_q; + reg [0:0] redist3_signX_uid29_fpToFxPTest_q_3_delay_0; + reg [0:0] redist4_excN_x_uid16_fpToFxPTest_q_3_q; + reg [0:0] redist4_excN_x_uid16_fpToFxPTest_q_3_delay_0; + reg [0:0] redist4_excN_x_uid16_fpToFxPTest_q_3_delay_1; + reg [0:0] redist5_excI_x_uid15_fpToFxPTest_q_3_q; + reg [0:0] redist5_excI_x_uid15_fpToFxPTest_q_3_delay_0; + + + // maxNegValueU_uid55_fpToFxPTest(CONSTANT,54) + assign maxNegValueU_uid55_fpToFxPTest_q = 32'b00000000000000000000000000000000; + + // maxNegValueS_uid44_fpToFxPTest(CONSTANT,43) + assign maxNegValueS_uid44_fpToFxPTest_q = 32'b10000000000000000000000000000000; + + // maxPosValueS_uid43_fpToFxPTest(CONSTANT,42) + assign maxPosValueS_uid43_fpToFxPTest_q = 32'b01111111111111111111111111111111; + + // d0_uid47_fpToFxPTest(CONSTANT,46) + assign d0_uid47_fpToFxPTest_q = 3'b001; + + // signX_uid27_fpToFxPTest(BITSELECT,26)@0 + assign signX_uid27_fpToFxPTest_b = a[31:31]; + + // frac_x_uid10_fpToFxPTest(BITSELECT,9)@0 + assign frac_x_uid10_fpToFxPTest_b = a[22:0]; + + // cstZeroWF_uid7_fpToFxPTest(CONSTANT,6) + assign cstZeroWF_uid7_fpToFxPTest_q = 23'b00000000000000000000000; + + // fracXIsZero_uid13_fpToFxPTest(LOGICAL,12)@0 + assign fracXIsZero_uid13_fpToFxPTest_q = cstZeroWF_uid7_fpToFxPTest_q == frac_x_uid10_fpToFxPTest_b ? 1'b1 : 1'b0; + + // fracXIsNotZero_uid14_fpToFxPTest(LOGICAL,13)@0 + assign fracXIsNotZero_uid14_fpToFxPTest_q = ~ (fracXIsZero_uid13_fpToFxPTest_q); + + // cstAllOWE_uid6_fpToFxPTest(CONSTANT,5) + assign cstAllOWE_uid6_fpToFxPTest_q = 8'b11111111; + + // exp_x_uid9_fpToFxPTest(BITSELECT,8)@0 + assign exp_x_uid9_fpToFxPTest_b = a[30:23]; + + // expXIsMax_uid12_fpToFxPTest(LOGICAL,11)@0 + assign expXIsMax_uid12_fpToFxPTest_q = exp_x_uid9_fpToFxPTest_b == cstAllOWE_uid6_fpToFxPTest_q ? 1'b1 : 1'b0; + + // excN_x_uid16_fpToFxPTest(LOGICAL,15)@0 + assign excN_x_uid16_fpToFxPTest_q = expXIsMax_uid12_fpToFxPTest_q & fracXIsNotZero_uid14_fpToFxPTest_q; + + // notNan_uid28_fpToFxPTest(LOGICAL,27)@0 + assign notNan_uid28_fpToFxPTest_q = ~ (excN_x_uid16_fpToFxPTest_q); + + // signX_uid29_fpToFxPTest(LOGICAL,28)@0 + 1 + assign signX_uid29_fpToFxPTest_qi = notNan_uid28_fpToFxPTest_q & signX_uid27_fpToFxPTest_b; + dspba_delay_ver #( .width(1), .depth(1), .reset_kind("SYNC"), .phase(0), .modulus(1) ) + signX_uid29_fpToFxPTest_delay ( .xin(signX_uid29_fpToFxPTest_qi), .xout(signX_uid29_fpToFxPTest_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // GND(CONSTANT,0) + assign GND_q = 1'b0; + + // rightShiftStage2Idx1Pad16_uid83_rightShiferNoStickyOut_uid42_fpToFxPTest(CONSTANT,82) + assign rightShiftStage2Idx1Pad16_uid83_rightShiferNoStickyOut_uid42_fpToFxPTest_q = 16'b0000000000000000; + + // rightShiftStage2Idx1Rng16_uid82_rightShiferNoStickyOut_uid42_fpToFxPTest(BITSELECT,81)@1 + assign rightShiftStage2Idx1Rng16_uid82_rightShiferNoStickyOut_uid42_fpToFxPTest_b = rightShiftStage1_uid81_rightShiferNoStickyOut_uid42_fpToFxPTest_q[31:16]; + + // rightShiftStage2Idx1_uid84_rightShiferNoStickyOut_uid42_fpToFxPTest(BITJOIN,83)@1 + assign rightShiftStage2Idx1_uid84_rightShiferNoStickyOut_uid42_fpToFxPTest_q = {rightShiftStage2Idx1Pad16_uid83_rightShiferNoStickyOut_uid42_fpToFxPTest_q, rightShiftStage2Idx1Rng16_uid82_rightShiferNoStickyOut_uid42_fpToFxPTest_b}; + + // rightShiftStage1Idx3Pad12_uid78_rightShiferNoStickyOut_uid42_fpToFxPTest(CONSTANT,77) + assign rightShiftStage1Idx3Pad12_uid78_rightShiferNoStickyOut_uid42_fpToFxPTest_q = 12'b000000000000; + + // rightShiftStage1Idx3Rng12_uid77_rightShiferNoStickyOut_uid42_fpToFxPTest(BITSELECT,76)@1 + assign rightShiftStage1Idx3Rng12_uid77_rightShiferNoStickyOut_uid42_fpToFxPTest_b = rightShiftStage0_uid70_rightShiferNoStickyOut_uid42_fpToFxPTest_q[31:12]; + + // rightShiftStage1Idx3_uid79_rightShiferNoStickyOut_uid42_fpToFxPTest(BITJOIN,78)@1 + assign rightShiftStage1Idx3_uid79_rightShiferNoStickyOut_uid42_fpToFxPTest_q = {rightShiftStage1Idx3Pad12_uid78_rightShiferNoStickyOut_uid42_fpToFxPTest_q, rightShiftStage1Idx3Rng12_uid77_rightShiferNoStickyOut_uid42_fpToFxPTest_b}; + + // cstAllZWE_uid8_fpToFxPTest(CONSTANT,7) + assign cstAllZWE_uid8_fpToFxPTest_q = 8'b00000000; + + // rightShiftStage1Idx2Rng8_uid74_rightShiferNoStickyOut_uid42_fpToFxPTest(BITSELECT,73)@1 + assign rightShiftStage1Idx2Rng8_uid74_rightShiferNoStickyOut_uid42_fpToFxPTest_b = rightShiftStage0_uid70_rightShiferNoStickyOut_uid42_fpToFxPTest_q[31:8]; + + // rightShiftStage1Idx2_uid76_rightShiferNoStickyOut_uid42_fpToFxPTest(BITJOIN,75)@1 + assign rightShiftStage1Idx2_uid76_rightShiferNoStickyOut_uid42_fpToFxPTest_q = {cstAllZWE_uid8_fpToFxPTest_q, rightShiftStage1Idx2Rng8_uid74_rightShiferNoStickyOut_uid42_fpToFxPTest_b}; + + // rightShiftStage1Idx1Pad4_uid72_rightShiferNoStickyOut_uid42_fpToFxPTest(CONSTANT,71) + assign rightShiftStage1Idx1Pad4_uid72_rightShiferNoStickyOut_uid42_fpToFxPTest_q = 4'b0000; + + // rightShiftStage1Idx1Rng4_uid71_rightShiferNoStickyOut_uid42_fpToFxPTest(BITSELECT,70)@1 + assign rightShiftStage1Idx1Rng4_uid71_rightShiferNoStickyOut_uid42_fpToFxPTest_b = rightShiftStage0_uid70_rightShiferNoStickyOut_uid42_fpToFxPTest_q[31:4]; + + // rightShiftStage1Idx1_uid73_rightShiferNoStickyOut_uid42_fpToFxPTest(BITJOIN,72)@1 + assign rightShiftStage1Idx1_uid73_rightShiferNoStickyOut_uid42_fpToFxPTest_q = {rightShiftStage1Idx1Pad4_uid72_rightShiferNoStickyOut_uid42_fpToFxPTest_q, rightShiftStage1Idx1Rng4_uid71_rightShiferNoStickyOut_uid42_fpToFxPTest_b}; + + // rightShiftStage0Idx3Pad3_uid67_rightShiferNoStickyOut_uid42_fpToFxPTest(CONSTANT,66) + assign rightShiftStage0Idx3Pad3_uid67_rightShiferNoStickyOut_uid42_fpToFxPTest_q = 3'b000; + + // rightShiftStage0Idx3Rng3_uid66_rightShiferNoStickyOut_uid42_fpToFxPTest(BITSELECT,65)@1 + assign rightShiftStage0Idx3Rng3_uid66_rightShiferNoStickyOut_uid42_fpToFxPTest_b = shifterIn_uid41_fpToFxPTest_q[31:3]; + + // rightShiftStage0Idx3_uid68_rightShiferNoStickyOut_uid42_fpToFxPTest(BITJOIN,67)@1 + assign rightShiftStage0Idx3_uid68_rightShiferNoStickyOut_uid42_fpToFxPTest_q = {rightShiftStage0Idx3Pad3_uid67_rightShiferNoStickyOut_uid42_fpToFxPTest_q, rightShiftStage0Idx3Rng3_uid66_rightShiferNoStickyOut_uid42_fpToFxPTest_b}; + + // rightShiftStage0Idx2Pad2_uid64_rightShiferNoStickyOut_uid42_fpToFxPTest(CONSTANT,63) + assign rightShiftStage0Idx2Pad2_uid64_rightShiferNoStickyOut_uid42_fpToFxPTest_q = 2'b00; + + // rightShiftStage0Idx2Rng2_uid63_rightShiferNoStickyOut_uid42_fpToFxPTest(BITSELECT,62)@1 + assign rightShiftStage0Idx2Rng2_uid63_rightShiferNoStickyOut_uid42_fpToFxPTest_b = shifterIn_uid41_fpToFxPTest_q[31:2]; + + // rightShiftStage0Idx2_uid65_rightShiferNoStickyOut_uid42_fpToFxPTest(BITJOIN,64)@1 + assign rightShiftStage0Idx2_uid65_rightShiferNoStickyOut_uid42_fpToFxPTest_q = {rightShiftStage0Idx2Pad2_uid64_rightShiferNoStickyOut_uid42_fpToFxPTest_q, rightShiftStage0Idx2Rng2_uid63_rightShiferNoStickyOut_uid42_fpToFxPTest_b}; + + // rightShiftStage0Idx1Rng1_uid60_rightShiferNoStickyOut_uid42_fpToFxPTest(BITSELECT,59)@1 + assign rightShiftStage0Idx1Rng1_uid60_rightShiferNoStickyOut_uid42_fpToFxPTest_b = shifterIn_uid41_fpToFxPTest_q[31:1]; + + // rightShiftStage0Idx1_uid62_rightShiferNoStickyOut_uid42_fpToFxPTest(BITJOIN,61)@1 + assign rightShiftStage0Idx1_uid62_rightShiferNoStickyOut_uid42_fpToFxPTest_q = {GND_q, rightShiftStage0Idx1Rng1_uid60_rightShiferNoStickyOut_uid42_fpToFxPTest_b}; + + // excZ_x_uid11_fpToFxPTest(LOGICAL,10)@0 + assign excZ_x_uid11_fpToFxPTest_q = exp_x_uid9_fpToFxPTest_b == cstAllZWE_uid8_fpToFxPTest_q ? 1'b1 : 1'b0; + + // invExcXZ_uid24_fpToFxPTest(LOGICAL,23)@0 + 1 + assign invExcXZ_uid24_fpToFxPTest_qi = ~ (excZ_x_uid11_fpToFxPTest_q); + dspba_delay_ver #( .width(1), .depth(1), .reset_kind("SYNC"), .phase(0), .modulus(1) ) + invExcXZ_uid24_fpToFxPTest_delay ( .xin(invExcXZ_uid24_fpToFxPTest_qi), .xout(invExcXZ_uid24_fpToFxPTest_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // fracPostZ_uid23_fpToFxPTest(MUX,22)@0 + 1 + assign fracPostZ_uid23_fpToFxPTest_s = excZ_x_uid11_fpToFxPTest_q; + always @ (posedge clk) + begin + if (areset) + begin + fracPostZ_uid23_fpToFxPTest_q <= 23'b0; + end + else if (en == 1'b1) + begin + unique case (fracPostZ_uid23_fpToFxPTest_s) + 1'b0 : fracPostZ_uid23_fpToFxPTest_q <= frac_x_uid10_fpToFxPTest_b; + 1'b1 : fracPostZ_uid23_fpToFxPTest_q <= cstZeroWF_uid7_fpToFxPTest_q; + default : fracPostZ_uid23_fpToFxPTest_q <= 23'b0; + endcase + end + end + + // oFracX_uid25_fpToFxPTest(BITJOIN,24)@1 + assign oFracX_uid25_fpToFxPTest_q = {invExcXZ_uid24_fpToFxPTest_q, fracPostZ_uid23_fpToFxPTest_q}; + + // shifterIn_uid41_fpToFxPTest(BITJOIN,40)@1 + assign shifterIn_uid41_fpToFxPTest_q = {oFracX_uid25_fpToFxPTest_q, cstAllZWE_uid8_fpToFxPTest_q}; + + // rightShiftStage0_uid70_rightShiferNoStickyOut_uid42_fpToFxPTest(MUX,69)@1 + assign rightShiftStage0_uid70_rightShiferNoStickyOut_uid42_fpToFxPTest_s = rightShiftStageSel0Dto0_uid69_rightShiferNoStickyOut_uid42_fpToFxPTest_merged_bit_select_b; + always @(rightShiftStage0_uid70_rightShiferNoStickyOut_uid42_fpToFxPTest_s or en or shifterIn_uid41_fpToFxPTest_q or rightShiftStage0Idx1_uid62_rightShiferNoStickyOut_uid42_fpToFxPTest_q or rightShiftStage0Idx2_uid65_rightShiferNoStickyOut_uid42_fpToFxPTest_q or rightShiftStage0Idx3_uid68_rightShiferNoStickyOut_uid42_fpToFxPTest_q) + begin + unique case (rightShiftStage0_uid70_rightShiferNoStickyOut_uid42_fpToFxPTest_s) + 2'b00 : rightShiftStage0_uid70_rightShiferNoStickyOut_uid42_fpToFxPTest_q = shifterIn_uid41_fpToFxPTest_q; + 2'b01 : rightShiftStage0_uid70_rightShiferNoStickyOut_uid42_fpToFxPTest_q = rightShiftStage0Idx1_uid62_rightShiferNoStickyOut_uid42_fpToFxPTest_q; + 2'b10 : rightShiftStage0_uid70_rightShiferNoStickyOut_uid42_fpToFxPTest_q = rightShiftStage0Idx2_uid65_rightShiferNoStickyOut_uid42_fpToFxPTest_q; + 2'b11 : rightShiftStage0_uid70_rightShiferNoStickyOut_uid42_fpToFxPTest_q = rightShiftStage0Idx3_uid68_rightShiferNoStickyOut_uid42_fpToFxPTest_q; + default : rightShiftStage0_uid70_rightShiferNoStickyOut_uid42_fpToFxPTest_q = 32'b0; + endcase + end + + // rightShiftStage1_uid81_rightShiferNoStickyOut_uid42_fpToFxPTest(MUX,80)@1 + assign rightShiftStage1_uid81_rightShiferNoStickyOut_uid42_fpToFxPTest_s = rightShiftStageSel0Dto0_uid69_rightShiferNoStickyOut_uid42_fpToFxPTest_merged_bit_select_c; + always @(rightShiftStage1_uid81_rightShiferNoStickyOut_uid42_fpToFxPTest_s or en or rightShiftStage0_uid70_rightShiferNoStickyOut_uid42_fpToFxPTest_q or rightShiftStage1Idx1_uid73_rightShiferNoStickyOut_uid42_fpToFxPTest_q or rightShiftStage1Idx2_uid76_rightShiferNoStickyOut_uid42_fpToFxPTest_q or rightShiftStage1Idx3_uid79_rightShiferNoStickyOut_uid42_fpToFxPTest_q) + begin + unique case (rightShiftStage1_uid81_rightShiferNoStickyOut_uid42_fpToFxPTest_s) + 2'b00 : rightShiftStage1_uid81_rightShiferNoStickyOut_uid42_fpToFxPTest_q = rightShiftStage0_uid70_rightShiferNoStickyOut_uid42_fpToFxPTest_q; + 2'b01 : rightShiftStage1_uid81_rightShiferNoStickyOut_uid42_fpToFxPTest_q = rightShiftStage1Idx1_uid73_rightShiferNoStickyOut_uid42_fpToFxPTest_q; + 2'b10 : rightShiftStage1_uid81_rightShiferNoStickyOut_uid42_fpToFxPTest_q = rightShiftStage1Idx2_uid76_rightShiferNoStickyOut_uid42_fpToFxPTest_q; + 2'b11 : rightShiftStage1_uid81_rightShiferNoStickyOut_uid42_fpToFxPTest_q = rightShiftStage1Idx3_uid79_rightShiferNoStickyOut_uid42_fpToFxPTest_q; + default : rightShiftStage1_uid81_rightShiferNoStickyOut_uid42_fpToFxPTest_q = 32'b0; + endcase + end + + // maxShiftCst_uid37_fpToFxPTest(CONSTANT,36) + assign maxShiftCst_uid37_fpToFxPTest_q = 6'b100000; + + // ovfExpVal_uid34_fpToFxPTest(CONSTANT,33) + assign ovfExpVal_uid34_fpToFxPTest_q = 9'b010011101; + + // shiftValE_uid35_fpToFxPTest(SUB,34)@0 + assign shiftValE_uid35_fpToFxPTest_a = {{2{ovfExpVal_uid34_fpToFxPTest_q[8]}}, ovfExpVal_uid34_fpToFxPTest_q}; + assign shiftValE_uid35_fpToFxPTest_b = {3'b000, exp_x_uid9_fpToFxPTest_b}; + assign shiftValE_uid35_fpToFxPTest_o = $signed(shiftValE_uid35_fpToFxPTest_a) - $signed(shiftValE_uid35_fpToFxPTest_b); + assign shiftValE_uid35_fpToFxPTest_q = shiftValE_uid35_fpToFxPTest_o[9:0]; + + // shiftValRaw_uid36_fpToFxPTest(BITSELECT,35)@0 + assign shiftValRaw_uid36_fpToFxPTest_in = shiftValE_uid35_fpToFxPTest_q[5:0]; + assign shiftValRaw_uid36_fpToFxPTest_b = shiftValRaw_uid36_fpToFxPTest_in[5:0]; + + // shiftOutOfRange_uid38_fpToFxPTest(COMPARE,37)@0 + assign shiftOutOfRange_uid38_fpToFxPTest_a = {{2{shiftValE_uid35_fpToFxPTest_q[9]}}, shiftValE_uid35_fpToFxPTest_q}; + assign shiftOutOfRange_uid38_fpToFxPTest_b = {6'b000000, maxShiftCst_uid37_fpToFxPTest_q}; + assign shiftOutOfRange_uid38_fpToFxPTest_o = $signed(shiftOutOfRange_uid38_fpToFxPTest_a) - $signed(shiftOutOfRange_uid38_fpToFxPTest_b); + assign shiftOutOfRange_uid38_fpToFxPTest_n[0] = ~ (shiftOutOfRange_uid38_fpToFxPTest_o[11]); + + // shiftVal_uid39_fpToFxPTest(MUX,38)@0 + 1 + assign shiftVal_uid39_fpToFxPTest_s = shiftOutOfRange_uid38_fpToFxPTest_n; + always @ (posedge clk) + begin + if (areset) + begin + shiftVal_uid39_fpToFxPTest_q <= 6'b0; + end + else if (en == 1'b1) + begin + unique case (shiftVal_uid39_fpToFxPTest_s) + 1'b0 : shiftVal_uid39_fpToFxPTest_q <= shiftValRaw_uid36_fpToFxPTest_b; + 1'b1 : shiftVal_uid39_fpToFxPTest_q <= maxShiftCst_uid37_fpToFxPTest_q; + default : shiftVal_uid39_fpToFxPTest_q <= 6'b0; + endcase + end + end + + // rightShiftStageSel0Dto0_uid69_rightShiferNoStickyOut_uid42_fpToFxPTest_merged_bit_select(BITSELECT,89)@1 + assign rightShiftStageSel0Dto0_uid69_rightShiferNoStickyOut_uid42_fpToFxPTest_merged_bit_select_b = shiftVal_uid39_fpToFxPTest_q[1:0]; + assign rightShiftStageSel0Dto0_uid69_rightShiferNoStickyOut_uid42_fpToFxPTest_merged_bit_select_c = shiftVal_uid39_fpToFxPTest_q[3:2]; + assign rightShiftStageSel0Dto0_uid69_rightShiferNoStickyOut_uid42_fpToFxPTest_merged_bit_select_d = shiftVal_uid39_fpToFxPTest_q[5:4]; + + // rightShiftStage2_uid88_rightShiferNoStickyOut_uid42_fpToFxPTest(MUX,87)@1 + assign rightShiftStage2_uid88_rightShiferNoStickyOut_uid42_fpToFxPTest_s = rightShiftStageSel0Dto0_uid69_rightShiferNoStickyOut_uid42_fpToFxPTest_merged_bit_select_d; + always @(rightShiftStage2_uid88_rightShiferNoStickyOut_uid42_fpToFxPTest_s or en or rightShiftStage1_uid81_rightShiferNoStickyOut_uid42_fpToFxPTest_q or rightShiftStage2Idx1_uid84_rightShiferNoStickyOut_uid42_fpToFxPTest_q or maxNegValueU_uid55_fpToFxPTest_q) + begin + unique case (rightShiftStage2_uid88_rightShiferNoStickyOut_uid42_fpToFxPTest_s) + 2'b00 : rightShiftStage2_uid88_rightShiferNoStickyOut_uid42_fpToFxPTest_q = rightShiftStage1_uid81_rightShiferNoStickyOut_uid42_fpToFxPTest_q; + 2'b01 : rightShiftStage2_uid88_rightShiferNoStickyOut_uid42_fpToFxPTest_q = rightShiftStage2Idx1_uid84_rightShiferNoStickyOut_uid42_fpToFxPTest_q; + 2'b10 : rightShiftStage2_uid88_rightShiferNoStickyOut_uid42_fpToFxPTest_q = maxNegValueU_uid55_fpToFxPTest_q; + 2'b11 : rightShiftStage2_uid88_rightShiferNoStickyOut_uid42_fpToFxPTest_q = maxNegValueU_uid55_fpToFxPTest_q; + default : rightShiftStage2_uid88_rightShiferNoStickyOut_uid42_fpToFxPTest_q = 32'b0; + endcase + end + + // zRightShiferNoStickyOut_uid45_fpToFxPTest(BITJOIN,44)@1 + assign zRightShiferNoStickyOut_uid45_fpToFxPTest_q = {GND_q, rightShiftStage2_uid88_rightShiferNoStickyOut_uid42_fpToFxPTest_q}; + + // xXorSignE_uid46_fpToFxPTest(LOGICAL,45)@1 + 1 + assign xXorSignE_uid46_fpToFxPTest_b = {{32{signX_uid29_fpToFxPTest_q[0]}}, signX_uid29_fpToFxPTest_q}; + assign xXorSignE_uid46_fpToFxPTest_qi = zRightShiferNoStickyOut_uid45_fpToFxPTest_q ^ xXorSignE_uid46_fpToFxPTest_b; + dspba_delay_ver #( .width(33), .depth(1), .reset_kind("SYNC"), .phase(0), .modulus(1) ) + xXorSignE_uid46_fpToFxPTest_delay ( .xin(xXorSignE_uid46_fpToFxPTest_qi), .xout(xXorSignE_uid46_fpToFxPTest_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // sPostRndFull_uid48_fpToFxPTest(ADD,47)@2 + assign sPostRndFull_uid48_fpToFxPTest_a = {{1{xXorSignE_uid46_fpToFxPTest_q[32]}}, xXorSignE_uid46_fpToFxPTest_q}; + assign sPostRndFull_uid48_fpToFxPTest_b = {{31{d0_uid47_fpToFxPTest_q[2]}}, d0_uid47_fpToFxPTest_q}; + assign sPostRndFull_uid48_fpToFxPTest_o = $signed(sPostRndFull_uid48_fpToFxPTest_a) + $signed(sPostRndFull_uid48_fpToFxPTest_b); + assign sPostRndFull_uid48_fpToFxPTest_q = sPostRndFull_uid48_fpToFxPTest_o[33:0]; + + // sPostRnd_uid49_fpToFxPTest(BITSELECT,48)@2 + assign sPostRnd_uid49_fpToFxPTest_in = sPostRndFull_uid48_fpToFxPTest_q[32:0]; + assign sPostRnd_uid49_fpToFxPTest_b = sPostRnd_uid49_fpToFxPTest_in[32:1]; + + // redist0_sPostRnd_uid49_fpToFxPTest_b_1(DELAY,90) + always @ (posedge clk) + begin + if (areset) + begin + redist0_sPostRnd_uid49_fpToFxPTest_b_1_q <= '0; + end + else if (en == 1'b1) + begin + redist0_sPostRnd_uid49_fpToFxPTest_b_1_q <= sPostRnd_uid49_fpToFxPTest_b; + end + end + + // redist3_signX_uid29_fpToFxPTest_q_3(DELAY,93) + always @ (posedge clk) + begin + if (areset) + begin + redist3_signX_uid29_fpToFxPTest_q_3_delay_0 <= '0; + redist3_signX_uid29_fpToFxPTest_q_3_q <= '0; + end + else if (en == 1'b1) + begin + redist3_signX_uid29_fpToFxPTest_q_3_delay_0 <= signX_uid29_fpToFxPTest_q; + redist3_signX_uid29_fpToFxPTest_q_3_q <= redist3_signX_uid29_fpToFxPTest_q_3_delay_0; + end + end + + // udfExpVal_uid32_fpToFxPTest(CONSTANT,31) + assign udfExpVal_uid32_fpToFxPTest_q = 8'b01111101; + + // udf_uid33_fpToFxPTest(COMPARE,32)@0 + 1 + assign udf_uid33_fpToFxPTest_a = {{3{udfExpVal_uid32_fpToFxPTest_q[7]}}, udfExpVal_uid32_fpToFxPTest_q}; + assign udf_uid33_fpToFxPTest_b = {3'b000, exp_x_uid9_fpToFxPTest_b}; + always @ (posedge clk) + begin + if (areset) + begin + udf_uid33_fpToFxPTest_o <= 11'b0; + end + else if (en == 1'b1) + begin + udf_uid33_fpToFxPTest_o <= $signed(udf_uid33_fpToFxPTest_a) - $signed(udf_uid33_fpToFxPTest_b); + end + end + assign udf_uid33_fpToFxPTest_n[0] = ~ (udf_uid33_fpToFxPTest_o[10]); + + // redist1_udf_uid33_fpToFxPTest_n_3(DELAY,91) + always @ (posedge clk) + begin + if (areset) + begin + redist1_udf_uid33_fpToFxPTest_n_3_delay_0 <= '0; + redist1_udf_uid33_fpToFxPTest_n_3_q <= '0; + end + else if (en == 1'b1) + begin + redist1_udf_uid33_fpToFxPTest_n_3_delay_0 <= udf_uid33_fpToFxPTest_n; + redist1_udf_uid33_fpToFxPTest_n_3_q <= redist1_udf_uid33_fpToFxPTest_n_3_delay_0; + end + end + + // sPostRnd_uid50_fpToFxPTest(BITSELECT,49)@2 + assign sPostRnd_uid50_fpToFxPTest_in = {{1{sPostRndFull_uid48_fpToFxPTest_q[33]}}, sPostRndFull_uid48_fpToFxPTest_q}; + assign sPostRnd_uid50_fpToFxPTest_b = sPostRnd_uid50_fpToFxPTest_in[34:1]; + + // rndOvfPos_uid51_fpToFxPTest(COMPARE,50)@2 + 1 + assign rndOvfPos_uid51_fpToFxPTest_a = {4'b0000, maxPosValueS_uid43_fpToFxPTest_q}; + assign rndOvfPos_uid51_fpToFxPTest_b = {{2{sPostRnd_uid50_fpToFxPTest_b[33]}}, sPostRnd_uid50_fpToFxPTest_b}; + always @ (posedge clk) + begin + if (areset) + begin + rndOvfPos_uid51_fpToFxPTest_o <= 36'b0; + end + else if (en == 1'b1) + begin + rndOvfPos_uid51_fpToFxPTest_o <= $signed(rndOvfPos_uid51_fpToFxPTest_a) - $signed(rndOvfPos_uid51_fpToFxPTest_b); + end + end + assign rndOvfPos_uid51_fpToFxPTest_c[0] = rndOvfPos_uid51_fpToFxPTest_o[35]; + + // ovfExpVal_uid30_fpToFxPTest(CONSTANT,29) + assign ovfExpVal_uid30_fpToFxPTest_q = 9'b010011110; + + // ovfExpRange_uid31_fpToFxPTest(COMPARE,30)@0 + 1 + assign ovfExpRange_uid31_fpToFxPTest_a = {3'b000, exp_x_uid9_fpToFxPTest_b}; + assign ovfExpRange_uid31_fpToFxPTest_b = {{2{ovfExpVal_uid30_fpToFxPTest_q[8]}}, ovfExpVal_uid30_fpToFxPTest_q}; + always @ (posedge clk) + begin + if (areset) + begin + ovfExpRange_uid31_fpToFxPTest_o <= 11'b0; + end + else if (en == 1'b1) + begin + ovfExpRange_uid31_fpToFxPTest_o <= $signed(ovfExpRange_uid31_fpToFxPTest_a) - $signed(ovfExpRange_uid31_fpToFxPTest_b); + end + end + assign ovfExpRange_uid31_fpToFxPTest_n[0] = ~ (ovfExpRange_uid31_fpToFxPTest_o[10]); + + // redist2_ovfExpRange_uid31_fpToFxPTest_n_3(DELAY,92) + always @ (posedge clk) + begin + if (areset) + begin + redist2_ovfExpRange_uid31_fpToFxPTest_n_3_delay_0 <= '0; + redist2_ovfExpRange_uid31_fpToFxPTest_n_3_q <= '0; + end + else if (en == 1'b1) + begin + redist2_ovfExpRange_uid31_fpToFxPTest_n_3_delay_0 <= ovfExpRange_uid31_fpToFxPTest_n; + redist2_ovfExpRange_uid31_fpToFxPTest_n_3_q <= redist2_ovfExpRange_uid31_fpToFxPTest_n_3_delay_0; + end + end + + // excI_x_uid15_fpToFxPTest(LOGICAL,14)@0 + 1 + assign excI_x_uid15_fpToFxPTest_qi = expXIsMax_uid12_fpToFxPTest_q & fracXIsZero_uid13_fpToFxPTest_q; + dspba_delay_ver #( .width(1), .depth(1), .reset_kind("SYNC"), .phase(0), .modulus(1) ) + excI_x_uid15_fpToFxPTest_delay ( .xin(excI_x_uid15_fpToFxPTest_qi), .xout(excI_x_uid15_fpToFxPTest_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // redist5_excI_x_uid15_fpToFxPTest_q_3(DELAY,95) + always @ (posedge clk) + begin + if (areset) + begin + redist5_excI_x_uid15_fpToFxPTest_q_3_delay_0 <= '0; + redist5_excI_x_uid15_fpToFxPTest_q_3_q <= '0; + end + else if (en == 1'b1) + begin + redist5_excI_x_uid15_fpToFxPTest_q_3_delay_0 <= excI_x_uid15_fpToFxPTest_q; + redist5_excI_x_uid15_fpToFxPTest_q_3_q <= redist5_excI_x_uid15_fpToFxPTest_q_3_delay_0; + end + end + + // redist4_excN_x_uid16_fpToFxPTest_q_3(DELAY,94) + always @ (posedge clk) + begin + if (areset) + begin + redist4_excN_x_uid16_fpToFxPTest_q_3_delay_0 <= '0; + redist4_excN_x_uid16_fpToFxPTest_q_3_delay_1 <= '0; + redist4_excN_x_uid16_fpToFxPTest_q_3_q <= '0; + end + else if (en == 1'b1) + begin + redist4_excN_x_uid16_fpToFxPTest_q_3_delay_0 <= excN_x_uid16_fpToFxPTest_q; + redist4_excN_x_uid16_fpToFxPTest_q_3_delay_1 <= redist4_excN_x_uid16_fpToFxPTest_q_3_delay_0; + redist4_excN_x_uid16_fpToFxPTest_q_3_q <= redist4_excN_x_uid16_fpToFxPTest_q_3_delay_1; + end + end + + // ovfPostRnd_uid52_fpToFxPTest(LOGICAL,51)@3 + assign ovfPostRnd_uid52_fpToFxPTest_q = redist4_excN_x_uid16_fpToFxPTest_q_3_q | redist5_excI_x_uid15_fpToFxPTest_q_3_q | redist2_ovfExpRange_uid31_fpToFxPTest_n_3_q | rndOvfPos_uid51_fpToFxPTest_c; + + // muxSelConc_uid53_fpToFxPTest(BITJOIN,52)@3 + assign muxSelConc_uid53_fpToFxPTest_q = {redist3_signX_uid29_fpToFxPTest_q_3_q, redist1_udf_uid33_fpToFxPTest_n_3_q, ovfPostRnd_uid52_fpToFxPTest_q}; + + // muxSel_uid54_fpToFxPTest(LOOKUP,53)@3 + always @(muxSelConc_uid53_fpToFxPTest_q) + begin + // Begin reserved scope level + unique case (muxSelConc_uid53_fpToFxPTest_q) + 3'b000 : muxSel_uid54_fpToFxPTest_q = 2'b00; + 3'b001 : muxSel_uid54_fpToFxPTest_q = 2'b01; + 3'b010 : muxSel_uid54_fpToFxPTest_q = 2'b11; + 3'b011 : muxSel_uid54_fpToFxPTest_q = 2'b11; + 3'b100 : muxSel_uid54_fpToFxPTest_q = 2'b00; + 3'b101 : muxSel_uid54_fpToFxPTest_q = 2'b10; + 3'b110 : muxSel_uid54_fpToFxPTest_q = 2'b11; + 3'b111 : muxSel_uid54_fpToFxPTest_q = 2'b11; + default : begin + // unreachable + muxSel_uid54_fpToFxPTest_q = 2'bxx; + end + endcase + // End reserved scope level + end + + // finalOut_uid56_fpToFxPTest(MUX,55)@3 + assign finalOut_uid56_fpToFxPTest_s = muxSel_uid54_fpToFxPTest_q; + always @(finalOut_uid56_fpToFxPTest_s or en or redist0_sPostRnd_uid49_fpToFxPTest_b_1_q or maxPosValueS_uid43_fpToFxPTest_q or maxNegValueS_uid44_fpToFxPTest_q or maxNegValueU_uid55_fpToFxPTest_q) + begin + unique case (finalOut_uid56_fpToFxPTest_s) + 2'b00 : finalOut_uid56_fpToFxPTest_q = redist0_sPostRnd_uid49_fpToFxPTest_b_1_q; + 2'b01 : finalOut_uid56_fpToFxPTest_q = maxPosValueS_uid43_fpToFxPTest_q; + 2'b10 : finalOut_uid56_fpToFxPTest_q = maxNegValueS_uid44_fpToFxPTest_q; + 2'b11 : finalOut_uid56_fpToFxPTest_q = maxNegValueU_uid55_fpToFxPTest_q; + default : finalOut_uid56_fpToFxPTest_q = 32'b0; + endcase + end + + // xOut(GPOUT,4)@3 + assign q = finalOut_uid56_fpToFxPTest_q; + +endmodule diff --git a/hw/rtl/fp_cores/altera/stratix10/acl_ftou.sv b/hw/rtl/fp_cores/altera/stratix10/acl_ftou.sv new file mode 100644 index 00000000..cb93a84f --- /dev/null +++ b/hw/rtl/fp_cores/altera/stratix10/acl_ftou.sv @@ -0,0 +1,563 @@ +// ------------------------------------------------------------------------- +// High Level Design Compiler for Intel(R) FPGAs Version 18.1 (Release Build #277) +// Quartus Prime development tool and MATLAB/Simulink Interface +// +// Legal Notice: Copyright 2019 Intel Corporation. All rights reserved. +// Your use of Intel Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly +// subject to the terms and conditions of the Intel FPGA Software License +// Agreement, Intel MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for +// the sole purpose of programming logic devices manufactured by Intel +// and sold by Intel or its authorized distributors. Please refer to the +// applicable agreement for further details. +// --------------------------------------------------------------------------- + +// SystemVerilog created from acl_ftou +// SystemVerilog created on Sun Dec 27 09:48:58 2020 + + +(* altera_attribute = "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410; -name MESSAGE_DISABLE 113007; -name MESSAGE_DISABLE 10958" *) +module acl_ftou ( + input wire [31:0] a, + input wire [0:0] en, + output wire [31:0] q, + input wire clk, + input wire areset + ); + + wire [0:0] GND_q; + wire [0:0] VCC_q; + wire [7:0] cstAllOWE_uid6_fpToFxPTest_q; + wire [22:0] cstZeroWF_uid7_fpToFxPTest_q; + wire [7:0] cstAllZWE_uid8_fpToFxPTest_q; + wire [7:0] exp_x_uid9_fpToFxPTest_b; + wire [22:0] frac_x_uid10_fpToFxPTest_b; + wire [0:0] excZ_x_uid11_fpToFxPTest_qi; + reg [0:0] excZ_x_uid11_fpToFxPTest_q; + wire [0:0] expXIsMax_uid12_fpToFxPTest_qi; + reg [0:0] expXIsMax_uid12_fpToFxPTest_q; + wire [0:0] fracXIsZero_uid13_fpToFxPTest_q; + wire [0:0] fracXIsNotZero_uid14_fpToFxPTest_q; + wire [0:0] excI_x_uid15_fpToFxPTest_qi; + reg [0:0] excI_x_uid15_fpToFxPTest_q; + wire [0:0] excN_x_uid16_fpToFxPTest_q; + wire [0:0] fracPostZ_uid23_fpToFxPTest_s; + reg [22:0] fracPostZ_uid23_fpToFxPTest_q; + wire [0:0] invExcXZ_uid24_fpToFxPTest_q; + wire [23:0] oFracX_uid25_fpToFxPTest_q; + wire [0:0] signX_uid27_fpToFxPTest_b; + wire [0:0] notNan_uid28_fpToFxPTest_q; + wire [0:0] signX_uid29_fpToFxPTest_qi; + reg [0:0] signX_uid29_fpToFxPTest_q; + wire [8:0] ovfExpVal_uid30_fpToFxPTest_q; + wire [10:0] ovf_uid31_fpToFxPTest_a; + wire [10:0] ovf_uid31_fpToFxPTest_b; + logic [10:0] ovf_uid31_fpToFxPTest_o; + wire [0:0] ovf_uid31_fpToFxPTest_n; + wire [0:0] negOrOvf_uid32_fpToFxPTest_q; + wire [7:0] udfExpVal_uid33_fpToFxPTest_q; + wire [10:0] udf_uid34_fpToFxPTest_a; + wire [10:0] udf_uid34_fpToFxPTest_b; + logic [10:0] udf_uid34_fpToFxPTest_o; + wire [0:0] udf_uid34_fpToFxPTest_n; + wire [8:0] ovfExpVal_uid35_fpToFxPTest_q; + wire [10:0] shiftValE_uid36_fpToFxPTest_a; + wire [10:0] shiftValE_uid36_fpToFxPTest_b; + logic [10:0] shiftValE_uid36_fpToFxPTest_o; + wire [9:0] shiftValE_uid36_fpToFxPTest_q; + wire [5:0] shiftValRaw_uid37_fpToFxPTest_in; + wire [5:0] shiftValRaw_uid37_fpToFxPTest_b; + wire [5:0] maxShiftCst_uid38_fpToFxPTest_q; + wire [11:0] shiftOutOfRange_uid39_fpToFxPTest_a; + wire [11:0] shiftOutOfRange_uid39_fpToFxPTest_b; + logic [11:0] shiftOutOfRange_uid39_fpToFxPTest_o; + wire [0:0] shiftOutOfRange_uid39_fpToFxPTest_n; + wire [0:0] shiftVal_uid40_fpToFxPTest_s; + reg [5:0] shiftVal_uid40_fpToFxPTest_q; + wire [8:0] zPadd_uid41_fpToFxPTest_q; + wire [32:0] shifterIn_uid42_fpToFxPTest_q; + wire [31:0] maxPosValueU_uid44_fpToFxPTest_q; + wire [31:0] maxNegValueU_uid45_fpToFxPTest_q; + wire [33:0] zRightShiferNoStickyOut_uid47_fpToFxPTest_q; + wire [34:0] sPostRndFull_uid48_fpToFxPTest_a; + wire [34:0] sPostRndFull_uid48_fpToFxPTest_b; + logic [34:0] sPostRndFull_uid48_fpToFxPTest_o; + wire [34:0] sPostRndFull_uid48_fpToFxPTest_q; + wire [32:0] sPostRnd_uid49_fpToFxPTest_in; + wire [31:0] sPostRnd_uid49_fpToFxPTest_b; + wire [33:0] sPostRndFullMSBU_uid50_fpToFxPTest_in; + wire [0:0] sPostRndFullMSBU_uid50_fpToFxPTest_b; + wire [0:0] ovfPostRnd_uid51_fpToFxPTest_q; + wire [2:0] muxSelConc_uid52_fpToFxPTest_q; + reg [1:0] muxSel_uid53_fpToFxPTest_q; + wire [1:0] finalOut_uid55_fpToFxPTest_s; + reg [31:0] finalOut_uid55_fpToFxPTest_q; + wire [31:0] rightShiftStage0Idx1Rng1_uid59_rightShiferNoStickyOut_uid43_fpToFxPTest_b; + wire [32:0] rightShiftStage0Idx1_uid61_rightShiferNoStickyOut_uid43_fpToFxPTest_q; + wire [30:0] rightShiftStage0Idx2Rng2_uid62_rightShiferNoStickyOut_uid43_fpToFxPTest_b; + wire [1:0] rightShiftStage0Idx2Pad2_uid63_rightShiferNoStickyOut_uid43_fpToFxPTest_q; + wire [32:0] rightShiftStage0Idx2_uid64_rightShiferNoStickyOut_uid43_fpToFxPTest_q; + wire [29:0] rightShiftStage0Idx3Rng3_uid65_rightShiferNoStickyOut_uid43_fpToFxPTest_b; + wire [2:0] rightShiftStage0Idx3Pad3_uid66_rightShiferNoStickyOut_uid43_fpToFxPTest_q; + wire [32:0] rightShiftStage0Idx3_uid67_rightShiferNoStickyOut_uid43_fpToFxPTest_q; + wire [1:0] rightShiftStage0_uid69_rightShiferNoStickyOut_uid43_fpToFxPTest_s; + reg [32:0] rightShiftStage0_uid69_rightShiferNoStickyOut_uid43_fpToFxPTest_q; + wire [28:0] rightShiftStage1Idx1Rng4_uid70_rightShiferNoStickyOut_uid43_fpToFxPTest_b; + wire [3:0] rightShiftStage1Idx1Pad4_uid71_rightShiferNoStickyOut_uid43_fpToFxPTest_q; + wire [32:0] rightShiftStage1Idx1_uid72_rightShiferNoStickyOut_uid43_fpToFxPTest_q; + wire [24:0] rightShiftStage1Idx2Rng8_uid73_rightShiferNoStickyOut_uid43_fpToFxPTest_b; + wire [32:0] rightShiftStage1Idx2_uid75_rightShiferNoStickyOut_uid43_fpToFxPTest_q; + wire [20:0] rightShiftStage1Idx3Rng12_uid76_rightShiferNoStickyOut_uid43_fpToFxPTest_b; + wire [11:0] rightShiftStage1Idx3Pad12_uid77_rightShiferNoStickyOut_uid43_fpToFxPTest_q; + wire [32:0] rightShiftStage1Idx3_uid78_rightShiferNoStickyOut_uid43_fpToFxPTest_q; + wire [1:0] rightShiftStage1_uid80_rightShiferNoStickyOut_uid43_fpToFxPTest_s; + reg [32:0] rightShiftStage1_uid80_rightShiferNoStickyOut_uid43_fpToFxPTest_q; + wire [16:0] rightShiftStage2Idx1Rng16_uid81_rightShiferNoStickyOut_uid43_fpToFxPTest_b; + wire [15:0] rightShiftStage2Idx1Pad16_uid82_rightShiferNoStickyOut_uid43_fpToFxPTest_q; + wire [32:0] rightShiftStage2Idx1_uid83_rightShiferNoStickyOut_uid43_fpToFxPTest_q; + wire [0:0] rightShiftStage2Idx2Rng32_uid84_rightShiferNoStickyOut_uid43_fpToFxPTest_b; + wire [32:0] rightShiftStage2Idx2_uid86_rightShiferNoStickyOut_uid43_fpToFxPTest_q; + wire [32:0] rightShiftStage2Idx3_uid87_rightShiferNoStickyOut_uid43_fpToFxPTest_q; + wire [1:0] rightShiftStage2_uid89_rightShiferNoStickyOut_uid43_fpToFxPTest_s; + reg [32:0] rightShiftStage2_uid89_rightShiferNoStickyOut_uid43_fpToFxPTest_q; + wire [1:0] rightShiftStageSel0Dto0_uid68_rightShiferNoStickyOut_uid43_fpToFxPTest_merged_bit_select_b; + wire [1:0] rightShiftStageSel0Dto0_uid68_rightShiferNoStickyOut_uid43_fpToFxPTest_merged_bit_select_c; + wire [1:0] rightShiftStageSel0Dto0_uid68_rightShiferNoStickyOut_uid43_fpToFxPTest_merged_bit_select_d; + reg [31:0] redist0_sPostRnd_uid49_fpToFxPTest_b_1_q; + reg [0:0] redist1_udf_uid34_fpToFxPTest_n_2_q; + reg [0:0] redist2_ovf_uid31_fpToFxPTest_n_2_q; + reg [0:0] redist3_signX_uid27_fpToFxPTest_b_1_q; + reg [0:0] redist4_excN_x_uid16_fpToFxPTest_q_1_q; + reg [22:0] redist5_frac_x_uid10_fpToFxPTest_b_1_q; + + + // maxNegValueU_uid45_fpToFxPTest(CONSTANT,44) + assign maxNegValueU_uid45_fpToFxPTest_q = 32'b00000000000000000000000000000000; + + // maxPosValueU_uid44_fpToFxPTest(CONSTANT,43) + assign maxPosValueU_uid44_fpToFxPTest_q = 32'b11111111111111111111111111111111; + + // VCC(CONSTANT,1) + assign VCC_q = 1'b1; + + // GND(CONSTANT,0) + assign GND_q = 1'b0; + + // rightShiftStage2Idx3_uid87_rightShiferNoStickyOut_uid43_fpToFxPTest(CONSTANT,86) + assign rightShiftStage2Idx3_uid87_rightShiferNoStickyOut_uid43_fpToFxPTest_q = 33'b000000000000000000000000000000000; + + // rightShiftStage2Idx2Rng32_uid84_rightShiferNoStickyOut_uid43_fpToFxPTest(BITSELECT,83)@1 + assign rightShiftStage2Idx2Rng32_uid84_rightShiferNoStickyOut_uid43_fpToFxPTest_b = rightShiftStage1_uid80_rightShiferNoStickyOut_uid43_fpToFxPTest_q[32:32]; + + // rightShiftStage2Idx2_uid86_rightShiferNoStickyOut_uid43_fpToFxPTest(BITJOIN,85)@1 + assign rightShiftStage2Idx2_uid86_rightShiferNoStickyOut_uid43_fpToFxPTest_q = {maxNegValueU_uid45_fpToFxPTest_q, rightShiftStage2Idx2Rng32_uid84_rightShiferNoStickyOut_uid43_fpToFxPTest_b}; + + // rightShiftStage2Idx1Pad16_uid82_rightShiferNoStickyOut_uid43_fpToFxPTest(CONSTANT,81) + assign rightShiftStage2Idx1Pad16_uid82_rightShiferNoStickyOut_uid43_fpToFxPTest_q = 16'b0000000000000000; + + // rightShiftStage2Idx1Rng16_uid81_rightShiferNoStickyOut_uid43_fpToFxPTest(BITSELECT,80)@1 + assign rightShiftStage2Idx1Rng16_uid81_rightShiferNoStickyOut_uid43_fpToFxPTest_b = rightShiftStage1_uid80_rightShiferNoStickyOut_uid43_fpToFxPTest_q[32:16]; + + // rightShiftStage2Idx1_uid83_rightShiferNoStickyOut_uid43_fpToFxPTest(BITJOIN,82)@1 + assign rightShiftStage2Idx1_uid83_rightShiferNoStickyOut_uid43_fpToFxPTest_q = {rightShiftStage2Idx1Pad16_uid82_rightShiferNoStickyOut_uid43_fpToFxPTest_q, rightShiftStage2Idx1Rng16_uid81_rightShiferNoStickyOut_uid43_fpToFxPTest_b}; + + // rightShiftStage1Idx3Pad12_uid77_rightShiferNoStickyOut_uid43_fpToFxPTest(CONSTANT,76) + assign rightShiftStage1Idx3Pad12_uid77_rightShiferNoStickyOut_uid43_fpToFxPTest_q = 12'b000000000000; + + // rightShiftStage1Idx3Rng12_uid76_rightShiferNoStickyOut_uid43_fpToFxPTest(BITSELECT,75)@1 + assign rightShiftStage1Idx3Rng12_uid76_rightShiferNoStickyOut_uid43_fpToFxPTest_b = rightShiftStage0_uid69_rightShiferNoStickyOut_uid43_fpToFxPTest_q[32:12]; + + // rightShiftStage1Idx3_uid78_rightShiferNoStickyOut_uid43_fpToFxPTest(BITJOIN,77)@1 + assign rightShiftStage1Idx3_uid78_rightShiferNoStickyOut_uid43_fpToFxPTest_q = {rightShiftStage1Idx3Pad12_uid77_rightShiferNoStickyOut_uid43_fpToFxPTest_q, rightShiftStage1Idx3Rng12_uid76_rightShiferNoStickyOut_uid43_fpToFxPTest_b}; + + // cstAllZWE_uid8_fpToFxPTest(CONSTANT,7) + assign cstAllZWE_uid8_fpToFxPTest_q = 8'b00000000; + + // rightShiftStage1Idx2Rng8_uid73_rightShiferNoStickyOut_uid43_fpToFxPTest(BITSELECT,72)@1 + assign rightShiftStage1Idx2Rng8_uid73_rightShiferNoStickyOut_uid43_fpToFxPTest_b = rightShiftStage0_uid69_rightShiferNoStickyOut_uid43_fpToFxPTest_q[32:8]; + + // rightShiftStage1Idx2_uid75_rightShiferNoStickyOut_uid43_fpToFxPTest(BITJOIN,74)@1 + assign rightShiftStage1Idx2_uid75_rightShiferNoStickyOut_uid43_fpToFxPTest_q = {cstAllZWE_uid8_fpToFxPTest_q, rightShiftStage1Idx2Rng8_uid73_rightShiferNoStickyOut_uid43_fpToFxPTest_b}; + + // rightShiftStage1Idx1Pad4_uid71_rightShiferNoStickyOut_uid43_fpToFxPTest(CONSTANT,70) + assign rightShiftStage1Idx1Pad4_uid71_rightShiferNoStickyOut_uid43_fpToFxPTest_q = 4'b0000; + + // rightShiftStage1Idx1Rng4_uid70_rightShiferNoStickyOut_uid43_fpToFxPTest(BITSELECT,69)@1 + assign rightShiftStage1Idx1Rng4_uid70_rightShiferNoStickyOut_uid43_fpToFxPTest_b = rightShiftStage0_uid69_rightShiferNoStickyOut_uid43_fpToFxPTest_q[32:4]; + + // rightShiftStage1Idx1_uid72_rightShiferNoStickyOut_uid43_fpToFxPTest(BITJOIN,71)@1 + assign rightShiftStage1Idx1_uid72_rightShiferNoStickyOut_uid43_fpToFxPTest_q = {rightShiftStage1Idx1Pad4_uid71_rightShiferNoStickyOut_uid43_fpToFxPTest_q, rightShiftStage1Idx1Rng4_uid70_rightShiferNoStickyOut_uid43_fpToFxPTest_b}; + + // rightShiftStage0Idx3Pad3_uid66_rightShiferNoStickyOut_uid43_fpToFxPTest(CONSTANT,65) + assign rightShiftStage0Idx3Pad3_uid66_rightShiferNoStickyOut_uid43_fpToFxPTest_q = 3'b000; + + // rightShiftStage0Idx3Rng3_uid65_rightShiferNoStickyOut_uid43_fpToFxPTest(BITSELECT,64)@1 + assign rightShiftStage0Idx3Rng3_uid65_rightShiferNoStickyOut_uid43_fpToFxPTest_b = shifterIn_uid42_fpToFxPTest_q[32:3]; + + // rightShiftStage0Idx3_uid67_rightShiferNoStickyOut_uid43_fpToFxPTest(BITJOIN,66)@1 + assign rightShiftStage0Idx3_uid67_rightShiferNoStickyOut_uid43_fpToFxPTest_q = {rightShiftStage0Idx3Pad3_uid66_rightShiferNoStickyOut_uid43_fpToFxPTest_q, rightShiftStage0Idx3Rng3_uid65_rightShiferNoStickyOut_uid43_fpToFxPTest_b}; + + // rightShiftStage0Idx2Pad2_uid63_rightShiferNoStickyOut_uid43_fpToFxPTest(CONSTANT,62) + assign rightShiftStage0Idx2Pad2_uid63_rightShiferNoStickyOut_uid43_fpToFxPTest_q = 2'b00; + + // rightShiftStage0Idx2Rng2_uid62_rightShiferNoStickyOut_uid43_fpToFxPTest(BITSELECT,61)@1 + assign rightShiftStage0Idx2Rng2_uid62_rightShiferNoStickyOut_uid43_fpToFxPTest_b = shifterIn_uid42_fpToFxPTest_q[32:2]; + + // rightShiftStage0Idx2_uid64_rightShiferNoStickyOut_uid43_fpToFxPTest(BITJOIN,63)@1 + assign rightShiftStage0Idx2_uid64_rightShiferNoStickyOut_uid43_fpToFxPTest_q = {rightShiftStage0Idx2Pad2_uid63_rightShiferNoStickyOut_uid43_fpToFxPTest_q, rightShiftStage0Idx2Rng2_uid62_rightShiferNoStickyOut_uid43_fpToFxPTest_b}; + + // rightShiftStage0Idx1Rng1_uid59_rightShiferNoStickyOut_uid43_fpToFxPTest(BITSELECT,58)@1 + assign rightShiftStage0Idx1Rng1_uid59_rightShiferNoStickyOut_uid43_fpToFxPTest_b = shifterIn_uid42_fpToFxPTest_q[32:1]; + + // rightShiftStage0Idx1_uid61_rightShiferNoStickyOut_uid43_fpToFxPTest(BITJOIN,60)@1 + assign rightShiftStage0Idx1_uid61_rightShiferNoStickyOut_uid43_fpToFxPTest_q = {GND_q, rightShiftStage0Idx1Rng1_uid59_rightShiferNoStickyOut_uid43_fpToFxPTest_b}; + + // exp_x_uid9_fpToFxPTest(BITSELECT,8)@0 + assign exp_x_uid9_fpToFxPTest_b = a[30:23]; + + // excZ_x_uid11_fpToFxPTest(LOGICAL,10)@0 + 1 + assign excZ_x_uid11_fpToFxPTest_qi = exp_x_uid9_fpToFxPTest_b == cstAllZWE_uid8_fpToFxPTest_q ? 1'b1 : 1'b0; + dspba_delay_ver #( .width(1), .depth(1), .reset_kind("SYNC"), .phase(0), .modulus(1) ) + excZ_x_uid11_fpToFxPTest_delay ( .xin(excZ_x_uid11_fpToFxPTest_qi), .xout(excZ_x_uid11_fpToFxPTest_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // invExcXZ_uid24_fpToFxPTest(LOGICAL,23)@1 + assign invExcXZ_uid24_fpToFxPTest_q = ~ (excZ_x_uid11_fpToFxPTest_q); + + // cstZeroWF_uid7_fpToFxPTest(CONSTANT,6) + assign cstZeroWF_uid7_fpToFxPTest_q = 23'b00000000000000000000000; + + // frac_x_uid10_fpToFxPTest(BITSELECT,9)@0 + assign frac_x_uid10_fpToFxPTest_b = a[22:0]; + + // redist5_frac_x_uid10_fpToFxPTest_b_1(DELAY,96) + always @ (posedge clk) + begin + if (areset) + begin + redist5_frac_x_uid10_fpToFxPTest_b_1_q <= '0; + end + else if (en == 1'b1) + begin + redist5_frac_x_uid10_fpToFxPTest_b_1_q <= frac_x_uid10_fpToFxPTest_b; + end + end + + // fracPostZ_uid23_fpToFxPTest(MUX,22)@1 + assign fracPostZ_uid23_fpToFxPTest_s = excZ_x_uid11_fpToFxPTest_q; + always @(fracPostZ_uid23_fpToFxPTest_s or en or redist5_frac_x_uid10_fpToFxPTest_b_1_q or cstZeroWF_uid7_fpToFxPTest_q) + begin + unique case (fracPostZ_uid23_fpToFxPTest_s) + 1'b0 : fracPostZ_uid23_fpToFxPTest_q = redist5_frac_x_uid10_fpToFxPTest_b_1_q; + 1'b1 : fracPostZ_uid23_fpToFxPTest_q = cstZeroWF_uid7_fpToFxPTest_q; + default : fracPostZ_uid23_fpToFxPTest_q = 23'b0; + endcase + end + + // oFracX_uid25_fpToFxPTest(BITJOIN,24)@1 + assign oFracX_uid25_fpToFxPTest_q = {invExcXZ_uid24_fpToFxPTest_q, fracPostZ_uid23_fpToFxPTest_q}; + + // zPadd_uid41_fpToFxPTest(CONSTANT,40) + assign zPadd_uid41_fpToFxPTest_q = 9'b000000000; + + // shifterIn_uid42_fpToFxPTest(BITJOIN,41)@1 + assign shifterIn_uid42_fpToFxPTest_q = {oFracX_uid25_fpToFxPTest_q, zPadd_uid41_fpToFxPTest_q}; + + // rightShiftStage0_uid69_rightShiferNoStickyOut_uid43_fpToFxPTest(MUX,68)@1 + assign rightShiftStage0_uid69_rightShiferNoStickyOut_uid43_fpToFxPTest_s = rightShiftStageSel0Dto0_uid68_rightShiferNoStickyOut_uid43_fpToFxPTest_merged_bit_select_b; + always @(rightShiftStage0_uid69_rightShiferNoStickyOut_uid43_fpToFxPTest_s or en or shifterIn_uid42_fpToFxPTest_q or rightShiftStage0Idx1_uid61_rightShiferNoStickyOut_uid43_fpToFxPTest_q or rightShiftStage0Idx2_uid64_rightShiferNoStickyOut_uid43_fpToFxPTest_q or rightShiftStage0Idx3_uid67_rightShiferNoStickyOut_uid43_fpToFxPTest_q) + begin + unique case (rightShiftStage0_uid69_rightShiferNoStickyOut_uid43_fpToFxPTest_s) + 2'b00 : rightShiftStage0_uid69_rightShiferNoStickyOut_uid43_fpToFxPTest_q = shifterIn_uid42_fpToFxPTest_q; + 2'b01 : rightShiftStage0_uid69_rightShiferNoStickyOut_uid43_fpToFxPTest_q = rightShiftStage0Idx1_uid61_rightShiferNoStickyOut_uid43_fpToFxPTest_q; + 2'b10 : rightShiftStage0_uid69_rightShiferNoStickyOut_uid43_fpToFxPTest_q = rightShiftStage0Idx2_uid64_rightShiferNoStickyOut_uid43_fpToFxPTest_q; + 2'b11 : rightShiftStage0_uid69_rightShiferNoStickyOut_uid43_fpToFxPTest_q = rightShiftStage0Idx3_uid67_rightShiferNoStickyOut_uid43_fpToFxPTest_q; + default : rightShiftStage0_uid69_rightShiferNoStickyOut_uid43_fpToFxPTest_q = 33'b0; + endcase + end + + // rightShiftStage1_uid80_rightShiferNoStickyOut_uid43_fpToFxPTest(MUX,79)@1 + assign rightShiftStage1_uid80_rightShiferNoStickyOut_uid43_fpToFxPTest_s = rightShiftStageSel0Dto0_uid68_rightShiferNoStickyOut_uid43_fpToFxPTest_merged_bit_select_c; + always @(rightShiftStage1_uid80_rightShiferNoStickyOut_uid43_fpToFxPTest_s or en or rightShiftStage0_uid69_rightShiferNoStickyOut_uid43_fpToFxPTest_q or rightShiftStage1Idx1_uid72_rightShiferNoStickyOut_uid43_fpToFxPTest_q or rightShiftStage1Idx2_uid75_rightShiferNoStickyOut_uid43_fpToFxPTest_q or rightShiftStage1Idx3_uid78_rightShiferNoStickyOut_uid43_fpToFxPTest_q) + begin + unique case (rightShiftStage1_uid80_rightShiferNoStickyOut_uid43_fpToFxPTest_s) + 2'b00 : rightShiftStage1_uid80_rightShiferNoStickyOut_uid43_fpToFxPTest_q = rightShiftStage0_uid69_rightShiferNoStickyOut_uid43_fpToFxPTest_q; + 2'b01 : rightShiftStage1_uid80_rightShiferNoStickyOut_uid43_fpToFxPTest_q = rightShiftStage1Idx1_uid72_rightShiferNoStickyOut_uid43_fpToFxPTest_q; + 2'b10 : rightShiftStage1_uid80_rightShiferNoStickyOut_uid43_fpToFxPTest_q = rightShiftStage1Idx2_uid75_rightShiferNoStickyOut_uid43_fpToFxPTest_q; + 2'b11 : rightShiftStage1_uid80_rightShiferNoStickyOut_uid43_fpToFxPTest_q = rightShiftStage1Idx3_uid78_rightShiferNoStickyOut_uid43_fpToFxPTest_q; + default : rightShiftStage1_uid80_rightShiferNoStickyOut_uid43_fpToFxPTest_q = 33'b0; + endcase + end + + // maxShiftCst_uid38_fpToFxPTest(CONSTANT,37) + assign maxShiftCst_uid38_fpToFxPTest_q = 6'b100001; + + // ovfExpVal_uid35_fpToFxPTest(CONSTANT,34) + assign ovfExpVal_uid35_fpToFxPTest_q = 9'b010011110; + + // shiftValE_uid36_fpToFxPTest(SUB,35)@0 + assign shiftValE_uid36_fpToFxPTest_a = {{2{ovfExpVal_uid35_fpToFxPTest_q[8]}}, ovfExpVal_uid35_fpToFxPTest_q}; + assign shiftValE_uid36_fpToFxPTest_b = {3'b000, exp_x_uid9_fpToFxPTest_b}; + assign shiftValE_uid36_fpToFxPTest_o = $signed(shiftValE_uid36_fpToFxPTest_a) - $signed(shiftValE_uid36_fpToFxPTest_b); + assign shiftValE_uid36_fpToFxPTest_q = shiftValE_uid36_fpToFxPTest_o[9:0]; + + // shiftValRaw_uid37_fpToFxPTest(BITSELECT,36)@0 + assign shiftValRaw_uid37_fpToFxPTest_in = shiftValE_uid36_fpToFxPTest_q[5:0]; + assign shiftValRaw_uid37_fpToFxPTest_b = shiftValRaw_uid37_fpToFxPTest_in[5:0]; + + // shiftOutOfRange_uid39_fpToFxPTest(COMPARE,38)@0 + assign shiftOutOfRange_uid39_fpToFxPTest_a = {{2{shiftValE_uid36_fpToFxPTest_q[9]}}, shiftValE_uid36_fpToFxPTest_q}; + assign shiftOutOfRange_uid39_fpToFxPTest_b = {6'b000000, maxShiftCst_uid38_fpToFxPTest_q}; + assign shiftOutOfRange_uid39_fpToFxPTest_o = $signed(shiftOutOfRange_uid39_fpToFxPTest_a) - $signed(shiftOutOfRange_uid39_fpToFxPTest_b); + assign shiftOutOfRange_uid39_fpToFxPTest_n[0] = ~ (shiftOutOfRange_uid39_fpToFxPTest_o[11]); + + // shiftVal_uid40_fpToFxPTest(MUX,39)@0 + 1 + assign shiftVal_uid40_fpToFxPTest_s = shiftOutOfRange_uid39_fpToFxPTest_n; + always @ (posedge clk) + begin + if (areset) + begin + shiftVal_uid40_fpToFxPTest_q <= 6'b0; + end + else if (en == 1'b1) + begin + unique case (shiftVal_uid40_fpToFxPTest_s) + 1'b0 : shiftVal_uid40_fpToFxPTest_q <= shiftValRaw_uid37_fpToFxPTest_b; + 1'b1 : shiftVal_uid40_fpToFxPTest_q <= maxShiftCst_uid38_fpToFxPTest_q; + default : shiftVal_uid40_fpToFxPTest_q <= 6'b0; + endcase + end + end + + // rightShiftStageSel0Dto0_uid68_rightShiferNoStickyOut_uid43_fpToFxPTest_merged_bit_select(BITSELECT,90)@1 + assign rightShiftStageSel0Dto0_uid68_rightShiferNoStickyOut_uid43_fpToFxPTest_merged_bit_select_b = shiftVal_uid40_fpToFxPTest_q[1:0]; + assign rightShiftStageSel0Dto0_uid68_rightShiferNoStickyOut_uid43_fpToFxPTest_merged_bit_select_c = shiftVal_uid40_fpToFxPTest_q[3:2]; + assign rightShiftStageSel0Dto0_uid68_rightShiferNoStickyOut_uid43_fpToFxPTest_merged_bit_select_d = shiftVal_uid40_fpToFxPTest_q[5:4]; + + // rightShiftStage2_uid89_rightShiferNoStickyOut_uid43_fpToFxPTest(MUX,88)@1 + 1 + assign rightShiftStage2_uid89_rightShiferNoStickyOut_uid43_fpToFxPTest_s = rightShiftStageSel0Dto0_uid68_rightShiferNoStickyOut_uid43_fpToFxPTest_merged_bit_select_d; + always @ (posedge clk) + begin + if (areset) + begin + rightShiftStage2_uid89_rightShiferNoStickyOut_uid43_fpToFxPTest_q <= 33'b0; + end + else if (en == 1'b1) + begin + unique case (rightShiftStage2_uid89_rightShiferNoStickyOut_uid43_fpToFxPTest_s) + 2'b00 : rightShiftStage2_uid89_rightShiferNoStickyOut_uid43_fpToFxPTest_q <= rightShiftStage1_uid80_rightShiferNoStickyOut_uid43_fpToFxPTest_q; + 2'b01 : rightShiftStage2_uid89_rightShiferNoStickyOut_uid43_fpToFxPTest_q <= rightShiftStage2Idx1_uid83_rightShiferNoStickyOut_uid43_fpToFxPTest_q; + 2'b10 : rightShiftStage2_uid89_rightShiferNoStickyOut_uid43_fpToFxPTest_q <= rightShiftStage2Idx2_uid86_rightShiferNoStickyOut_uid43_fpToFxPTest_q; + 2'b11 : rightShiftStage2_uid89_rightShiferNoStickyOut_uid43_fpToFxPTest_q <= rightShiftStage2Idx3_uid87_rightShiferNoStickyOut_uid43_fpToFxPTest_q; + default : rightShiftStage2_uid89_rightShiferNoStickyOut_uid43_fpToFxPTest_q <= 33'b0; + endcase + end + end + + // zRightShiferNoStickyOut_uid47_fpToFxPTest(BITJOIN,46)@2 + assign zRightShiferNoStickyOut_uid47_fpToFxPTest_q = {GND_q, rightShiftStage2_uid89_rightShiferNoStickyOut_uid43_fpToFxPTest_q}; + + // sPostRndFull_uid48_fpToFxPTest(ADD,47)@2 + assign sPostRndFull_uid48_fpToFxPTest_a = {1'b0, zRightShiferNoStickyOut_uid47_fpToFxPTest_q}; + assign sPostRndFull_uid48_fpToFxPTest_b = {34'b0000000000000000000000000000000000, VCC_q}; + assign sPostRndFull_uid48_fpToFxPTest_o = $unsigned(sPostRndFull_uid48_fpToFxPTest_a) + $unsigned(sPostRndFull_uid48_fpToFxPTest_b); + assign sPostRndFull_uid48_fpToFxPTest_q = sPostRndFull_uid48_fpToFxPTest_o[34:0]; + + // sPostRnd_uid49_fpToFxPTest(BITSELECT,48)@2 + assign sPostRnd_uid49_fpToFxPTest_in = sPostRndFull_uid48_fpToFxPTest_q[32:0]; + assign sPostRnd_uid49_fpToFxPTest_b = sPostRnd_uid49_fpToFxPTest_in[32:1]; + + // redist0_sPostRnd_uid49_fpToFxPTest_b_1(DELAY,91) + always @ (posedge clk) + begin + if (areset) + begin + redist0_sPostRnd_uid49_fpToFxPTest_b_1_q <= '0; + end + else if (en == 1'b1) + begin + redist0_sPostRnd_uid49_fpToFxPTest_b_1_q <= sPostRnd_uid49_fpToFxPTest_b; + end + end + + // signX_uid27_fpToFxPTest(BITSELECT,26)@0 + assign signX_uid27_fpToFxPTest_b = a[31:31]; + + // redist3_signX_uid27_fpToFxPTest_b_1(DELAY,94) + always @ (posedge clk) + begin + if (areset) + begin + redist3_signX_uid27_fpToFxPTest_b_1_q <= '0; + end + else if (en == 1'b1) + begin + redist3_signX_uid27_fpToFxPTest_b_1_q <= signX_uid27_fpToFxPTest_b; + end + end + + // fracXIsZero_uid13_fpToFxPTest(LOGICAL,12)@1 + assign fracXIsZero_uid13_fpToFxPTest_q = cstZeroWF_uid7_fpToFxPTest_q == redist5_frac_x_uid10_fpToFxPTest_b_1_q ? 1'b1 : 1'b0; + + // fracXIsNotZero_uid14_fpToFxPTest(LOGICAL,13)@1 + assign fracXIsNotZero_uid14_fpToFxPTest_q = ~ (fracXIsZero_uid13_fpToFxPTest_q); + + // cstAllOWE_uid6_fpToFxPTest(CONSTANT,5) + assign cstAllOWE_uid6_fpToFxPTest_q = 8'b11111111; + + // expXIsMax_uid12_fpToFxPTest(LOGICAL,11)@0 + 1 + assign expXIsMax_uid12_fpToFxPTest_qi = exp_x_uid9_fpToFxPTest_b == cstAllOWE_uid6_fpToFxPTest_q ? 1'b1 : 1'b0; + dspba_delay_ver #( .width(1), .depth(1), .reset_kind("SYNC"), .phase(0), .modulus(1) ) + expXIsMax_uid12_fpToFxPTest_delay ( .xin(expXIsMax_uid12_fpToFxPTest_qi), .xout(expXIsMax_uid12_fpToFxPTest_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // excN_x_uid16_fpToFxPTest(LOGICAL,15)@1 + assign excN_x_uid16_fpToFxPTest_q = expXIsMax_uid12_fpToFxPTest_q & fracXIsNotZero_uid14_fpToFxPTest_q; + + // notNan_uid28_fpToFxPTest(LOGICAL,27)@1 + assign notNan_uid28_fpToFxPTest_q = ~ (excN_x_uid16_fpToFxPTest_q); + + // signX_uid29_fpToFxPTest(LOGICAL,28)@1 + 1 + assign signX_uid29_fpToFxPTest_qi = notNan_uid28_fpToFxPTest_q & redist3_signX_uid27_fpToFxPTest_b_1_q; + dspba_delay_ver #( .width(1), .depth(1), .reset_kind("SYNC"), .phase(0), .modulus(1) ) + signX_uid29_fpToFxPTest_delay ( .xin(signX_uid29_fpToFxPTest_qi), .xout(signX_uid29_fpToFxPTest_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // udfExpVal_uid33_fpToFxPTest(CONSTANT,32) + assign udfExpVal_uid33_fpToFxPTest_q = 8'b01111101; + + // udf_uid34_fpToFxPTest(COMPARE,33)@0 + 1 + assign udf_uid34_fpToFxPTest_a = {{3{udfExpVal_uid33_fpToFxPTest_q[7]}}, udfExpVal_uid33_fpToFxPTest_q}; + assign udf_uid34_fpToFxPTest_b = {3'b000, exp_x_uid9_fpToFxPTest_b}; + always @ (posedge clk) + begin + if (areset) + begin + udf_uid34_fpToFxPTest_o <= 11'b0; + end + else if (en == 1'b1) + begin + udf_uid34_fpToFxPTest_o <= $signed(udf_uid34_fpToFxPTest_a) - $signed(udf_uid34_fpToFxPTest_b); + end + end + assign udf_uid34_fpToFxPTest_n[0] = ~ (udf_uid34_fpToFxPTest_o[10]); + + // redist1_udf_uid34_fpToFxPTest_n_2(DELAY,92) + always @ (posedge clk) + begin + if (areset) + begin + redist1_udf_uid34_fpToFxPTest_n_2_q <= '0; + end + else if (en == 1'b1) + begin + redist1_udf_uid34_fpToFxPTest_n_2_q <= udf_uid34_fpToFxPTest_n; + end + end + + // sPostRndFullMSBU_uid50_fpToFxPTest(BITSELECT,49)@2 + assign sPostRndFullMSBU_uid50_fpToFxPTest_in = sPostRndFull_uid48_fpToFxPTest_q[33:0]; + assign sPostRndFullMSBU_uid50_fpToFxPTest_b = sPostRndFullMSBU_uid50_fpToFxPTest_in[33:33]; + + // ovfExpVal_uid30_fpToFxPTest(CONSTANT,29) + assign ovfExpVal_uid30_fpToFxPTest_q = 9'b010011111; + + // ovf_uid31_fpToFxPTest(COMPARE,30)@0 + 1 + assign ovf_uid31_fpToFxPTest_a = {3'b000, exp_x_uid9_fpToFxPTest_b}; + assign ovf_uid31_fpToFxPTest_b = {{2{ovfExpVal_uid30_fpToFxPTest_q[8]}}, ovfExpVal_uid30_fpToFxPTest_q}; + always @ (posedge clk) + begin + if (areset) + begin + ovf_uid31_fpToFxPTest_o <= 11'b0; + end + else if (en == 1'b1) + begin + ovf_uid31_fpToFxPTest_o <= $signed(ovf_uid31_fpToFxPTest_a) - $signed(ovf_uid31_fpToFxPTest_b); + end + end + assign ovf_uid31_fpToFxPTest_n[0] = ~ (ovf_uid31_fpToFxPTest_o[10]); + + // redist2_ovf_uid31_fpToFxPTest_n_2(DELAY,93) + always @ (posedge clk) + begin + if (areset) + begin + redist2_ovf_uid31_fpToFxPTest_n_2_q <= '0; + end + else if (en == 1'b1) + begin + redist2_ovf_uid31_fpToFxPTest_n_2_q <= ovf_uid31_fpToFxPTest_n; + end + end + + // negOrOvf_uid32_fpToFxPTest(LOGICAL,31)@2 + assign negOrOvf_uid32_fpToFxPTest_q = signX_uid29_fpToFxPTest_q | redist2_ovf_uid31_fpToFxPTest_n_2_q; + + // excI_x_uid15_fpToFxPTest(LOGICAL,14)@1 + 1 + assign excI_x_uid15_fpToFxPTest_qi = expXIsMax_uid12_fpToFxPTest_q & fracXIsZero_uid13_fpToFxPTest_q; + dspba_delay_ver #( .width(1), .depth(1), .reset_kind("SYNC"), .phase(0), .modulus(1) ) + excI_x_uid15_fpToFxPTest_delay ( .xin(excI_x_uid15_fpToFxPTest_qi), .xout(excI_x_uid15_fpToFxPTest_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // redist4_excN_x_uid16_fpToFxPTest_q_1(DELAY,95) + always @ (posedge clk) + begin + if (areset) + begin + redist4_excN_x_uid16_fpToFxPTest_q_1_q <= '0; + end + else if (en == 1'b1) + begin + redist4_excN_x_uid16_fpToFxPTest_q_1_q <= excN_x_uid16_fpToFxPTest_q; + end + end + + // ovfPostRnd_uid51_fpToFxPTest(LOGICAL,50)@2 + assign ovfPostRnd_uid51_fpToFxPTest_q = redist4_excN_x_uid16_fpToFxPTest_q_1_q | excI_x_uid15_fpToFxPTest_q | negOrOvf_uid32_fpToFxPTest_q | sPostRndFullMSBU_uid50_fpToFxPTest_b; + + // muxSelConc_uid52_fpToFxPTest(BITJOIN,51)@2 + assign muxSelConc_uid52_fpToFxPTest_q = {signX_uid29_fpToFxPTest_q, redist1_udf_uid34_fpToFxPTest_n_2_q, ovfPostRnd_uid51_fpToFxPTest_q}; + + // muxSel_uid53_fpToFxPTest(LOOKUP,52)@2 + 1 + always @ (posedge clk) + begin + if (areset) + begin + muxSel_uid53_fpToFxPTest_q <= 2'b00; + end + else if (en == 1'b1) + begin + unique case (muxSelConc_uid52_fpToFxPTest_q) + 3'b000 : muxSel_uid53_fpToFxPTest_q <= 2'b00; + 3'b001 : muxSel_uid53_fpToFxPTest_q <= 2'b01; + 3'b010 : muxSel_uid53_fpToFxPTest_q <= 2'b11; + 3'b011 : muxSel_uid53_fpToFxPTest_q <= 2'b00; + 3'b100 : muxSel_uid53_fpToFxPTest_q <= 2'b10; + 3'b101 : muxSel_uid53_fpToFxPTest_q <= 2'b10; + 3'b110 : muxSel_uid53_fpToFxPTest_q <= 2'b10; + 3'b111 : muxSel_uid53_fpToFxPTest_q <= 2'b10; + default : begin + // unreachable + muxSel_uid53_fpToFxPTest_q <= 2'bxx; + end + endcase + end + end + + // finalOut_uid55_fpToFxPTest(MUX,54)@3 + assign finalOut_uid55_fpToFxPTest_s = muxSel_uid53_fpToFxPTest_q; + always @(finalOut_uid55_fpToFxPTest_s or en or redist0_sPostRnd_uid49_fpToFxPTest_b_1_q or maxPosValueU_uid44_fpToFxPTest_q or maxNegValueU_uid45_fpToFxPTest_q) + begin + unique case (finalOut_uid55_fpToFxPTest_s) + 2'b00 : finalOut_uid55_fpToFxPTest_q = redist0_sPostRnd_uid49_fpToFxPTest_b_1_q; + 2'b01 : finalOut_uid55_fpToFxPTest_q = maxPosValueU_uid44_fpToFxPTest_q; + 2'b10 : finalOut_uid55_fpToFxPTest_q = maxNegValueU_uid45_fpToFxPTest_q; + 2'b11 : finalOut_uid55_fpToFxPTest_q = maxNegValueU_uid45_fpToFxPTest_q; + default : finalOut_uid55_fpToFxPTest_q = 32'b0; + endcase + end + + // xOut(GPOUT,4)@3 + assign q = finalOut_uid55_fpToFxPTest_q; + +endmodule diff --git a/hw/rtl/fp_cores/altera/stratix10/acl_gen.log b/hw/rtl/fp_cores/altera/stratix10/acl_gen.log new file mode 100644 index 00000000..24e3b78b --- /dev/null +++ b/hw/rtl/fp_cores/altera/stratix10/acl_gen.log @@ -0,0 +1,296 @@ +starting execution ... +build model options ... +argc=22 +Generation context: + Will not generate valid and channel signals + HardFP is enabled enabling set to true + Correct rounding constraint detected + Will not generate valid and channel signals + The new component name is acl_fadd + Frequency 250MHz + Deployment FPGA Stratix10 +Estimated resources LUTs 0, DSPs 2, RAMBits 0, RAMBlocks 0 +The pipeline depth of the block is 3 cycle(s) +@@start +@name FPAdd@ +@latency 3@ +@LUT 0@ +@DSP 2@ +@RAMBits 0@ +@RAMBlockUsage 0@ +@enable 1@ +@subnormals 0@ +@error 0.50@ +@rounding RNE@ +@method single path@ +@inPort 0 fpieee 8 23@ +@inPort 1 fpieee 8 23@ +@outPort 0 fpieee 8 23@ +@nochanvalid 1@ +@@end +starting execution ... +build model options ... +argc=22 +Generation context: + Will not generate valid and channel signals + HardFP is enabled enabling set to true + Correct rounding constraint detected + Will not generate valid and channel signals + The new component name is acl_fsub + Frequency 250MHz + Deployment FPGA Stratix10 +Estimated resources LUTs 0, DSPs 2, RAMBits 0, RAMBlocks 0 +The pipeline depth of the block is 3 cycle(s) +@@start +@name FPSub@ +@latency 3@ +@LUT 0@ +@DSP 2@ +@RAMBits 0@ +@RAMBlockUsage 0@ +@enable 1@ +@subnormals 0@ +@error 0.50@ +@rounding RNE@ +@method single path@ +@inPort 0 fpieee 8 23@ +@inPort 1 fpieee 8 23@ +@outPort 0 fpieee 8 23@ +@nochanvalid 1@ +@@end +starting execution ... +build model options ... +argc=22 +Generation context: + Will not generate valid and channel signals + HardFP is enabled enabling set to true + Correct rounding constraint detected + Will not generate valid and channel signals + The new component name is acl_fmul + Frequency 250MHz + Deployment FPGA Stratix10 +Estimated resources LUTs 0, DSPs 2, RAMBits 0, RAMBlocks 0 +The pipeline depth of the block is 3 cycle(s) +@@start +@name FPMul@ +@latency 3@ +@LUT 0@ +@DSP 2@ +@RAMBits 0@ +@RAMBlockUsage 0@ +@enable 1@ +@subnormals 0@ +@error 0.50@ +@rounding RNE@ +@method default@ +@inPort 0 fpieee 8 23@ +@inPort 1 fpieee 8 23@ +@outPort 0 fpieee 8 23@ +@nochanvalid 1@ +@@end +starting execution ... +build model options ... +argc=22 +Generation context: + Will not generate valid and channel signals + HardFP is enabled enabling set to true + Correct rounding constraint detected + Will not generate valid and channel signals + The new component name is acl_fmadd + Frequency 250MHz + Deployment FPGA Stratix10 +Estimated resources LUTs 0, DSPs 2, RAMBits 0, RAMBlocks 0 +The pipeline depth of the block is 4 cycle(s) +@@start +@name FPMultAdd@ +@latency 4@ +@LUT 0@ +@DSP 2@ +@RAMBits 0@ +@RAMBlockUsage 0@ +@enable 1@ +@subnormals 0@ +@error 0.50@ +@rounding RNE@ +@method multadd@ +@inPort 0 fpieee 8 23@ +@inPort 1 fpieee 8 23@ +@inPort 2 fpieee 8 23@ +@outPort 0 fpieee 8 23@ +@nochanvalid 1@ +@@end +starting execution ... +build model options ... +argc=23 +Generation context: + Will not generate valid and channel signals + HardFP is enabled enabling set to true + Correct rounding constraint detected + Will not generate valid and channel signals + The new component name is acl_fdiv + Frequency 250MHz + Deployment FPGA Stratix10 +Estimated resources LUTs 1232, DSPs 7, RAMBits 34304, RAMBlocks 3 +The pipeline depth of the block is 34 cycle(s) +@@start +@name FPDiv@ +@latency 34@ +@LUT 1232@ +@DSP 7@ +@RAMBits 34304@ +@RAMBlockUsage 3@ +@enable 1@ +@subnormals 0@ +@error 0.50@ +@rounding RNE@ +@method polynomial approximation@ +@inPort 0 fpieee 8 23@ +@inPort 1 fpieee 8 23@ +@outPort 0 fpieee 8 23@ +@nochanvalid 1@ +@@end +starting execution ... +build model options ... +argc=22 +Generation context: + Will not generate valid and channel signals + HardFP is enabled enabling set to true + Correct rounding constraint detected + Will not generate valid and channel signals + The new component name is acl_fsqrt + Frequency 250MHz + Deployment FPGA Stratix10 +Estimated resources LUTs 609, DSPs 5, RAMBits 15872, RAMBlocks 3 +The pipeline depth of the block is 25 cycle(s) +@@start +@name FPSqrt@ +@latency 25@ +@LUT 609@ +@DSP 5@ +@RAMBits 15872@ +@RAMBlockUsage 3@ +@enable 1@ +@subnormals 0@ +@error 0.50@ +@rounding RNE@ +@method polynomial approximation@ +@inPort 0 fpieee 8 23@ +@outPort 0 fpieee 8 23@ +@nochanvalid 1@ +@@end +starting execution ... +build model options ... +argc=25 +Generation context: + Will not generate valid and channel signals + HardFP is enabled enabling set to true + Correct rounding constraint detected + Will not generate valid and channel signals + The new component name is acl_ftoi + Frequency 250MHz + Deployment FPGA Stratix10 +Estimated resources LUTs 344, DSPs 0, RAMBits 0, RAMBlocks 0 +The pipeline depth of the block is 3 cycle(s) +@@start +@name FPToFXP@ +@latency 3@ +@LUT 344@ +@DSP 0@ +@RAMBits 0@ +@RAMBlockUsage 0@ +@enable 1@ +@subnormals 0@ +@error 0.50@ +@rounding RNE@ +@method default@ +@inPort 0 fpieee 8 23@ +@outPort 0 fxp 32 0 1@ +@nochanvalid 1@ +@@end +starting execution ... +build model options ... +argc=25 +Generation context: + Will not generate valid and channel signals + HardFP is enabled enabling set to true + Correct rounding constraint detected + Will not generate valid and channel signals + The new component name is acl_ftou + Frequency 250MHz + Deployment FPGA Stratix10 +Estimated resources LUTs 272, DSPs 0, RAMBits 0, RAMBlocks 0 +The pipeline depth of the block is 3 cycle(s) +@@start +@name FPToFXP@ +@latency 3@ +@LUT 272@ +@DSP 0@ +@RAMBits 0@ +@RAMBlockUsage 0@ +@enable 1@ +@subnormals 0@ +@error 0.50@ +@rounding RNE@ +@method default@ +@inPort 0 fpieee 8 23@ +@outPort 0 fxp 32 0 0@ +@nochanvalid 1@ +@@end +starting execution ... +build model options ... +argc=25 +Generation context: + Will not generate valid and channel signals + HardFP is enabled enabling set to true + Correct rounding constraint detected + Will not generate valid and channel signals + The new component name is acl_itof + Frequency 250MHz + Deployment FPGA Stratix10 +Estimated resources LUTs 362, DSPs 0, RAMBits 0, RAMBlocks 0 +The pipeline depth of the block is 7 cycle(s) +@@start +@name FXPToFP@ +@latency 7@ +@LUT 362@ +@DSP 0@ +@RAMBits 0@ +@RAMBlockUsage 0@ +@enable 1@ +@subnormals 0@ +@error 0.50@ +@rounding RNE@ +@method default@ +@inPort 0 fxp 32 0 1@ +@outPort 0 fpieee 8 23@ +@nochanvalid 1@ +@@end +starting execution ... +build model options ... +argc=25 +Generation context: + Will not generate valid and channel signals + HardFP is enabled enabling set to true + Correct rounding constraint detected + Will not generate valid and channel signals + The new component name is acl_utof + Frequency 300MHz + Deployment FPGA Stratix10 +Estimated resources LUTs 310, DSPs 0, RAMBits 0, RAMBlocks 0 +The pipeline depth of the block is 7 cycle(s) +@@start +@name FXPToFP@ +@latency 7@ +@LUT 310@ +@DSP 0@ +@RAMBits 0@ +@RAMBlockUsage 0@ +@enable 1@ +@subnormals 0@ +@error 0.50@ +@rounding RNE@ +@method default@ +@inPort 0 fxp 32 0 0@ +@outPort 0 fpieee 8 23@ +@nochanvalid 1@ +@@end diff --git a/hw/rtl/fp_cores/altera/stratix10/acl_gen.sh b/hw/rtl/fp_cores/altera/stratix10/acl_gen.sh new file mode 100755 index 00000000..e9d4397e --- /dev/null +++ b/hw/rtl/fp_cores/altera/stratix10/acl_gen.sh @@ -0,0 +1,33 @@ +#!/bin/bash + +FAMILY=Stratix10 +PREFIX=acl + +CMD_POLY_EVAL_PATH=$QUARTUS_HOME/dspba/backend/linux64 + +OPTIONS="-target $FAMILY -noChanValid -enable -enableHardFP 1 -printMachineReadable -lang verilog -correctRounding -noChanValid -enable -speedgrade 2" + +export LD_LIBRARY_PATH=$CMD_POLY_EVAL_PATH:$LD_LIBRARY_PATH + +CMD="$CMD_POLY_EVAL_PATH/cmdPolyEval $OPTIONS" + +EXP_BITS=8 +MAN_BITS=23 + +FBITS="f$(($EXP_BITS + $MAN_BITS + 1))" + +echo Generating IP cores for $FBITS +{ + $CMD -name "$PREFIX"_fadd -frequency 250 FPAdd $EXP_BITS $MAN_BITS + $CMD -name "$PREFIX"_fsub -frequency 250 FPSub $EXP_BITS $MAN_BITS + $CMD -name "$PREFIX"_fmul -frequency 250 FPMul $EXP_BITS $MAN_BITS + $CMD -name "$PREFIX"_fmadd -frequency 250 FPMultAdd $EXP_BITS $MAN_BITS + $CMD -name "$PREFIX"_fdiv -frequency 250 FPDiv $EXP_BITS $MAN_BITS 0 + $CMD -name "$PREFIX"_fsqrt -frequency 250 FPSqrt $EXP_BITS $MAN_BITS + $CMD -name "$PREFIX"_ftoi -frequency 250 FPToFXP $EXP_BITS $MAN_BITS 32 0 1 + $CMD -name "$PREFIX"_ftou -frequency 250 FPToFXP $EXP_BITS $MAN_BITS 32 0 0 + $CMD -name "$PREFIX"_itof -frequency 250 FXPToFP 32 0 1 $EXP_BITS $MAN_BITS + $CMD -name "$PREFIX"_utof -frequency 300 FXPToFP 32 0 0 $EXP_BITS $MAN_BITS +} > acl_gen.log 2>&1 + +#cp $QUARTUS_HOME/dspba/backend/Libraries/sv/base/dspba_library_ver.sv . \ No newline at end of file diff --git a/hw/rtl/fp_cores/altera/stratix10/acl_itof.sv b/hw/rtl/fp_cores/altera/stratix10/acl_itof.sv new file mode 100644 index 00000000..6c9458ef --- /dev/null +++ b/hw/rtl/fp_cores/altera/stratix10/acl_itof.sv @@ -0,0 +1,631 @@ +// ------------------------------------------------------------------------- +// High Level Design Compiler for Intel(R) FPGAs Version 18.1 (Release Build #277) +// Quartus Prime development tool and MATLAB/Simulink Interface +// +// Legal Notice: Copyright 2019 Intel Corporation. All rights reserved. +// Your use of Intel Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly +// subject to the terms and conditions of the Intel FPGA Software License +// Agreement, Intel MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for +// the sole purpose of programming logic devices manufactured by Intel +// and sold by Intel or its authorized distributors. Please refer to the +// applicable agreement for further details. +// --------------------------------------------------------------------------- + +// SystemVerilog created from acl_itof +// SystemVerilog created on Sun Dec 27 09:48:58 2020 + + +(* altera_attribute = "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410; -name MESSAGE_DISABLE 113007; -name MESSAGE_DISABLE 10958" *) +module acl_itof ( + input wire [31:0] a, + input wire [0:0] en, + output wire [31:0] q, + input wire clk, + input wire areset + ); + + wire [0:0] GND_q; + wire [0:0] signX_uid6_fxpToFPTest_b; + wire [31:0] xXorSign_uid7_fxpToFPTest_b; + wire [31:0] xXorSign_uid7_fxpToFPTest_q; + wire [32:0] yE_uid8_fxpToFPTest_a; + wire [32:0] yE_uid8_fxpToFPTest_b; + logic [32:0] yE_uid8_fxpToFPTest_o; + wire [32:0] yE_uid8_fxpToFPTest_q; + wire [31:0] y_uid9_fxpToFPTest_in; + wire [31:0] y_uid9_fxpToFPTest_b; + wire [5:0] maxCount_uid11_fxpToFPTest_q; + wire [0:0] inIsZero_uid12_fxpToFPTest_qi; + reg [0:0] inIsZero_uid12_fxpToFPTest_q; + wire [7:0] msbIn_uid13_fxpToFPTest_q; + wire [8:0] expPreRnd_uid14_fxpToFPTest_a; + wire [8:0] expPreRnd_uid14_fxpToFPTest_b; + logic [8:0] expPreRnd_uid14_fxpToFPTest_o; + wire [8:0] expPreRnd_uid14_fxpToFPTest_q; + wire [32:0] expFracRnd_uid16_fxpToFPTest_q; + wire [0:0] sticky_uid20_fxpToFPTest_qi; + reg [0:0] sticky_uid20_fxpToFPTest_q; + wire [0:0] nr_uid21_fxpToFPTest_q; + wire [0:0] rnd_uid22_fxpToFPTest_q; + wire [34:0] expFracR_uid24_fxpToFPTest_a; + wire [34:0] expFracR_uid24_fxpToFPTest_b; + logic [34:0] expFracR_uid24_fxpToFPTest_o; + wire [33:0] expFracR_uid24_fxpToFPTest_q; + wire [23:0] fracR_uid25_fxpToFPTest_in; + wire [22:0] fracR_uid25_fxpToFPTest_b; + wire [9:0] expR_uid26_fxpToFPTest_b; + wire [11:0] udf_uid27_fxpToFPTest_a; + wire [11:0] udf_uid27_fxpToFPTest_b; + logic [11:0] udf_uid27_fxpToFPTest_o; + wire [0:0] udf_uid27_fxpToFPTest_n; + wire [7:0] expInf_uid28_fxpToFPTest_q; + wire [11:0] ovf_uid29_fxpToFPTest_a; + wire [11:0] ovf_uid29_fxpToFPTest_b; + logic [11:0] ovf_uid29_fxpToFPTest_o; + wire [0:0] ovf_uid29_fxpToFPTest_n; + wire [0:0] excSelector_uid30_fxpToFPTest_q; + wire [22:0] fracZ_uid31_fxpToFPTest_q; + wire [0:0] fracRPostExc_uid32_fxpToFPTest_s; + reg [22:0] fracRPostExc_uid32_fxpToFPTest_q; + wire [0:0] udfOrInZero_uid33_fxpToFPTest_q; + wire [1:0] excSelector_uid34_fxpToFPTest_q; + wire [7:0] expZ_uid37_fxpToFPTest_q; + wire [7:0] expR_uid38_fxpToFPTest_in; + wire [7:0] expR_uid38_fxpToFPTest_b; + wire [1:0] expRPostExc_uid39_fxpToFPTest_s; + reg [7:0] expRPostExc_uid39_fxpToFPTest_q; + wire [31:0] outRes_uid40_fxpToFPTest_q; + wire [31:0] zs_uid42_lzcShifterZ1_uid10_fxpToFPTest_q; + wire [0:0] vCount_uid44_lzcShifterZ1_uid10_fxpToFPTest_qi; + reg [0:0] vCount_uid44_lzcShifterZ1_uid10_fxpToFPTest_q; + wire [0:0] vStagei_uid46_lzcShifterZ1_uid10_fxpToFPTest_s; + reg [31:0] vStagei_uid46_lzcShifterZ1_uid10_fxpToFPTest_q; + wire [15:0] zs_uid47_lzcShifterZ1_uid10_fxpToFPTest_q; + wire [0:0] vCount_uid49_lzcShifterZ1_uid10_fxpToFPTest_q; + wire [31:0] cStage_uid52_lzcShifterZ1_uid10_fxpToFPTest_q; + wire [0:0] vStagei_uid53_lzcShifterZ1_uid10_fxpToFPTest_s; + reg [31:0] vStagei_uid53_lzcShifterZ1_uid10_fxpToFPTest_q; + wire [0:0] vCount_uid56_lzcShifterZ1_uid10_fxpToFPTest_q; + wire [31:0] cStage_uid59_lzcShifterZ1_uid10_fxpToFPTest_q; + wire [0:0] vStagei_uid60_lzcShifterZ1_uid10_fxpToFPTest_s; + reg [31:0] vStagei_uid60_lzcShifterZ1_uid10_fxpToFPTest_q; + wire [3:0] zs_uid61_lzcShifterZ1_uid10_fxpToFPTest_q; + wire [0:0] vCount_uid63_lzcShifterZ1_uid10_fxpToFPTest_q; + wire [31:0] cStage_uid66_lzcShifterZ1_uid10_fxpToFPTest_q; + wire [0:0] vStagei_uid67_lzcShifterZ1_uid10_fxpToFPTest_s; + reg [31:0] vStagei_uid67_lzcShifterZ1_uid10_fxpToFPTest_q; + wire [1:0] zs_uid68_lzcShifterZ1_uid10_fxpToFPTest_q; + wire [0:0] vCount_uid70_lzcShifterZ1_uid10_fxpToFPTest_q; + wire [31:0] cStage_uid73_lzcShifterZ1_uid10_fxpToFPTest_q; + wire [0:0] vStagei_uid74_lzcShifterZ1_uid10_fxpToFPTest_s; + reg [31:0] vStagei_uid74_lzcShifterZ1_uid10_fxpToFPTest_q; + wire [0:0] vCount_uid77_lzcShifterZ1_uid10_fxpToFPTest_q; + wire [31:0] cStage_uid80_lzcShifterZ1_uid10_fxpToFPTest_q; + wire [0:0] vStagei_uid81_lzcShifterZ1_uid10_fxpToFPTest_s; + reg [31:0] vStagei_uid81_lzcShifterZ1_uid10_fxpToFPTest_q; + wire [5:0] vCount_uid82_lzcShifterZ1_uid10_fxpToFPTest_q; + wire [7:0] vCountBig_uid84_lzcShifterZ1_uid10_fxpToFPTest_a; + wire [7:0] vCountBig_uid84_lzcShifterZ1_uid10_fxpToFPTest_b; + logic [7:0] vCountBig_uid84_lzcShifterZ1_uid10_fxpToFPTest_o; + wire [0:0] vCountBig_uid84_lzcShifterZ1_uid10_fxpToFPTest_c; + wire [0:0] vCountFinal_uid86_lzcShifterZ1_uid10_fxpToFPTest_s; + reg [5:0] vCountFinal_uid86_lzcShifterZ1_uid10_fxpToFPTest_q; + wire [1:0] l_uid17_fxpToFPTest_merged_bit_select_in; + wire [0:0] l_uid17_fxpToFPTest_merged_bit_select_b; + wire [0:0] l_uid17_fxpToFPTest_merged_bit_select_c; + wire [15:0] rVStage_uid48_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_b; + wire [15:0] rVStage_uid48_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_c; + wire [7:0] rVStage_uid55_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_b; + wire [23:0] rVStage_uid55_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_c; + wire [3:0] rVStage_uid62_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_b; + wire [27:0] rVStage_uid62_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_c; + wire [1:0] rVStage_uid69_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_b; + wire [29:0] rVStage_uid69_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_c; + wire [0:0] rVStage_uid76_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_b; + wire [30:0] rVStage_uid76_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_c; + wire [30:0] fracRnd_uid15_fxpToFPTest_merged_bit_select_in; + wire [23:0] fracRnd_uid15_fxpToFPTest_merged_bit_select_b; + wire [6:0] fracRnd_uid15_fxpToFPTest_merged_bit_select_c; + reg [23:0] redist0_fracRnd_uid15_fxpToFPTest_merged_bit_select_b_1_q; + reg [0:0] redist1_vCount_uid70_lzcShifterZ1_uid10_fxpToFPTest_q_1_q; + reg [0:0] redist2_vCount_uid63_lzcShifterZ1_uid10_fxpToFPTest_q_1_q; + reg [0:0] redist3_vCount_uid56_lzcShifterZ1_uid10_fxpToFPTest_q_2_q; + reg [0:0] redist3_vCount_uid56_lzcShifterZ1_uid10_fxpToFPTest_q_2_delay_0; + reg [0:0] redist4_vCount_uid49_lzcShifterZ1_uid10_fxpToFPTest_q_3_q; + reg [0:0] redist4_vCount_uid49_lzcShifterZ1_uid10_fxpToFPTest_q_3_delay_0; + reg [0:0] redist4_vCount_uid49_lzcShifterZ1_uid10_fxpToFPTest_q_3_delay_1; + reg [0:0] redist5_vCount_uid44_lzcShifterZ1_uid10_fxpToFPTest_q_4_q; + reg [0:0] redist5_vCount_uid44_lzcShifterZ1_uid10_fxpToFPTest_q_4_delay_0; + reg [0:0] redist5_vCount_uid44_lzcShifterZ1_uid10_fxpToFPTest_q_4_delay_1; + reg [9:0] redist6_expR_uid26_fxpToFPTest_b_1_q; + reg [22:0] redist7_fracR_uid25_fxpToFPTest_b_1_q; + reg [0:0] redist8_inIsZero_uid12_fxpToFPTest_q_2_q; + reg [31:0] redist9_y_uid9_fxpToFPTest_b_1_q; + reg [31:0] redist10_y_uid9_fxpToFPTest_b_2_q; + reg [0:0] redist11_signX_uid6_fxpToFPTest_b_7_q; + + + // signX_uid6_fxpToFPTest(BITSELECT,5)@0 + assign signX_uid6_fxpToFPTest_b = a[31:31]; + + // redist11_signX_uid6_fxpToFPTest_b_7(DELAY,106) + dspba_delay_ver #( .width(1), .depth(7), .reset_kind("SYNC"), .phase(0), .modulus(1) ) + redist11_signX_uid6_fxpToFPTest_b_7 ( .xin(signX_uid6_fxpToFPTest_b), .xout(redist11_signX_uid6_fxpToFPTest_b_7_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // expInf_uid28_fxpToFPTest(CONSTANT,27) + assign expInf_uid28_fxpToFPTest_q = 8'b11111111; + + // expZ_uid37_fxpToFPTest(CONSTANT,36) + assign expZ_uid37_fxpToFPTest_q = 8'b00000000; + + // rVStage_uid76_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select(BITSELECT,93)@5 + assign rVStage_uid76_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_b = vStagei_uid74_lzcShifterZ1_uid10_fxpToFPTest_q[31:31]; + assign rVStage_uid76_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_c = vStagei_uid74_lzcShifterZ1_uid10_fxpToFPTest_q[30:0]; + + // GND(CONSTANT,0) + assign GND_q = 1'b0; + + // cStage_uid80_lzcShifterZ1_uid10_fxpToFPTest(BITJOIN,79)@5 + assign cStage_uid80_lzcShifterZ1_uid10_fxpToFPTest_q = {rVStage_uid76_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_c, GND_q}; + + // rVStage_uid69_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select(BITSELECT,92)@4 + assign rVStage_uid69_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_b = vStagei_uid67_lzcShifterZ1_uid10_fxpToFPTest_q[31:30]; + assign rVStage_uid69_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_c = vStagei_uid67_lzcShifterZ1_uid10_fxpToFPTest_q[29:0]; + + // zs_uid68_lzcShifterZ1_uid10_fxpToFPTest(CONSTANT,67) + assign zs_uid68_lzcShifterZ1_uid10_fxpToFPTest_q = 2'b00; + + // cStage_uid73_lzcShifterZ1_uid10_fxpToFPTest(BITJOIN,72)@4 + assign cStage_uid73_lzcShifterZ1_uid10_fxpToFPTest_q = {rVStage_uid69_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_c, zs_uid68_lzcShifterZ1_uid10_fxpToFPTest_q}; + + // rVStage_uid62_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select(BITSELECT,91)@4 + assign rVStage_uid62_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_b = vStagei_uid60_lzcShifterZ1_uid10_fxpToFPTest_q[31:28]; + assign rVStage_uid62_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_c = vStagei_uid60_lzcShifterZ1_uid10_fxpToFPTest_q[27:0]; + + // zs_uid61_lzcShifterZ1_uid10_fxpToFPTest(CONSTANT,60) + assign zs_uid61_lzcShifterZ1_uid10_fxpToFPTest_q = 4'b0000; + + // cStage_uid66_lzcShifterZ1_uid10_fxpToFPTest(BITJOIN,65)@4 + assign cStage_uid66_lzcShifterZ1_uid10_fxpToFPTest_q = {rVStage_uid62_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_c, zs_uid61_lzcShifterZ1_uid10_fxpToFPTest_q}; + + // rVStage_uid55_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select(BITSELECT,90)@3 + assign rVStage_uid55_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_b = vStagei_uid53_lzcShifterZ1_uid10_fxpToFPTest_q[31:24]; + assign rVStage_uid55_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_c = vStagei_uid53_lzcShifterZ1_uid10_fxpToFPTest_q[23:0]; + + // cStage_uid59_lzcShifterZ1_uid10_fxpToFPTest(BITJOIN,58)@3 + assign cStage_uid59_lzcShifterZ1_uid10_fxpToFPTest_q = {rVStage_uid55_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_c, expZ_uid37_fxpToFPTest_q}; + + // rVStage_uid48_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select(BITSELECT,89)@2 + assign rVStage_uid48_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_b = vStagei_uid46_lzcShifterZ1_uid10_fxpToFPTest_q[31:16]; + assign rVStage_uid48_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_c = vStagei_uid46_lzcShifterZ1_uid10_fxpToFPTest_q[15:0]; + + // zs_uid47_lzcShifterZ1_uid10_fxpToFPTest(CONSTANT,46) + assign zs_uid47_lzcShifterZ1_uid10_fxpToFPTest_q = 16'b0000000000000000; + + // cStage_uid52_lzcShifterZ1_uid10_fxpToFPTest(BITJOIN,51)@2 + assign cStage_uid52_lzcShifterZ1_uid10_fxpToFPTest_q = {rVStage_uid48_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_c, zs_uid47_lzcShifterZ1_uid10_fxpToFPTest_q}; + + // zs_uid42_lzcShifterZ1_uid10_fxpToFPTest(CONSTANT,41) + assign zs_uid42_lzcShifterZ1_uid10_fxpToFPTest_q = 32'b00000000000000000000000000000000; + + // xXorSign_uid7_fxpToFPTest(LOGICAL,6)@0 + assign xXorSign_uid7_fxpToFPTest_b = {{31{signX_uid6_fxpToFPTest_b[0]}}, signX_uid6_fxpToFPTest_b}; + assign xXorSign_uid7_fxpToFPTest_q = a ^ xXorSign_uid7_fxpToFPTest_b; + + // yE_uid8_fxpToFPTest(ADD,7)@0 + assign yE_uid8_fxpToFPTest_a = {1'b0, xXorSign_uid7_fxpToFPTest_q}; + assign yE_uid8_fxpToFPTest_b = {32'b00000000000000000000000000000000, signX_uid6_fxpToFPTest_b}; + assign yE_uid8_fxpToFPTest_o = $unsigned(yE_uid8_fxpToFPTest_a) + $unsigned(yE_uid8_fxpToFPTest_b); + assign yE_uid8_fxpToFPTest_q = yE_uid8_fxpToFPTest_o[32:0]; + + // y_uid9_fxpToFPTest(BITSELECT,8)@0 + assign y_uid9_fxpToFPTest_in = yE_uid8_fxpToFPTest_q[31:0]; + assign y_uid9_fxpToFPTest_b = y_uid9_fxpToFPTest_in[31:0]; + + // redist9_y_uid9_fxpToFPTest_b_1(DELAY,104) + always @ (posedge clk) + begin + if (areset) + begin + redist9_y_uid9_fxpToFPTest_b_1_q <= '0; + end + else if (en == 1'b1) + begin + redist9_y_uid9_fxpToFPTest_b_1_q <= y_uid9_fxpToFPTest_b; + end + end + + // redist10_y_uid9_fxpToFPTest_b_2(DELAY,105) + always @ (posedge clk) + begin + if (areset) + begin + redist10_y_uid9_fxpToFPTest_b_2_q <= '0; + end + else if (en == 1'b1) + begin + redist10_y_uid9_fxpToFPTest_b_2_q <= redist9_y_uid9_fxpToFPTest_b_1_q; + end + end + + // vCount_uid44_lzcShifterZ1_uid10_fxpToFPTest(LOGICAL,43)@1 + 1 + assign vCount_uid44_lzcShifterZ1_uid10_fxpToFPTest_qi = redist9_y_uid9_fxpToFPTest_b_1_q == zs_uid42_lzcShifterZ1_uid10_fxpToFPTest_q ? 1'b1 : 1'b0; + dspba_delay_ver #( .width(1), .depth(1), .reset_kind("SYNC"), .phase(0), .modulus(1) ) + vCount_uid44_lzcShifterZ1_uid10_fxpToFPTest_delay ( .xin(vCount_uid44_lzcShifterZ1_uid10_fxpToFPTest_qi), .xout(vCount_uid44_lzcShifterZ1_uid10_fxpToFPTest_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // vStagei_uid46_lzcShifterZ1_uid10_fxpToFPTest(MUX,45)@2 + assign vStagei_uid46_lzcShifterZ1_uid10_fxpToFPTest_s = vCount_uid44_lzcShifterZ1_uid10_fxpToFPTest_q; + always @(vStagei_uid46_lzcShifterZ1_uid10_fxpToFPTest_s or en or redist10_y_uid9_fxpToFPTest_b_2_q or zs_uid42_lzcShifterZ1_uid10_fxpToFPTest_q) + begin + unique case (vStagei_uid46_lzcShifterZ1_uid10_fxpToFPTest_s) + 1'b0 : vStagei_uid46_lzcShifterZ1_uid10_fxpToFPTest_q = redist10_y_uid9_fxpToFPTest_b_2_q; + 1'b1 : vStagei_uid46_lzcShifterZ1_uid10_fxpToFPTest_q = zs_uid42_lzcShifterZ1_uid10_fxpToFPTest_q; + default : vStagei_uid46_lzcShifterZ1_uid10_fxpToFPTest_q = 32'b0; + endcase + end + + // vCount_uid49_lzcShifterZ1_uid10_fxpToFPTest(LOGICAL,48)@2 + assign vCount_uid49_lzcShifterZ1_uid10_fxpToFPTest_q = rVStage_uid48_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_b == zs_uid47_lzcShifterZ1_uid10_fxpToFPTest_q ? 1'b1 : 1'b0; + + // vStagei_uid53_lzcShifterZ1_uid10_fxpToFPTest(MUX,52)@2 + 1 + assign vStagei_uid53_lzcShifterZ1_uid10_fxpToFPTest_s = vCount_uid49_lzcShifterZ1_uid10_fxpToFPTest_q; + always @ (posedge clk) + begin + if (areset) + begin + vStagei_uid53_lzcShifterZ1_uid10_fxpToFPTest_q <= 32'b0; + end + else if (en == 1'b1) + begin + unique case (vStagei_uid53_lzcShifterZ1_uid10_fxpToFPTest_s) + 1'b0 : vStagei_uid53_lzcShifterZ1_uid10_fxpToFPTest_q <= vStagei_uid46_lzcShifterZ1_uid10_fxpToFPTest_q; + 1'b1 : vStagei_uid53_lzcShifterZ1_uid10_fxpToFPTest_q <= cStage_uid52_lzcShifterZ1_uid10_fxpToFPTest_q; + default : vStagei_uid53_lzcShifterZ1_uid10_fxpToFPTest_q <= 32'b0; + endcase + end + end + + // vCount_uid56_lzcShifterZ1_uid10_fxpToFPTest(LOGICAL,55)@3 + assign vCount_uid56_lzcShifterZ1_uid10_fxpToFPTest_q = rVStage_uid55_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_b == expZ_uid37_fxpToFPTest_q ? 1'b1 : 1'b0; + + // vStagei_uid60_lzcShifterZ1_uid10_fxpToFPTest(MUX,59)@3 + 1 + assign vStagei_uid60_lzcShifterZ1_uid10_fxpToFPTest_s = vCount_uid56_lzcShifterZ1_uid10_fxpToFPTest_q; + always @ (posedge clk) + begin + if (areset) + begin + vStagei_uid60_lzcShifterZ1_uid10_fxpToFPTest_q <= 32'b0; + end + else if (en == 1'b1) + begin + unique case (vStagei_uid60_lzcShifterZ1_uid10_fxpToFPTest_s) + 1'b0 : vStagei_uid60_lzcShifterZ1_uid10_fxpToFPTest_q <= vStagei_uid53_lzcShifterZ1_uid10_fxpToFPTest_q; + 1'b1 : vStagei_uid60_lzcShifterZ1_uid10_fxpToFPTest_q <= cStage_uid59_lzcShifterZ1_uid10_fxpToFPTest_q; + default : vStagei_uid60_lzcShifterZ1_uid10_fxpToFPTest_q <= 32'b0; + endcase + end + end + + // vCount_uid63_lzcShifterZ1_uid10_fxpToFPTest(LOGICAL,62)@4 + assign vCount_uid63_lzcShifterZ1_uid10_fxpToFPTest_q = rVStage_uid62_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_b == zs_uid61_lzcShifterZ1_uid10_fxpToFPTest_q ? 1'b1 : 1'b0; + + // vStagei_uid67_lzcShifterZ1_uid10_fxpToFPTest(MUX,66)@4 + assign vStagei_uid67_lzcShifterZ1_uid10_fxpToFPTest_s = vCount_uid63_lzcShifterZ1_uid10_fxpToFPTest_q; + always @(vStagei_uid67_lzcShifterZ1_uid10_fxpToFPTest_s or en or vStagei_uid60_lzcShifterZ1_uid10_fxpToFPTest_q or cStage_uid66_lzcShifterZ1_uid10_fxpToFPTest_q) + begin + unique case (vStagei_uid67_lzcShifterZ1_uid10_fxpToFPTest_s) + 1'b0 : vStagei_uid67_lzcShifterZ1_uid10_fxpToFPTest_q = vStagei_uid60_lzcShifterZ1_uid10_fxpToFPTest_q; + 1'b1 : vStagei_uid67_lzcShifterZ1_uid10_fxpToFPTest_q = cStage_uid66_lzcShifterZ1_uid10_fxpToFPTest_q; + default : vStagei_uid67_lzcShifterZ1_uid10_fxpToFPTest_q = 32'b0; + endcase + end + + // vCount_uid70_lzcShifterZ1_uid10_fxpToFPTest(LOGICAL,69)@4 + assign vCount_uid70_lzcShifterZ1_uid10_fxpToFPTest_q = rVStage_uid69_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_b == zs_uid68_lzcShifterZ1_uid10_fxpToFPTest_q ? 1'b1 : 1'b0; + + // vStagei_uid74_lzcShifterZ1_uid10_fxpToFPTest(MUX,73)@4 + 1 + assign vStagei_uid74_lzcShifterZ1_uid10_fxpToFPTest_s = vCount_uid70_lzcShifterZ1_uid10_fxpToFPTest_q; + always @ (posedge clk) + begin + if (areset) + begin + vStagei_uid74_lzcShifterZ1_uid10_fxpToFPTest_q <= 32'b0; + end + else if (en == 1'b1) + begin + unique case (vStagei_uid74_lzcShifterZ1_uid10_fxpToFPTest_s) + 1'b0 : vStagei_uid74_lzcShifterZ1_uid10_fxpToFPTest_q <= vStagei_uid67_lzcShifterZ1_uid10_fxpToFPTest_q; + 1'b1 : vStagei_uid74_lzcShifterZ1_uid10_fxpToFPTest_q <= cStage_uid73_lzcShifterZ1_uid10_fxpToFPTest_q; + default : vStagei_uid74_lzcShifterZ1_uid10_fxpToFPTest_q <= 32'b0; + endcase + end + end + + // vCount_uid77_lzcShifterZ1_uid10_fxpToFPTest(LOGICAL,76)@5 + assign vCount_uid77_lzcShifterZ1_uid10_fxpToFPTest_q = rVStage_uid76_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_b == GND_q ? 1'b1 : 1'b0; + + // vStagei_uid81_lzcShifterZ1_uid10_fxpToFPTest(MUX,80)@5 + assign vStagei_uid81_lzcShifterZ1_uid10_fxpToFPTest_s = vCount_uid77_lzcShifterZ1_uid10_fxpToFPTest_q; + always @(vStagei_uid81_lzcShifterZ1_uid10_fxpToFPTest_s or en or vStagei_uid74_lzcShifterZ1_uid10_fxpToFPTest_q or cStage_uid80_lzcShifterZ1_uid10_fxpToFPTest_q) + begin + unique case (vStagei_uid81_lzcShifterZ1_uid10_fxpToFPTest_s) + 1'b0 : vStagei_uid81_lzcShifterZ1_uid10_fxpToFPTest_q = vStagei_uid74_lzcShifterZ1_uid10_fxpToFPTest_q; + 1'b1 : vStagei_uid81_lzcShifterZ1_uid10_fxpToFPTest_q = cStage_uid80_lzcShifterZ1_uid10_fxpToFPTest_q; + default : vStagei_uid81_lzcShifterZ1_uid10_fxpToFPTest_q = 32'b0; + endcase + end + + // fracRnd_uid15_fxpToFPTest_merged_bit_select(BITSELECT,94)@5 + assign fracRnd_uid15_fxpToFPTest_merged_bit_select_in = vStagei_uid81_lzcShifterZ1_uid10_fxpToFPTest_q[30:0]; + assign fracRnd_uid15_fxpToFPTest_merged_bit_select_b = fracRnd_uid15_fxpToFPTest_merged_bit_select_in[30:7]; + assign fracRnd_uid15_fxpToFPTest_merged_bit_select_c = fracRnd_uid15_fxpToFPTest_merged_bit_select_in[6:0]; + + // sticky_uid20_fxpToFPTest(LOGICAL,19)@5 + 1 + assign sticky_uid20_fxpToFPTest_qi = fracRnd_uid15_fxpToFPTest_merged_bit_select_c != 7'b0000000 ? 1'b1 : 1'b0; + dspba_delay_ver #( .width(1), .depth(1), .reset_kind("SYNC"), .phase(0), .modulus(1) ) + sticky_uid20_fxpToFPTest_delay ( .xin(sticky_uid20_fxpToFPTest_qi), .xout(sticky_uid20_fxpToFPTest_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // nr_uid21_fxpToFPTest(LOGICAL,20)@6 + assign nr_uid21_fxpToFPTest_q = ~ (l_uid17_fxpToFPTest_merged_bit_select_c); + + // l_uid17_fxpToFPTest_merged_bit_select(BITSELECT,88)@6 + assign l_uid17_fxpToFPTest_merged_bit_select_in = expFracRnd_uid16_fxpToFPTest_q[1:0]; + assign l_uid17_fxpToFPTest_merged_bit_select_b = l_uid17_fxpToFPTest_merged_bit_select_in[1:1]; + assign l_uid17_fxpToFPTest_merged_bit_select_c = l_uid17_fxpToFPTest_merged_bit_select_in[0:0]; + + // rnd_uid22_fxpToFPTest(LOGICAL,21)@6 + assign rnd_uid22_fxpToFPTest_q = l_uid17_fxpToFPTest_merged_bit_select_b | nr_uid21_fxpToFPTest_q | sticky_uid20_fxpToFPTest_q; + + // maxCount_uid11_fxpToFPTest(CONSTANT,10) + assign maxCount_uid11_fxpToFPTest_q = 6'b100000; + + // redist5_vCount_uid44_lzcShifterZ1_uid10_fxpToFPTest_q_4(DELAY,100) + always @ (posedge clk) + begin + if (areset) + begin + redist5_vCount_uid44_lzcShifterZ1_uid10_fxpToFPTest_q_4_delay_0 <= '0; + redist5_vCount_uid44_lzcShifterZ1_uid10_fxpToFPTest_q_4_delay_1 <= '0; + redist5_vCount_uid44_lzcShifterZ1_uid10_fxpToFPTest_q_4_q <= '0; + end + else if (en == 1'b1) + begin + redist5_vCount_uid44_lzcShifterZ1_uid10_fxpToFPTest_q_4_delay_0 <= vCount_uid44_lzcShifterZ1_uid10_fxpToFPTest_q; + redist5_vCount_uid44_lzcShifterZ1_uid10_fxpToFPTest_q_4_delay_1 <= redist5_vCount_uid44_lzcShifterZ1_uid10_fxpToFPTest_q_4_delay_0; + redist5_vCount_uid44_lzcShifterZ1_uid10_fxpToFPTest_q_4_q <= redist5_vCount_uid44_lzcShifterZ1_uid10_fxpToFPTest_q_4_delay_1; + end + end + + // redist4_vCount_uid49_lzcShifterZ1_uid10_fxpToFPTest_q_3(DELAY,99) + always @ (posedge clk) + begin + if (areset) + begin + redist4_vCount_uid49_lzcShifterZ1_uid10_fxpToFPTest_q_3_delay_0 <= '0; + redist4_vCount_uid49_lzcShifterZ1_uid10_fxpToFPTest_q_3_delay_1 <= '0; + redist4_vCount_uid49_lzcShifterZ1_uid10_fxpToFPTest_q_3_q <= '0; + end + else if (en == 1'b1) + begin + redist4_vCount_uid49_lzcShifterZ1_uid10_fxpToFPTest_q_3_delay_0 <= vCount_uid49_lzcShifterZ1_uid10_fxpToFPTest_q; + redist4_vCount_uid49_lzcShifterZ1_uid10_fxpToFPTest_q_3_delay_1 <= redist4_vCount_uid49_lzcShifterZ1_uid10_fxpToFPTest_q_3_delay_0; + redist4_vCount_uid49_lzcShifterZ1_uid10_fxpToFPTest_q_3_q <= redist4_vCount_uid49_lzcShifterZ1_uid10_fxpToFPTest_q_3_delay_1; + end + end + + // redist3_vCount_uid56_lzcShifterZ1_uid10_fxpToFPTest_q_2(DELAY,98) + always @ (posedge clk) + begin + if (areset) + begin + redist3_vCount_uid56_lzcShifterZ1_uid10_fxpToFPTest_q_2_delay_0 <= '0; + redist3_vCount_uid56_lzcShifterZ1_uid10_fxpToFPTest_q_2_q <= '0; + end + else if (en == 1'b1) + begin + redist3_vCount_uid56_lzcShifterZ1_uid10_fxpToFPTest_q_2_delay_0 <= vCount_uid56_lzcShifterZ1_uid10_fxpToFPTest_q; + redist3_vCount_uid56_lzcShifterZ1_uid10_fxpToFPTest_q_2_q <= redist3_vCount_uid56_lzcShifterZ1_uid10_fxpToFPTest_q_2_delay_0; + end + end + + // redist2_vCount_uid63_lzcShifterZ1_uid10_fxpToFPTest_q_1(DELAY,97) + always @ (posedge clk) + begin + if (areset) + begin + redist2_vCount_uid63_lzcShifterZ1_uid10_fxpToFPTest_q_1_q <= '0; + end + else if (en == 1'b1) + begin + redist2_vCount_uid63_lzcShifterZ1_uid10_fxpToFPTest_q_1_q <= vCount_uid63_lzcShifterZ1_uid10_fxpToFPTest_q; + end + end + + // redist1_vCount_uid70_lzcShifterZ1_uid10_fxpToFPTest_q_1(DELAY,96) + always @ (posedge clk) + begin + if (areset) + begin + redist1_vCount_uid70_lzcShifterZ1_uid10_fxpToFPTest_q_1_q <= '0; + end + else if (en == 1'b1) + begin + redist1_vCount_uid70_lzcShifterZ1_uid10_fxpToFPTest_q_1_q <= vCount_uid70_lzcShifterZ1_uid10_fxpToFPTest_q; + end + end + + // vCount_uid82_lzcShifterZ1_uid10_fxpToFPTest(BITJOIN,81)@5 + assign vCount_uid82_lzcShifterZ1_uid10_fxpToFPTest_q = {redist5_vCount_uid44_lzcShifterZ1_uid10_fxpToFPTest_q_4_q, redist4_vCount_uid49_lzcShifterZ1_uid10_fxpToFPTest_q_3_q, redist3_vCount_uid56_lzcShifterZ1_uid10_fxpToFPTest_q_2_q, redist2_vCount_uid63_lzcShifterZ1_uid10_fxpToFPTest_q_1_q, redist1_vCount_uid70_lzcShifterZ1_uid10_fxpToFPTest_q_1_q, vCount_uid77_lzcShifterZ1_uid10_fxpToFPTest_q}; + + // vCountBig_uid84_lzcShifterZ1_uid10_fxpToFPTest(COMPARE,83)@5 + assign vCountBig_uid84_lzcShifterZ1_uid10_fxpToFPTest_a = {2'b00, maxCount_uid11_fxpToFPTest_q}; + assign vCountBig_uid84_lzcShifterZ1_uid10_fxpToFPTest_b = {2'b00, vCount_uid82_lzcShifterZ1_uid10_fxpToFPTest_q}; + assign vCountBig_uid84_lzcShifterZ1_uid10_fxpToFPTest_o = $unsigned(vCountBig_uid84_lzcShifterZ1_uid10_fxpToFPTest_a) - $unsigned(vCountBig_uid84_lzcShifterZ1_uid10_fxpToFPTest_b); + assign vCountBig_uid84_lzcShifterZ1_uid10_fxpToFPTest_c[0] = vCountBig_uid84_lzcShifterZ1_uid10_fxpToFPTest_o[7]; + + // vCountFinal_uid86_lzcShifterZ1_uid10_fxpToFPTest(MUX,85)@5 + assign vCountFinal_uid86_lzcShifterZ1_uid10_fxpToFPTest_s = vCountBig_uid84_lzcShifterZ1_uid10_fxpToFPTest_c; + always @(vCountFinal_uid86_lzcShifterZ1_uid10_fxpToFPTest_s or en or vCount_uid82_lzcShifterZ1_uid10_fxpToFPTest_q or maxCount_uid11_fxpToFPTest_q) + begin + unique case (vCountFinal_uid86_lzcShifterZ1_uid10_fxpToFPTest_s) + 1'b0 : vCountFinal_uid86_lzcShifterZ1_uid10_fxpToFPTest_q = vCount_uid82_lzcShifterZ1_uid10_fxpToFPTest_q; + 1'b1 : vCountFinal_uid86_lzcShifterZ1_uid10_fxpToFPTest_q = maxCount_uid11_fxpToFPTest_q; + default : vCountFinal_uid86_lzcShifterZ1_uid10_fxpToFPTest_q = 6'b0; + endcase + end + + // msbIn_uid13_fxpToFPTest(CONSTANT,12) + assign msbIn_uid13_fxpToFPTest_q = 8'b10011110; + + // expPreRnd_uid14_fxpToFPTest(SUB,13)@5 + 1 + assign expPreRnd_uid14_fxpToFPTest_a = {1'b0, msbIn_uid13_fxpToFPTest_q}; + assign expPreRnd_uid14_fxpToFPTest_b = {3'b000, vCountFinal_uid86_lzcShifterZ1_uid10_fxpToFPTest_q}; + always @ (posedge clk) + begin + if (areset) + begin + expPreRnd_uid14_fxpToFPTest_o <= 9'b0; + end + else if (en == 1'b1) + begin + expPreRnd_uid14_fxpToFPTest_o <= $unsigned(expPreRnd_uid14_fxpToFPTest_a) - $unsigned(expPreRnd_uid14_fxpToFPTest_b); + end + end + assign expPreRnd_uid14_fxpToFPTest_q = expPreRnd_uid14_fxpToFPTest_o[8:0]; + + // redist0_fracRnd_uid15_fxpToFPTest_merged_bit_select_b_1(DELAY,95) + always @ (posedge clk) + begin + if (areset) + begin + redist0_fracRnd_uid15_fxpToFPTest_merged_bit_select_b_1_q <= '0; + end + else if (en == 1'b1) + begin + redist0_fracRnd_uid15_fxpToFPTest_merged_bit_select_b_1_q <= fracRnd_uid15_fxpToFPTest_merged_bit_select_b; + end + end + + // expFracRnd_uid16_fxpToFPTest(BITJOIN,15)@6 + assign expFracRnd_uid16_fxpToFPTest_q = {expPreRnd_uid14_fxpToFPTest_q, redist0_fracRnd_uid15_fxpToFPTest_merged_bit_select_b_1_q}; + + // expFracR_uid24_fxpToFPTest(ADD,23)@6 + assign expFracR_uid24_fxpToFPTest_a = {{2{expFracRnd_uid16_fxpToFPTest_q[32]}}, expFracRnd_uid16_fxpToFPTest_q}; + assign expFracR_uid24_fxpToFPTest_b = {34'b0000000000000000000000000000000000, rnd_uid22_fxpToFPTest_q}; + assign expFracR_uid24_fxpToFPTest_o = $signed(expFracR_uid24_fxpToFPTest_a) + $signed(expFracR_uid24_fxpToFPTest_b); + assign expFracR_uid24_fxpToFPTest_q = expFracR_uid24_fxpToFPTest_o[33:0]; + + // expR_uid26_fxpToFPTest(BITSELECT,25)@6 + assign expR_uid26_fxpToFPTest_b = expFracR_uid24_fxpToFPTest_q[33:24]; + + // redist6_expR_uid26_fxpToFPTest_b_1(DELAY,101) + always @ (posedge clk) + begin + if (areset) + begin + redist6_expR_uid26_fxpToFPTest_b_1_q <= '0; + end + else if (en == 1'b1) + begin + redist6_expR_uid26_fxpToFPTest_b_1_q <= expR_uid26_fxpToFPTest_b; + end + end + + // expR_uid38_fxpToFPTest(BITSELECT,37)@7 + assign expR_uid38_fxpToFPTest_in = redist6_expR_uid26_fxpToFPTest_b_1_q[7:0]; + assign expR_uid38_fxpToFPTest_b = expR_uid38_fxpToFPTest_in[7:0]; + + // ovf_uid29_fxpToFPTest(COMPARE,28)@7 + assign ovf_uid29_fxpToFPTest_a = {{2{redist6_expR_uid26_fxpToFPTest_b_1_q[9]}}, redist6_expR_uid26_fxpToFPTest_b_1_q}; + assign ovf_uid29_fxpToFPTest_b = {4'b0000, expInf_uid28_fxpToFPTest_q}; + assign ovf_uid29_fxpToFPTest_o = $signed(ovf_uid29_fxpToFPTest_a) - $signed(ovf_uid29_fxpToFPTest_b); + assign ovf_uid29_fxpToFPTest_n[0] = ~ (ovf_uid29_fxpToFPTest_o[11]); + + // inIsZero_uid12_fxpToFPTest(LOGICAL,11)@5 + 1 + assign inIsZero_uid12_fxpToFPTest_qi = vCountFinal_uid86_lzcShifterZ1_uid10_fxpToFPTest_q == maxCount_uid11_fxpToFPTest_q ? 1'b1 : 1'b0; + dspba_delay_ver #( .width(1), .depth(1), .reset_kind("SYNC"), .phase(0), .modulus(1) ) + inIsZero_uid12_fxpToFPTest_delay ( .xin(inIsZero_uid12_fxpToFPTest_qi), .xout(inIsZero_uid12_fxpToFPTest_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // redist8_inIsZero_uid12_fxpToFPTest_q_2(DELAY,103) + always @ (posedge clk) + begin + if (areset) + begin + redist8_inIsZero_uid12_fxpToFPTest_q_2_q <= '0; + end + else if (en == 1'b1) + begin + redist8_inIsZero_uid12_fxpToFPTest_q_2_q <= inIsZero_uid12_fxpToFPTest_q; + end + end + + // udf_uid27_fxpToFPTest(COMPARE,26)@7 + assign udf_uid27_fxpToFPTest_a = {11'b00000000000, GND_q}; + assign udf_uid27_fxpToFPTest_b = {{2{redist6_expR_uid26_fxpToFPTest_b_1_q[9]}}, redist6_expR_uid26_fxpToFPTest_b_1_q}; + assign udf_uid27_fxpToFPTest_o = $signed(udf_uid27_fxpToFPTest_a) - $signed(udf_uid27_fxpToFPTest_b); + assign udf_uid27_fxpToFPTest_n[0] = ~ (udf_uid27_fxpToFPTest_o[11]); + + // udfOrInZero_uid33_fxpToFPTest(LOGICAL,32)@7 + assign udfOrInZero_uid33_fxpToFPTest_q = udf_uid27_fxpToFPTest_n | redist8_inIsZero_uid12_fxpToFPTest_q_2_q; + + // excSelector_uid34_fxpToFPTest(BITJOIN,33)@7 + assign excSelector_uid34_fxpToFPTest_q = {ovf_uid29_fxpToFPTest_n, udfOrInZero_uid33_fxpToFPTest_q}; + + // expRPostExc_uid39_fxpToFPTest(MUX,38)@7 + assign expRPostExc_uid39_fxpToFPTest_s = excSelector_uid34_fxpToFPTest_q; + always @(expRPostExc_uid39_fxpToFPTest_s or en or expR_uid38_fxpToFPTest_b or expZ_uid37_fxpToFPTest_q or expInf_uid28_fxpToFPTest_q) + begin + unique case (expRPostExc_uid39_fxpToFPTest_s) + 2'b00 : expRPostExc_uid39_fxpToFPTest_q = expR_uid38_fxpToFPTest_b; + 2'b01 : expRPostExc_uid39_fxpToFPTest_q = expZ_uid37_fxpToFPTest_q; + 2'b10 : expRPostExc_uid39_fxpToFPTest_q = expInf_uid28_fxpToFPTest_q; + 2'b11 : expRPostExc_uid39_fxpToFPTest_q = expInf_uid28_fxpToFPTest_q; + default : expRPostExc_uid39_fxpToFPTest_q = 8'b0; + endcase + end + + // fracZ_uid31_fxpToFPTest(CONSTANT,30) + assign fracZ_uid31_fxpToFPTest_q = 23'b00000000000000000000000; + + // fracR_uid25_fxpToFPTest(BITSELECT,24)@6 + assign fracR_uid25_fxpToFPTest_in = expFracR_uid24_fxpToFPTest_q[23:0]; + assign fracR_uid25_fxpToFPTest_b = fracR_uid25_fxpToFPTest_in[23:1]; + + // redist7_fracR_uid25_fxpToFPTest_b_1(DELAY,102) + always @ (posedge clk) + begin + if (areset) + begin + redist7_fracR_uid25_fxpToFPTest_b_1_q <= '0; + end + else if (en == 1'b1) + begin + redist7_fracR_uid25_fxpToFPTest_b_1_q <= fracR_uid25_fxpToFPTest_b; + end + end + + // excSelector_uid30_fxpToFPTest(LOGICAL,29)@7 + assign excSelector_uid30_fxpToFPTest_q = redist8_inIsZero_uid12_fxpToFPTest_q_2_q | ovf_uid29_fxpToFPTest_n | udf_uid27_fxpToFPTest_n; + + // fracRPostExc_uid32_fxpToFPTest(MUX,31)@7 + assign fracRPostExc_uid32_fxpToFPTest_s = excSelector_uid30_fxpToFPTest_q; + always @(fracRPostExc_uid32_fxpToFPTest_s or en or redist7_fracR_uid25_fxpToFPTest_b_1_q or fracZ_uid31_fxpToFPTest_q) + begin + unique case (fracRPostExc_uid32_fxpToFPTest_s) + 1'b0 : fracRPostExc_uid32_fxpToFPTest_q = redist7_fracR_uid25_fxpToFPTest_b_1_q; + 1'b1 : fracRPostExc_uid32_fxpToFPTest_q = fracZ_uid31_fxpToFPTest_q; + default : fracRPostExc_uid32_fxpToFPTest_q = 23'b0; + endcase + end + + // outRes_uid40_fxpToFPTest(BITJOIN,39)@7 + assign outRes_uid40_fxpToFPTest_q = {redist11_signX_uid6_fxpToFPTest_b_7_q, expRPostExc_uid39_fxpToFPTest_q, fracRPostExc_uid32_fxpToFPTest_q}; + + // xOut(GPOUT,4)@7 + assign q = outRes_uid40_fxpToFPTest_q; + +endmodule diff --git a/hw/rtl/fp_cores/altera/stratix10/acl_utof.sv b/hw/rtl/fp_cores/altera/stratix10/acl_utof.sv new file mode 100644 index 00000000..f8b4897a --- /dev/null +++ b/hw/rtl/fp_cores/altera/stratix10/acl_utof.sv @@ -0,0 +1,607 @@ +// ------------------------------------------------------------------------- +// High Level Design Compiler for Intel(R) FPGAs Version 18.1 (Release Build #277) +// Quartus Prime development tool and MATLAB/Simulink Interface +// +// Legal Notice: Copyright 2019 Intel Corporation. All rights reserved. +// Your use of Intel Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly +// subject to the terms and conditions of the Intel FPGA Software License +// Agreement, Intel MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for +// the sole purpose of programming logic devices manufactured by Intel +// and sold by Intel or its authorized distributors. Please refer to the +// applicable agreement for further details. +// --------------------------------------------------------------------------- + +// SystemVerilog created from acl_utof +// SystemVerilog created on Sun Dec 27 09:48:58 2020 + + +(* altera_attribute = "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410; -name MESSAGE_DISABLE 113007; -name MESSAGE_DISABLE 10958" *) +module acl_utof ( + input wire [31:0] a, + input wire [0:0] en, + output wire [31:0] q, + input wire clk, + input wire areset + ); + + wire [0:0] GND_q; + wire [5:0] maxCount_uid7_fxpToFPTest_q; + wire [0:0] inIsZero_uid8_fxpToFPTest_qi; + reg [0:0] inIsZero_uid8_fxpToFPTest_q; + wire [7:0] msbIn_uid9_fxpToFPTest_q; + wire [8:0] expPreRnd_uid10_fxpToFPTest_a; + wire [8:0] expPreRnd_uid10_fxpToFPTest_b; + logic [8:0] expPreRnd_uid10_fxpToFPTest_o; + wire [8:0] expPreRnd_uid10_fxpToFPTest_q; + wire [32:0] expFracRnd_uid12_fxpToFPTest_q; + wire [0:0] sticky_uid16_fxpToFPTest_q; + wire [0:0] nr_uid17_fxpToFPTest_q; + wire [0:0] rnd_uid18_fxpToFPTest_qi; + reg [0:0] rnd_uid18_fxpToFPTest_q; + wire [34:0] expFracR_uid20_fxpToFPTest_a; + wire [34:0] expFracR_uid20_fxpToFPTest_b; + logic [34:0] expFracR_uid20_fxpToFPTest_o; + wire [33:0] expFracR_uid20_fxpToFPTest_q; + wire [23:0] fracR_uid21_fxpToFPTest_in; + wire [22:0] fracR_uid21_fxpToFPTest_b; + wire [9:0] expR_uid22_fxpToFPTest_b; + wire [11:0] udf_uid23_fxpToFPTest_a; + wire [11:0] udf_uid23_fxpToFPTest_b; + logic [11:0] udf_uid23_fxpToFPTest_o; + wire [0:0] udf_uid23_fxpToFPTest_n; + wire [7:0] expInf_uid24_fxpToFPTest_q; + wire [11:0] ovf_uid25_fxpToFPTest_a; + wire [11:0] ovf_uid25_fxpToFPTest_b; + logic [11:0] ovf_uid25_fxpToFPTest_o; + wire [0:0] ovf_uid25_fxpToFPTest_n; + wire [0:0] excSelector_uid26_fxpToFPTest_q; + wire [22:0] fracZ_uid27_fxpToFPTest_q; + wire [0:0] fracRPostExc_uid28_fxpToFPTest_s; + reg [22:0] fracRPostExc_uid28_fxpToFPTest_q; + wire [0:0] udfOrInZero_uid29_fxpToFPTest_q; + wire [1:0] excSelector_uid30_fxpToFPTest_q; + wire [7:0] expZ_uid33_fxpToFPTest_q; + wire [7:0] expR_uid34_fxpToFPTest_in; + wire [7:0] expR_uid34_fxpToFPTest_b; + wire [1:0] expRPostExc_uid35_fxpToFPTest_s; + reg [7:0] expRPostExc_uid35_fxpToFPTest_q; + wire [31:0] outRes_uid36_fxpToFPTest_q; + wire [31:0] zs_uid38_lzcShifterZ1_uid6_fxpToFPTest_q; + wire [0:0] vCount_uid40_lzcShifterZ1_uid6_fxpToFPTest_q; + wire [0:0] vStagei_uid42_lzcShifterZ1_uid6_fxpToFPTest_s; + reg [31:0] vStagei_uid42_lzcShifterZ1_uid6_fxpToFPTest_q; + wire [15:0] zs_uid43_lzcShifterZ1_uid6_fxpToFPTest_q; + wire [0:0] vCount_uid45_lzcShifterZ1_uid6_fxpToFPTest_q; + wire [31:0] cStage_uid48_lzcShifterZ1_uid6_fxpToFPTest_q; + wire [0:0] vStagei_uid49_lzcShifterZ1_uid6_fxpToFPTest_s; + reg [31:0] vStagei_uid49_lzcShifterZ1_uid6_fxpToFPTest_q; + wire [0:0] vCount_uid52_lzcShifterZ1_uid6_fxpToFPTest_q; + wire [31:0] cStage_uid55_lzcShifterZ1_uid6_fxpToFPTest_q; + wire [0:0] vStagei_uid56_lzcShifterZ1_uid6_fxpToFPTest_s; + reg [31:0] vStagei_uid56_lzcShifterZ1_uid6_fxpToFPTest_q; + wire [3:0] zs_uid57_lzcShifterZ1_uid6_fxpToFPTest_q; + wire [0:0] vCount_uid59_lzcShifterZ1_uid6_fxpToFPTest_q; + wire [31:0] cStage_uid62_lzcShifterZ1_uid6_fxpToFPTest_q; + wire [0:0] vStagei_uid63_lzcShifterZ1_uid6_fxpToFPTest_s; + reg [31:0] vStagei_uid63_lzcShifterZ1_uid6_fxpToFPTest_q; + wire [1:0] zs_uid64_lzcShifterZ1_uid6_fxpToFPTest_q; + wire [0:0] vCount_uid66_lzcShifterZ1_uid6_fxpToFPTest_q; + wire [31:0] cStage_uid69_lzcShifterZ1_uid6_fxpToFPTest_q; + wire [0:0] vStagei_uid70_lzcShifterZ1_uid6_fxpToFPTest_s; + reg [31:0] vStagei_uid70_lzcShifterZ1_uid6_fxpToFPTest_q; + wire [0:0] vCount_uid73_lzcShifterZ1_uid6_fxpToFPTest_q; + wire [31:0] cStage_uid76_lzcShifterZ1_uid6_fxpToFPTest_q; + wire [0:0] vStagei_uid77_lzcShifterZ1_uid6_fxpToFPTest_s; + reg [31:0] vStagei_uid77_lzcShifterZ1_uid6_fxpToFPTest_q; + wire [5:0] vCount_uid78_lzcShifterZ1_uid6_fxpToFPTest_q; + wire [7:0] vCountBig_uid80_lzcShifterZ1_uid6_fxpToFPTest_a; + wire [7:0] vCountBig_uid80_lzcShifterZ1_uid6_fxpToFPTest_b; + logic [7:0] vCountBig_uid80_lzcShifterZ1_uid6_fxpToFPTest_o; + wire [0:0] vCountBig_uid80_lzcShifterZ1_uid6_fxpToFPTest_c; + wire [0:0] vCountFinal_uid82_lzcShifterZ1_uid6_fxpToFPTest_s; + reg [5:0] vCountFinal_uid82_lzcShifterZ1_uid6_fxpToFPTest_q; + wire [1:0] l_uid13_fxpToFPTest_merged_bit_select_in; + wire [0:0] l_uid13_fxpToFPTest_merged_bit_select_b; + wire [0:0] l_uid13_fxpToFPTest_merged_bit_select_c; + wire [15:0] rVStage_uid44_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_b; + wire [15:0] rVStage_uid44_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_c; + wire [7:0] rVStage_uid51_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_b; + wire [23:0] rVStage_uid51_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_c; + wire [3:0] rVStage_uid58_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_b; + wire [27:0] rVStage_uid58_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_c; + wire [1:0] rVStage_uid65_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_b; + wire [29:0] rVStage_uid65_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_c; + wire [0:0] rVStage_uid72_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_b; + wire [30:0] rVStage_uid72_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_c; + wire [30:0] fracRnd_uid11_fxpToFPTest_merged_bit_select_in; + wire [23:0] fracRnd_uid11_fxpToFPTest_merged_bit_select_b; + wire [6:0] fracRnd_uid11_fxpToFPTest_merged_bit_select_c; + reg [23:0] redist0_fracRnd_uid11_fxpToFPTest_merged_bit_select_b_1_q; + reg [6:0] redist1_fracRnd_uid11_fxpToFPTest_merged_bit_select_c_1_q; + reg [5:0] redist2_vCount_uid78_lzcShifterZ1_uid6_fxpToFPTest_q_1_q; + reg [0:0] redist3_vCount_uid59_lzcShifterZ1_uid6_fxpToFPTest_q_1_q; + reg [0:0] redist4_vCount_uid52_lzcShifterZ1_uid6_fxpToFPTest_q_2_q; + reg [0:0] redist4_vCount_uid52_lzcShifterZ1_uid6_fxpToFPTest_q_2_delay_0; + reg [0:0] redist5_vCount_uid45_lzcShifterZ1_uid6_fxpToFPTest_q_3_q; + reg [0:0] redist5_vCount_uid45_lzcShifterZ1_uid6_fxpToFPTest_q_3_delay_0; + reg [0:0] redist5_vCount_uid45_lzcShifterZ1_uid6_fxpToFPTest_q_3_delay_1; + reg [0:0] redist6_vCount_uid40_lzcShifterZ1_uid6_fxpToFPTest_q_4_q; + reg [0:0] redist6_vCount_uid40_lzcShifterZ1_uid6_fxpToFPTest_q_4_delay_0; + reg [0:0] redist6_vCount_uid40_lzcShifterZ1_uid6_fxpToFPTest_q_4_delay_1; + reg [0:0] redist6_vCount_uid40_lzcShifterZ1_uid6_fxpToFPTest_q_4_delay_2; + reg [9:0] redist7_expR_uid22_fxpToFPTest_b_1_q; + reg [22:0] redist8_fracR_uid21_fxpToFPTest_b_1_q; + reg [32:0] redist9_expFracRnd_uid12_fxpToFPTest_q_1_q; + reg [0:0] redist10_inIsZero_uid8_fxpToFPTest_q_2_q; + + + // GND(CONSTANT,0) + assign GND_q = 1'b0; + + // expInf_uid24_fxpToFPTest(CONSTANT,23) + assign expInf_uid24_fxpToFPTest_q = 8'b11111111; + + // expZ_uid33_fxpToFPTest(CONSTANT,32) + assign expZ_uid33_fxpToFPTest_q = 8'b00000000; + + // rVStage_uid72_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select(BITSELECT,89)@4 + assign rVStage_uid72_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_b = vStagei_uid70_lzcShifterZ1_uid6_fxpToFPTest_q[31:31]; + assign rVStage_uid72_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_c = vStagei_uid70_lzcShifterZ1_uid6_fxpToFPTest_q[30:0]; + + // cStage_uid76_lzcShifterZ1_uid6_fxpToFPTest(BITJOIN,75)@4 + assign cStage_uid76_lzcShifterZ1_uid6_fxpToFPTest_q = {rVStage_uid72_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_c, GND_q}; + + // rVStage_uid65_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select(BITSELECT,88)@4 + assign rVStage_uid65_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_b = vStagei_uid63_lzcShifterZ1_uid6_fxpToFPTest_q[31:30]; + assign rVStage_uid65_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_c = vStagei_uid63_lzcShifterZ1_uid6_fxpToFPTest_q[29:0]; + + // zs_uid64_lzcShifterZ1_uid6_fxpToFPTest(CONSTANT,63) + assign zs_uid64_lzcShifterZ1_uid6_fxpToFPTest_q = 2'b00; + + // cStage_uid69_lzcShifterZ1_uid6_fxpToFPTest(BITJOIN,68)@4 + assign cStage_uid69_lzcShifterZ1_uid6_fxpToFPTest_q = {rVStage_uid65_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_c, zs_uid64_lzcShifterZ1_uid6_fxpToFPTest_q}; + + // rVStage_uid58_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select(BITSELECT,87)@3 + assign rVStage_uid58_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_b = vStagei_uid56_lzcShifterZ1_uid6_fxpToFPTest_q[31:28]; + assign rVStage_uid58_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_c = vStagei_uid56_lzcShifterZ1_uid6_fxpToFPTest_q[27:0]; + + // zs_uid57_lzcShifterZ1_uid6_fxpToFPTest(CONSTANT,56) + assign zs_uid57_lzcShifterZ1_uid6_fxpToFPTest_q = 4'b0000; + + // cStage_uid62_lzcShifterZ1_uid6_fxpToFPTest(BITJOIN,61)@3 + assign cStage_uid62_lzcShifterZ1_uid6_fxpToFPTest_q = {rVStage_uid58_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_c, zs_uid57_lzcShifterZ1_uid6_fxpToFPTest_q}; + + // rVStage_uid51_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select(BITSELECT,86)@2 + assign rVStage_uid51_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_b = vStagei_uid49_lzcShifterZ1_uid6_fxpToFPTest_q[31:24]; + assign rVStage_uid51_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_c = vStagei_uid49_lzcShifterZ1_uid6_fxpToFPTest_q[23:0]; + + // cStage_uid55_lzcShifterZ1_uid6_fxpToFPTest(BITJOIN,54)@2 + assign cStage_uid55_lzcShifterZ1_uid6_fxpToFPTest_q = {rVStage_uid51_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_c, expZ_uid33_fxpToFPTest_q}; + + // rVStage_uid44_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select(BITSELECT,85)@1 + assign rVStage_uid44_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_b = vStagei_uid42_lzcShifterZ1_uid6_fxpToFPTest_q[31:16]; + assign rVStage_uid44_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_c = vStagei_uid42_lzcShifterZ1_uid6_fxpToFPTest_q[15:0]; + + // zs_uid43_lzcShifterZ1_uid6_fxpToFPTest(CONSTANT,42) + assign zs_uid43_lzcShifterZ1_uid6_fxpToFPTest_q = 16'b0000000000000000; + + // cStage_uid48_lzcShifterZ1_uid6_fxpToFPTest(BITJOIN,47)@1 + assign cStage_uid48_lzcShifterZ1_uid6_fxpToFPTest_q = {rVStage_uid44_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_c, zs_uid43_lzcShifterZ1_uid6_fxpToFPTest_q}; + + // zs_uid38_lzcShifterZ1_uid6_fxpToFPTest(CONSTANT,37) + assign zs_uid38_lzcShifterZ1_uid6_fxpToFPTest_q = 32'b00000000000000000000000000000000; + + // vCount_uid40_lzcShifterZ1_uid6_fxpToFPTest(LOGICAL,39)@0 + assign vCount_uid40_lzcShifterZ1_uid6_fxpToFPTest_q = a == zs_uid38_lzcShifterZ1_uid6_fxpToFPTest_q ? 1'b1 : 1'b0; + + // vStagei_uid42_lzcShifterZ1_uid6_fxpToFPTest(MUX,41)@0 + 1 + assign vStagei_uid42_lzcShifterZ1_uid6_fxpToFPTest_s = vCount_uid40_lzcShifterZ1_uid6_fxpToFPTest_q; + always @ (posedge clk) + begin + if (areset) + begin + vStagei_uid42_lzcShifterZ1_uid6_fxpToFPTest_q <= 32'b0; + end + else if (en == 1'b1) + begin + unique case (vStagei_uid42_lzcShifterZ1_uid6_fxpToFPTest_s) + 1'b0 : vStagei_uid42_lzcShifterZ1_uid6_fxpToFPTest_q <= a; + 1'b1 : vStagei_uid42_lzcShifterZ1_uid6_fxpToFPTest_q <= zs_uid38_lzcShifterZ1_uid6_fxpToFPTest_q; + default : vStagei_uid42_lzcShifterZ1_uid6_fxpToFPTest_q <= 32'b0; + endcase + end + end + + // vCount_uid45_lzcShifterZ1_uid6_fxpToFPTest(LOGICAL,44)@1 + assign vCount_uid45_lzcShifterZ1_uid6_fxpToFPTest_q = rVStage_uid44_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_b == zs_uid43_lzcShifterZ1_uid6_fxpToFPTest_q ? 1'b1 : 1'b0; + + // vStagei_uid49_lzcShifterZ1_uid6_fxpToFPTest(MUX,48)@1 + 1 + assign vStagei_uid49_lzcShifterZ1_uid6_fxpToFPTest_s = vCount_uid45_lzcShifterZ1_uid6_fxpToFPTest_q; + always @ (posedge clk) + begin + if (areset) + begin + vStagei_uid49_lzcShifterZ1_uid6_fxpToFPTest_q <= 32'b0; + end + else if (en == 1'b1) + begin + unique case (vStagei_uid49_lzcShifterZ1_uid6_fxpToFPTest_s) + 1'b0 : vStagei_uid49_lzcShifterZ1_uid6_fxpToFPTest_q <= vStagei_uid42_lzcShifterZ1_uid6_fxpToFPTest_q; + 1'b1 : vStagei_uid49_lzcShifterZ1_uid6_fxpToFPTest_q <= cStage_uid48_lzcShifterZ1_uid6_fxpToFPTest_q; + default : vStagei_uid49_lzcShifterZ1_uid6_fxpToFPTest_q <= 32'b0; + endcase + end + end + + // vCount_uid52_lzcShifterZ1_uid6_fxpToFPTest(LOGICAL,51)@2 + assign vCount_uid52_lzcShifterZ1_uid6_fxpToFPTest_q = rVStage_uid51_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_b == expZ_uid33_fxpToFPTest_q ? 1'b1 : 1'b0; + + // vStagei_uid56_lzcShifterZ1_uid6_fxpToFPTest(MUX,55)@2 + 1 + assign vStagei_uid56_lzcShifterZ1_uid6_fxpToFPTest_s = vCount_uid52_lzcShifterZ1_uid6_fxpToFPTest_q; + always @ (posedge clk) + begin + if (areset) + begin + vStagei_uid56_lzcShifterZ1_uid6_fxpToFPTest_q <= 32'b0; + end + else if (en == 1'b1) + begin + unique case (vStagei_uid56_lzcShifterZ1_uid6_fxpToFPTest_s) + 1'b0 : vStagei_uid56_lzcShifterZ1_uid6_fxpToFPTest_q <= vStagei_uid49_lzcShifterZ1_uid6_fxpToFPTest_q; + 1'b1 : vStagei_uid56_lzcShifterZ1_uid6_fxpToFPTest_q <= cStage_uid55_lzcShifterZ1_uid6_fxpToFPTest_q; + default : vStagei_uid56_lzcShifterZ1_uid6_fxpToFPTest_q <= 32'b0; + endcase + end + end + + // vCount_uid59_lzcShifterZ1_uid6_fxpToFPTest(LOGICAL,58)@3 + assign vCount_uid59_lzcShifterZ1_uid6_fxpToFPTest_q = rVStage_uid58_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_b == zs_uid57_lzcShifterZ1_uid6_fxpToFPTest_q ? 1'b1 : 1'b0; + + // vStagei_uid63_lzcShifterZ1_uid6_fxpToFPTest(MUX,62)@3 + 1 + assign vStagei_uid63_lzcShifterZ1_uid6_fxpToFPTest_s = vCount_uid59_lzcShifterZ1_uid6_fxpToFPTest_q; + always @ (posedge clk) + begin + if (areset) + begin + vStagei_uid63_lzcShifterZ1_uid6_fxpToFPTest_q <= 32'b0; + end + else if (en == 1'b1) + begin + unique case (vStagei_uid63_lzcShifterZ1_uid6_fxpToFPTest_s) + 1'b0 : vStagei_uid63_lzcShifterZ1_uid6_fxpToFPTest_q <= vStagei_uid56_lzcShifterZ1_uid6_fxpToFPTest_q; + 1'b1 : vStagei_uid63_lzcShifterZ1_uid6_fxpToFPTest_q <= cStage_uid62_lzcShifterZ1_uid6_fxpToFPTest_q; + default : vStagei_uid63_lzcShifterZ1_uid6_fxpToFPTest_q <= 32'b0; + endcase + end + end + + // vCount_uid66_lzcShifterZ1_uid6_fxpToFPTest(LOGICAL,65)@4 + assign vCount_uid66_lzcShifterZ1_uid6_fxpToFPTest_q = rVStage_uid65_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_b == zs_uid64_lzcShifterZ1_uid6_fxpToFPTest_q ? 1'b1 : 1'b0; + + // vStagei_uid70_lzcShifterZ1_uid6_fxpToFPTest(MUX,69)@4 + assign vStagei_uid70_lzcShifterZ1_uid6_fxpToFPTest_s = vCount_uid66_lzcShifterZ1_uid6_fxpToFPTest_q; + always @(vStagei_uid70_lzcShifterZ1_uid6_fxpToFPTest_s or en or vStagei_uid63_lzcShifterZ1_uid6_fxpToFPTest_q or cStage_uid69_lzcShifterZ1_uid6_fxpToFPTest_q) + begin + unique case (vStagei_uid70_lzcShifterZ1_uid6_fxpToFPTest_s) + 1'b0 : vStagei_uid70_lzcShifterZ1_uid6_fxpToFPTest_q = vStagei_uid63_lzcShifterZ1_uid6_fxpToFPTest_q; + 1'b1 : vStagei_uid70_lzcShifterZ1_uid6_fxpToFPTest_q = cStage_uid69_lzcShifterZ1_uid6_fxpToFPTest_q; + default : vStagei_uid70_lzcShifterZ1_uid6_fxpToFPTest_q = 32'b0; + endcase + end + + // vCount_uid73_lzcShifterZ1_uid6_fxpToFPTest(LOGICAL,72)@4 + assign vCount_uid73_lzcShifterZ1_uid6_fxpToFPTest_q = rVStage_uid72_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_b == GND_q ? 1'b1 : 1'b0; + + // vStagei_uid77_lzcShifterZ1_uid6_fxpToFPTest(MUX,76)@4 + assign vStagei_uid77_lzcShifterZ1_uid6_fxpToFPTest_s = vCount_uid73_lzcShifterZ1_uid6_fxpToFPTest_q; + always @(vStagei_uid77_lzcShifterZ1_uid6_fxpToFPTest_s or en or vStagei_uid70_lzcShifterZ1_uid6_fxpToFPTest_q or cStage_uid76_lzcShifterZ1_uid6_fxpToFPTest_q) + begin + unique case (vStagei_uid77_lzcShifterZ1_uid6_fxpToFPTest_s) + 1'b0 : vStagei_uid77_lzcShifterZ1_uid6_fxpToFPTest_q = vStagei_uid70_lzcShifterZ1_uid6_fxpToFPTest_q; + 1'b1 : vStagei_uid77_lzcShifterZ1_uid6_fxpToFPTest_q = cStage_uid76_lzcShifterZ1_uid6_fxpToFPTest_q; + default : vStagei_uid77_lzcShifterZ1_uid6_fxpToFPTest_q = 32'b0; + endcase + end + + // fracRnd_uid11_fxpToFPTest_merged_bit_select(BITSELECT,90)@4 + assign fracRnd_uid11_fxpToFPTest_merged_bit_select_in = vStagei_uid77_lzcShifterZ1_uid6_fxpToFPTest_q[30:0]; + assign fracRnd_uid11_fxpToFPTest_merged_bit_select_b = fracRnd_uid11_fxpToFPTest_merged_bit_select_in[30:7]; + assign fracRnd_uid11_fxpToFPTest_merged_bit_select_c = fracRnd_uid11_fxpToFPTest_merged_bit_select_in[6:0]; + + // redist1_fracRnd_uid11_fxpToFPTest_merged_bit_select_c_1(DELAY,92) + always @ (posedge clk) + begin + if (areset) + begin + redist1_fracRnd_uid11_fxpToFPTest_merged_bit_select_c_1_q <= '0; + end + else if (en == 1'b1) + begin + redist1_fracRnd_uid11_fxpToFPTest_merged_bit_select_c_1_q <= fracRnd_uid11_fxpToFPTest_merged_bit_select_c; + end + end + + // sticky_uid16_fxpToFPTest(LOGICAL,15)@5 + assign sticky_uid16_fxpToFPTest_q = redist1_fracRnd_uid11_fxpToFPTest_merged_bit_select_c_1_q != 7'b0000000 ? 1'b1 : 1'b0; + + // nr_uid17_fxpToFPTest(LOGICAL,16)@5 + assign nr_uid17_fxpToFPTest_q = ~ (l_uid13_fxpToFPTest_merged_bit_select_c); + + // maxCount_uid7_fxpToFPTest(CONSTANT,6) + assign maxCount_uid7_fxpToFPTest_q = 6'b100000; + + // redist6_vCount_uid40_lzcShifterZ1_uid6_fxpToFPTest_q_4(DELAY,97) + always @ (posedge clk) + begin + if (areset) + begin + redist6_vCount_uid40_lzcShifterZ1_uid6_fxpToFPTest_q_4_delay_0 <= '0; + redist6_vCount_uid40_lzcShifterZ1_uid6_fxpToFPTest_q_4_delay_1 <= '0; + redist6_vCount_uid40_lzcShifterZ1_uid6_fxpToFPTest_q_4_delay_2 <= '0; + redist6_vCount_uid40_lzcShifterZ1_uid6_fxpToFPTest_q_4_q <= '0; + end + else if (en == 1'b1) + begin + redist6_vCount_uid40_lzcShifterZ1_uid6_fxpToFPTest_q_4_delay_0 <= vCount_uid40_lzcShifterZ1_uid6_fxpToFPTest_q; + redist6_vCount_uid40_lzcShifterZ1_uid6_fxpToFPTest_q_4_delay_1 <= redist6_vCount_uid40_lzcShifterZ1_uid6_fxpToFPTest_q_4_delay_0; + redist6_vCount_uid40_lzcShifterZ1_uid6_fxpToFPTest_q_4_delay_2 <= redist6_vCount_uid40_lzcShifterZ1_uid6_fxpToFPTest_q_4_delay_1; + redist6_vCount_uid40_lzcShifterZ1_uid6_fxpToFPTest_q_4_q <= redist6_vCount_uid40_lzcShifterZ1_uid6_fxpToFPTest_q_4_delay_2; + end + end + + // redist5_vCount_uid45_lzcShifterZ1_uid6_fxpToFPTest_q_3(DELAY,96) + always @ (posedge clk) + begin + if (areset) + begin + redist5_vCount_uid45_lzcShifterZ1_uid6_fxpToFPTest_q_3_delay_0 <= '0; + redist5_vCount_uid45_lzcShifterZ1_uid6_fxpToFPTest_q_3_delay_1 <= '0; + redist5_vCount_uid45_lzcShifterZ1_uid6_fxpToFPTest_q_3_q <= '0; + end + else if (en == 1'b1) + begin + redist5_vCount_uid45_lzcShifterZ1_uid6_fxpToFPTest_q_3_delay_0 <= vCount_uid45_lzcShifterZ1_uid6_fxpToFPTest_q; + redist5_vCount_uid45_lzcShifterZ1_uid6_fxpToFPTest_q_3_delay_1 <= redist5_vCount_uid45_lzcShifterZ1_uid6_fxpToFPTest_q_3_delay_0; + redist5_vCount_uid45_lzcShifterZ1_uid6_fxpToFPTest_q_3_q <= redist5_vCount_uid45_lzcShifterZ1_uid6_fxpToFPTest_q_3_delay_1; + end + end + + // redist4_vCount_uid52_lzcShifterZ1_uid6_fxpToFPTest_q_2(DELAY,95) + always @ (posedge clk) + begin + if (areset) + begin + redist4_vCount_uid52_lzcShifterZ1_uid6_fxpToFPTest_q_2_delay_0 <= '0; + redist4_vCount_uid52_lzcShifterZ1_uid6_fxpToFPTest_q_2_q <= '0; + end + else if (en == 1'b1) + begin + redist4_vCount_uid52_lzcShifterZ1_uid6_fxpToFPTest_q_2_delay_0 <= vCount_uid52_lzcShifterZ1_uid6_fxpToFPTest_q; + redist4_vCount_uid52_lzcShifterZ1_uid6_fxpToFPTest_q_2_q <= redist4_vCount_uid52_lzcShifterZ1_uid6_fxpToFPTest_q_2_delay_0; + end + end + + // redist3_vCount_uid59_lzcShifterZ1_uid6_fxpToFPTest_q_1(DELAY,94) + always @ (posedge clk) + begin + if (areset) + begin + redist3_vCount_uid59_lzcShifterZ1_uid6_fxpToFPTest_q_1_q <= '0; + end + else if (en == 1'b1) + begin + redist3_vCount_uid59_lzcShifterZ1_uid6_fxpToFPTest_q_1_q <= vCount_uid59_lzcShifterZ1_uid6_fxpToFPTest_q; + end + end + + // vCount_uid78_lzcShifterZ1_uid6_fxpToFPTest(BITJOIN,77)@4 + assign vCount_uid78_lzcShifterZ1_uid6_fxpToFPTest_q = {redist6_vCount_uid40_lzcShifterZ1_uid6_fxpToFPTest_q_4_q, redist5_vCount_uid45_lzcShifterZ1_uid6_fxpToFPTest_q_3_q, redist4_vCount_uid52_lzcShifterZ1_uid6_fxpToFPTest_q_2_q, redist3_vCount_uid59_lzcShifterZ1_uid6_fxpToFPTest_q_1_q, vCount_uid66_lzcShifterZ1_uid6_fxpToFPTest_q, vCount_uid73_lzcShifterZ1_uid6_fxpToFPTest_q}; + + // redist2_vCount_uid78_lzcShifterZ1_uid6_fxpToFPTest_q_1(DELAY,93) + always @ (posedge clk) + begin + if (areset) + begin + redist2_vCount_uid78_lzcShifterZ1_uid6_fxpToFPTest_q_1_q <= '0; + end + else if (en == 1'b1) + begin + redist2_vCount_uid78_lzcShifterZ1_uid6_fxpToFPTest_q_1_q <= vCount_uid78_lzcShifterZ1_uid6_fxpToFPTest_q; + end + end + + // vCountBig_uid80_lzcShifterZ1_uid6_fxpToFPTest(COMPARE,79)@4 + 1 + assign vCountBig_uid80_lzcShifterZ1_uid6_fxpToFPTest_a = {2'b00, maxCount_uid7_fxpToFPTest_q}; + assign vCountBig_uid80_lzcShifterZ1_uid6_fxpToFPTest_b = {2'b00, vCount_uid78_lzcShifterZ1_uid6_fxpToFPTest_q}; + always @ (posedge clk) + begin + if (areset) + begin + vCountBig_uid80_lzcShifterZ1_uid6_fxpToFPTest_o <= 8'b0; + end + else if (en == 1'b1) + begin + vCountBig_uid80_lzcShifterZ1_uid6_fxpToFPTest_o <= $unsigned(vCountBig_uid80_lzcShifterZ1_uid6_fxpToFPTest_a) - $unsigned(vCountBig_uid80_lzcShifterZ1_uid6_fxpToFPTest_b); + end + end + assign vCountBig_uid80_lzcShifterZ1_uid6_fxpToFPTest_c[0] = vCountBig_uid80_lzcShifterZ1_uid6_fxpToFPTest_o[7]; + + // vCountFinal_uid82_lzcShifterZ1_uid6_fxpToFPTest(MUX,81)@5 + assign vCountFinal_uid82_lzcShifterZ1_uid6_fxpToFPTest_s = vCountBig_uid80_lzcShifterZ1_uid6_fxpToFPTest_c; + always @(vCountFinal_uid82_lzcShifterZ1_uid6_fxpToFPTest_s or en or redist2_vCount_uid78_lzcShifterZ1_uid6_fxpToFPTest_q_1_q or maxCount_uid7_fxpToFPTest_q) + begin + unique case (vCountFinal_uid82_lzcShifterZ1_uid6_fxpToFPTest_s) + 1'b0 : vCountFinal_uid82_lzcShifterZ1_uid6_fxpToFPTest_q = redist2_vCount_uid78_lzcShifterZ1_uid6_fxpToFPTest_q_1_q; + 1'b1 : vCountFinal_uid82_lzcShifterZ1_uid6_fxpToFPTest_q = maxCount_uid7_fxpToFPTest_q; + default : vCountFinal_uid82_lzcShifterZ1_uid6_fxpToFPTest_q = 6'b0; + endcase + end + + // msbIn_uid9_fxpToFPTest(CONSTANT,8) + assign msbIn_uid9_fxpToFPTest_q = 8'b10011110; + + // expPreRnd_uid10_fxpToFPTest(SUB,9)@5 + assign expPreRnd_uid10_fxpToFPTest_a = {1'b0, msbIn_uid9_fxpToFPTest_q}; + assign expPreRnd_uid10_fxpToFPTest_b = {3'b000, vCountFinal_uid82_lzcShifterZ1_uid6_fxpToFPTest_q}; + assign expPreRnd_uid10_fxpToFPTest_o = $unsigned(expPreRnd_uid10_fxpToFPTest_a) - $unsigned(expPreRnd_uid10_fxpToFPTest_b); + assign expPreRnd_uid10_fxpToFPTest_q = expPreRnd_uid10_fxpToFPTest_o[8:0]; + + // redist0_fracRnd_uid11_fxpToFPTest_merged_bit_select_b_1(DELAY,91) + always @ (posedge clk) + begin + if (areset) + begin + redist0_fracRnd_uid11_fxpToFPTest_merged_bit_select_b_1_q <= '0; + end + else if (en == 1'b1) + begin + redist0_fracRnd_uid11_fxpToFPTest_merged_bit_select_b_1_q <= fracRnd_uid11_fxpToFPTest_merged_bit_select_b; + end + end + + // expFracRnd_uid12_fxpToFPTest(BITJOIN,11)@5 + assign expFracRnd_uid12_fxpToFPTest_q = {expPreRnd_uid10_fxpToFPTest_q, redist0_fracRnd_uid11_fxpToFPTest_merged_bit_select_b_1_q}; + + // l_uid13_fxpToFPTest_merged_bit_select(BITSELECT,84)@5 + assign l_uid13_fxpToFPTest_merged_bit_select_in = expFracRnd_uid12_fxpToFPTest_q[1:0]; + assign l_uid13_fxpToFPTest_merged_bit_select_b = l_uid13_fxpToFPTest_merged_bit_select_in[1:1]; + assign l_uid13_fxpToFPTest_merged_bit_select_c = l_uid13_fxpToFPTest_merged_bit_select_in[0:0]; + + // rnd_uid18_fxpToFPTest(LOGICAL,17)@5 + 1 + assign rnd_uid18_fxpToFPTest_qi = l_uid13_fxpToFPTest_merged_bit_select_b | nr_uid17_fxpToFPTest_q | sticky_uid16_fxpToFPTest_q; + dspba_delay_ver #( .width(1), .depth(1), .reset_kind("SYNC"), .phase(0), .modulus(1) ) + rnd_uid18_fxpToFPTest_delay ( .xin(rnd_uid18_fxpToFPTest_qi), .xout(rnd_uid18_fxpToFPTest_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // redist9_expFracRnd_uid12_fxpToFPTest_q_1(DELAY,100) + always @ (posedge clk) + begin + if (areset) + begin + redist9_expFracRnd_uid12_fxpToFPTest_q_1_q <= '0; + end + else if (en == 1'b1) + begin + redist9_expFracRnd_uid12_fxpToFPTest_q_1_q <= expFracRnd_uid12_fxpToFPTest_q; + end + end + + // expFracR_uid20_fxpToFPTest(ADD,19)@6 + assign expFracR_uid20_fxpToFPTest_a = {{2{redist9_expFracRnd_uid12_fxpToFPTest_q_1_q[32]}}, redist9_expFracRnd_uid12_fxpToFPTest_q_1_q}; + assign expFracR_uid20_fxpToFPTest_b = {34'b0000000000000000000000000000000000, rnd_uid18_fxpToFPTest_q}; + assign expFracR_uid20_fxpToFPTest_o = $signed(expFracR_uid20_fxpToFPTest_a) + $signed(expFracR_uid20_fxpToFPTest_b); + assign expFracR_uid20_fxpToFPTest_q = expFracR_uid20_fxpToFPTest_o[33:0]; + + // expR_uid22_fxpToFPTest(BITSELECT,21)@6 + assign expR_uid22_fxpToFPTest_b = expFracR_uid20_fxpToFPTest_q[33:24]; + + // redist7_expR_uid22_fxpToFPTest_b_1(DELAY,98) + always @ (posedge clk) + begin + if (areset) + begin + redist7_expR_uid22_fxpToFPTest_b_1_q <= '0; + end + else if (en == 1'b1) + begin + redist7_expR_uid22_fxpToFPTest_b_1_q <= expR_uid22_fxpToFPTest_b; + end + end + + // expR_uid34_fxpToFPTest(BITSELECT,33)@7 + assign expR_uid34_fxpToFPTest_in = redist7_expR_uid22_fxpToFPTest_b_1_q[7:0]; + assign expR_uid34_fxpToFPTest_b = expR_uid34_fxpToFPTest_in[7:0]; + + // ovf_uid25_fxpToFPTest(COMPARE,24)@7 + assign ovf_uid25_fxpToFPTest_a = {{2{redist7_expR_uid22_fxpToFPTest_b_1_q[9]}}, redist7_expR_uid22_fxpToFPTest_b_1_q}; + assign ovf_uid25_fxpToFPTest_b = {4'b0000, expInf_uid24_fxpToFPTest_q}; + assign ovf_uid25_fxpToFPTest_o = $signed(ovf_uid25_fxpToFPTest_a) - $signed(ovf_uid25_fxpToFPTest_b); + assign ovf_uid25_fxpToFPTest_n[0] = ~ (ovf_uid25_fxpToFPTest_o[11]); + + // inIsZero_uid8_fxpToFPTest(LOGICAL,7)@5 + 1 + assign inIsZero_uid8_fxpToFPTest_qi = vCountFinal_uid82_lzcShifterZ1_uid6_fxpToFPTest_q == maxCount_uid7_fxpToFPTest_q ? 1'b1 : 1'b0; + dspba_delay_ver #( .width(1), .depth(1), .reset_kind("SYNC"), .phase(0), .modulus(1) ) + inIsZero_uid8_fxpToFPTest_delay ( .xin(inIsZero_uid8_fxpToFPTest_qi), .xout(inIsZero_uid8_fxpToFPTest_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // redist10_inIsZero_uid8_fxpToFPTest_q_2(DELAY,101) + always @ (posedge clk) + begin + if (areset) + begin + redist10_inIsZero_uid8_fxpToFPTest_q_2_q <= '0; + end + else if (en == 1'b1) + begin + redist10_inIsZero_uid8_fxpToFPTest_q_2_q <= inIsZero_uid8_fxpToFPTest_q; + end + end + + // udf_uid23_fxpToFPTest(COMPARE,22)@7 + assign udf_uid23_fxpToFPTest_a = {11'b00000000000, GND_q}; + assign udf_uid23_fxpToFPTest_b = {{2{redist7_expR_uid22_fxpToFPTest_b_1_q[9]}}, redist7_expR_uid22_fxpToFPTest_b_1_q}; + assign udf_uid23_fxpToFPTest_o = $signed(udf_uid23_fxpToFPTest_a) - $signed(udf_uid23_fxpToFPTest_b); + assign udf_uid23_fxpToFPTest_n[0] = ~ (udf_uid23_fxpToFPTest_o[11]); + + // udfOrInZero_uid29_fxpToFPTest(LOGICAL,28)@7 + assign udfOrInZero_uid29_fxpToFPTest_q = udf_uid23_fxpToFPTest_n | redist10_inIsZero_uid8_fxpToFPTest_q_2_q; + + // excSelector_uid30_fxpToFPTest(BITJOIN,29)@7 + assign excSelector_uid30_fxpToFPTest_q = {ovf_uid25_fxpToFPTest_n, udfOrInZero_uid29_fxpToFPTest_q}; + + // expRPostExc_uid35_fxpToFPTest(MUX,34)@7 + assign expRPostExc_uid35_fxpToFPTest_s = excSelector_uid30_fxpToFPTest_q; + always @(expRPostExc_uid35_fxpToFPTest_s or en or expR_uid34_fxpToFPTest_b or expZ_uid33_fxpToFPTest_q or expInf_uid24_fxpToFPTest_q) + begin + unique case (expRPostExc_uid35_fxpToFPTest_s) + 2'b00 : expRPostExc_uid35_fxpToFPTest_q = expR_uid34_fxpToFPTest_b; + 2'b01 : expRPostExc_uid35_fxpToFPTest_q = expZ_uid33_fxpToFPTest_q; + 2'b10 : expRPostExc_uid35_fxpToFPTest_q = expInf_uid24_fxpToFPTest_q; + 2'b11 : expRPostExc_uid35_fxpToFPTest_q = expInf_uid24_fxpToFPTest_q; + default : expRPostExc_uid35_fxpToFPTest_q = 8'b0; + endcase + end + + // fracZ_uid27_fxpToFPTest(CONSTANT,26) + assign fracZ_uid27_fxpToFPTest_q = 23'b00000000000000000000000; + + // fracR_uid21_fxpToFPTest(BITSELECT,20)@6 + assign fracR_uid21_fxpToFPTest_in = expFracR_uid20_fxpToFPTest_q[23:0]; + assign fracR_uid21_fxpToFPTest_b = fracR_uid21_fxpToFPTest_in[23:1]; + + // redist8_fracR_uid21_fxpToFPTest_b_1(DELAY,99) + always @ (posedge clk) + begin + if (areset) + begin + redist8_fracR_uid21_fxpToFPTest_b_1_q <= '0; + end + else if (en == 1'b1) + begin + redist8_fracR_uid21_fxpToFPTest_b_1_q <= fracR_uid21_fxpToFPTest_b; + end + end + + // excSelector_uid26_fxpToFPTest(LOGICAL,25)@7 + assign excSelector_uid26_fxpToFPTest_q = redist10_inIsZero_uid8_fxpToFPTest_q_2_q | ovf_uid25_fxpToFPTest_n | udf_uid23_fxpToFPTest_n; + + // fracRPostExc_uid28_fxpToFPTest(MUX,27)@7 + assign fracRPostExc_uid28_fxpToFPTest_s = excSelector_uid26_fxpToFPTest_q; + always @(fracRPostExc_uid28_fxpToFPTest_s or en or redist8_fracR_uid21_fxpToFPTest_b_1_q or fracZ_uid27_fxpToFPTest_q) + begin + unique case (fracRPostExc_uid28_fxpToFPTest_s) + 1'b0 : fracRPostExc_uid28_fxpToFPTest_q = redist8_fracR_uid21_fxpToFPTest_b_1_q; + 1'b1 : fracRPostExc_uid28_fxpToFPTest_q = fracZ_uid27_fxpToFPTest_q; + default : fracRPostExc_uid28_fxpToFPTest_q = 23'b0; + endcase + end + + // outRes_uid36_fxpToFPTest(BITJOIN,35)@7 + assign outRes_uid36_fxpToFPTest_q = {GND_q, expRPostExc_uid35_fxpToFPTest_q, fracRPostExc_uid28_fxpToFPTest_q}; + + // xOut(GPOUT,4)@7 + assign q = outRes_uid36_fxpToFPTest_q; + +endmodule diff --git a/hw/rtl/fp_cores/altera/stratix10/dspba_delay_ver.sv b/hw/rtl/fp_cores/altera/stratix10/dspba_delay_ver.sv new file mode 100644 index 00000000..4548682b --- /dev/null +++ b/hw/rtl/fp_cores/altera/stratix10/dspba_delay_ver.sv @@ -0,0 +1,98 @@ +// Legal Notice: Copyright 2017 Intel Corporation. All rights reserved. +// Your use of Intel Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing device programming or simulation files), and +// any associated documentation or information are expressly subject to the +// terms and conditions of the Intel FPGA Software License Agreement, +// Intel MegaCore Function License Agreement, or other applicable license +// agreement, including, without limitation, that your use is for the sole +// purpose of programming logic devices manufactured by Intel and sold by +// Intel or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +module dspba_delay_ver +#( + parameter width = 8, + parameter depth = 1, + parameter reset_high = 1'b1, + parameter reset_kind = "ASYNC", + parameter phase = 0, + parameter modulus = 1 +) ( + input clk, + input aclr, + input ena, + input [width-1:0] xin, + output [width-1:0] xout +); + + wire reset; + reg [width-1:0] delays [depth-1:0]; + + assign reset = aclr ^ reset_high; + + generate + if (depth > 0) + begin + genvar i; + for (i = 0; i < depth; ++i) + begin : delay_block + if ((reset_kind == "ASYNC") && (0 == (phase + i) % modulus)) + begin : async_reset + always @ (posedge clk or negedge reset) + begin: a + if (!reset) begin + delays[i] <= 0; + end else begin + if (ena) begin + if (i > 0) begin + delays[i] <= delays[i - 1]; + end else begin + delays[i] <= xin; + end + end + end + end + end + + if ((reset_kind == "SYNC") && (0 == (phase + i) % modulus)) + begin : sync_reset + always @ (posedge clk) + begin: a + if (!reset) begin + delays[i] <= 0; + end else begin + if (ena) begin + if (i > 0) begin + delays[i] <= delays[i - 1]; + end else begin + delays[i] <= xin; + end + end + end + end + end + + if ((reset_kind == "NONE") || (0 != (phase + i) % modulus)) + begin : no_reset + always @ (posedge clk) + begin: a + if (ena) begin + if (i > 0) begin + delays[i] <= delays[i - 1]; + end else begin + delays[i] <= xin; + end + end + end + end + end + + assign xout = delays[depth - 1]; + end else begin + assign xout = xin; + end + endgenerate + +endmodule \ No newline at end of file diff --git a/hw/syn/quartus/core/Makefile b/hw/syn/quartus/core/Makefile index 477d454d..1f41fa5f 100644 --- a/hw/syn/quartus/core/Makefile +++ b/hw/syn/quartus/core/Makefile @@ -1,7 +1,7 @@ PROJECT = Core TOP_LEVEL_ENTITY = VX_core SRC_FILE = VX_core.v -FPU_INCLUDE = ../../../rtl/fp_cores;../../../rtl/fp_cores/altera;../../../rtl/fp_cores/fpnew/src;../../../rtl/fp_cores/fpnew/src/fpu_div_sqrt_mvp/hdl;../../../rtl/fp_cores/fpnew/src/common_cells/include;../../../rtl/fp_cores/fpnew/src/common_cells/src +FPU_INCLUDE = ../../../rtl/fp_cores;../../../rtl/fp_cores/altera/arria10;../../../rtl/fp_cores/fpnew/src;../../../rtl/fp_cores/fpnew/src/fpu_div_sqrt_mvp/hdl;../../../rtl/fp_cores/fpnew/src/common_cells/include;../../../rtl/fp_cores/fpnew/src/common_cells/src RTL_INCLUDE = $(FPU_INCLUDE);../../../rtl;../../../rtl/libs;../../../rtl/interfaces;../../../rtl/cache PROJECT_FILES = $(PROJECT).qpf $(PROJECT).qsf diff --git a/hw/syn/quartus/core8/Makefile b/hw/syn/quartus/core8/Makefile index 9cbb35c7..fe1e02ae 100644 --- a/hw/syn/quartus/core8/Makefile +++ b/hw/syn/quartus/core8/Makefile @@ -1,7 +1,7 @@ PROJECT = Core TOP_LEVEL_ENTITY = VX_core SRC_FILE = VX_core.v -FPU_INCLUDE = ../../../rtl/fp_cores;../../../rtl/fp_cores/altera;../../../rtl/fp_cores/fpnew/src;../../../rtl/fp_cores/fpnew/src/fpu_div_sqrt_mvp/hdl;../../../rtl/fp_cores/fpnew/src/common_cells/include;../../../rtl/fp_cores/fpnew/src/common_cells/src +FPU_INCLUDE = ../../../rtl/fp_cores;../../../rtl/fp_cores/altera/arria10;../../../rtl/fp_cores/fpnew/src;../../../rtl/fp_cores/fpnew/src/fpu_div_sqrt_mvp/hdl;../../../rtl/fp_cores/fpnew/src/common_cells/include;../../../rtl/fp_cores/fpnew/src/common_cells/src RTL_INCLUDE = $(FPU_INCLUDE);../../../rtl;../../../rtl/libs;../../../rtl/interfaces;../../../rtl/cache PROJECT_FILES = $(PROJECT).qpf $(PROJECT).qsf diff --git a/hw/syn/quartus/pipeline/Makefile b/hw/syn/quartus/pipeline/Makefile index 76bad071..67941e7f 100644 --- a/hw/syn/quartus/pipeline/Makefile +++ b/hw/syn/quartus/pipeline/Makefile @@ -1,7 +1,7 @@ PROJECT = VX_pipeline TOP_LEVEL_ENTITY = VX_pipeline SRC_FILE = VX_pipeline.v -FPU_INCLUDE = ../../../rtl/fp_cores;../../../rtl/fp_cores/altera;../../../rtl/fp_cores/fpnew/src;../../../rtl/fp_cores/fpnew/src/fpu_div_sqrt_mvp/hdl;../../../rtl/fp_cores/fpnew/src/common_cells/include;../../../rtl/fp_cores/fpnew/src/common_cells/src +FPU_INCLUDE = ../../../rtl/fp_cores;../../../rtl/fp_cores/altera/arria10;../../../rtl/fp_cores/fpnew/src;../../../rtl/fp_cores/fpnew/src/fpu_div_sqrt_mvp/hdl;../../../rtl/fp_cores/fpnew/src/common_cells/include;../../../rtl/fp_cores/fpnew/src/common_cells/src RTL_INCLUDE = $(FPU_INCLUDE);../../../rtl;../../../rtl/libs;../../../rtl/interfaces PROJECT_FILES = $(PROJECT).qpf $(PROJECT).qsf diff --git a/hw/syn/quartus/project.tcl b/hw/syn/quartus/project.tcl index 8edc3278..061841b8 100644 --- a/hw/syn/quartus/project.tcl +++ b/hw/syn/quartus/project.tcl @@ -59,6 +59,19 @@ set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON set_global_assignment -name POWER_USE_TA_VALUE 65 set_global_assignment -name SEED 1 +switch $opts(family) { + "Arria 10" { + set_global_assignment -name VERILOG_MACRO ALTERA_A10 + } + "Stratix 10" { + set_global_assignment -name VERILOG_MACRO ALTERA_S10 + } + default { + puts stderr "Invalid device family" + exit 1 + } +} + set idx 0 foreach arg $q_args_orig { incr idx diff --git a/hw/syn/quartus/top/Makefile b/hw/syn/quartus/top/Makefile index 32ebc882..981dc60b 100644 --- a/hw/syn/quartus/top/Makefile +++ b/hw/syn/quartus/top/Makefile @@ -1,7 +1,7 @@ PROJECT = vortex_afu TOP_LEVEL_ENTITY = vortex_afu SRC_FILE = vortex_afu.sv -FPU_INCLUDE = ../../../rtl/fp_cores;../../../rtl/fp_cores/altera;../../../rtl/fp_cores/fpnew/src;../../../rtl/fp_cores/fpnew/src/fpu_div_sqrt_mvp/hdl;../../../rtl/fp_cores/fpnew/src/common_cells/include;../../../rtl/fp_cores/fpnew/src/common_cells/src +FPU_INCLUDE = ../../../rtl/fp_cores;../../../rtl/fp_cores/altera/arria10;../../../rtl/fp_cores/fpnew/src;../../../rtl/fp_cores/fpnew/src/fpu_div_sqrt_mvp/hdl;../../../rtl/fp_cores/fpnew/src/common_cells/include;../../../rtl/fp_cores/fpnew/src/common_cells/src RTL_INCLUDE = $(FPU_INCLUDE);../../../rtl;../../../rtl/libs;../../../rtl/interfaces;../../../rtl/cache;../../../rtl/afu;../../../rtl/afu/ccip PROJECT_FILES = $(PROJECT).qpf $(PROJECT).qsf diff --git a/hw/syn/quartus/top1/Makefile b/hw/syn/quartus/top1/Makefile index 34db9257..765e7c1a 100644 --- a/hw/syn/quartus/top1/Makefile +++ b/hw/syn/quartus/top1/Makefile @@ -1,7 +1,7 @@ PROJECT = vortex_afu TOP_LEVEL_ENTITY = vortex_afu SRC_FILE = vortex_afu.sv -FPU_INCLUDE = ../../../rtl/fp_cores;../../../rtl/fp_cores/altera;../../../rtl/fp_cores/fpnew/src;../../../rtl/fp_cores/fpnew/src/fpu_div_sqrt_mvp/hdl;../../../rtl/fp_cores/fpnew/src/common_cells/include;../../../rtl/fp_cores/fpnew/src/common_cells/src +FPU_INCLUDE = ../../../rtl/fp_cores;../../../rtl/fp_cores/altera/arria10;../../../rtl/fp_cores/fpnew/src;../../../rtl/fp_cores/fpnew/src/fpu_div_sqrt_mvp/hdl;../../../rtl/fp_cores/fpnew/src/common_cells/include;../../../rtl/fp_cores/fpnew/src/common_cells/src RTL_INCLUDE = $(FPU_INCLUDE);../../../rtl;../../../rtl/libs;../../../rtl/interfaces;../../../rtl/cache;../../../rtl/afu;../../../rtl/afu/ccip PROJECT_FILES = $(PROJECT).qpf $(PROJECT).qsf diff --git a/hw/syn/quartus/top2/Makefile b/hw/syn/quartus/top2/Makefile index 5c02d012..acb95d25 100644 --- a/hw/syn/quartus/top2/Makefile +++ b/hw/syn/quartus/top2/Makefile @@ -1,7 +1,7 @@ PROJECT = vortex_afu TOP_LEVEL_ENTITY = vortex_afu SRC_FILE = vortex_afu.sv -FPU_INCLUDE = ../../../rtl/fp_cores;../../../rtl/fp_cores/altera;../../../rtl/fp_cores/fpnew/src;../../../rtl/fp_cores/fpnew/src/fpu_div_sqrt_mvp/hdl;../../../rtl/fp_cores/fpnew/src/common_cells/include;../../../rtl/fp_cores/fpnew/src/common_cells/src +FPU_INCLUDE = ../../../rtl/fp_cores;../../../rtl/fp_cores/altera/arria10;../../../rtl/fp_cores/fpnew/src;../../../rtl/fp_cores/fpnew/src/fpu_div_sqrt_mvp/hdl;../../../rtl/fp_cores/fpnew/src/common_cells/include;../../../rtl/fp_cores/fpnew/src/common_cells/src RTL_INCLUDE = $(FPU_INCLUDE);../../../rtl;../../../rtl/libs;../../../rtl/interfaces;../../../rtl/cache;../../../rtl/afu;../../../rtl/afu/ccip PROJECT_FILES = $(PROJECT).qpf $(PROJECT).qsf diff --git a/hw/syn/quartus/top8/Makefile b/hw/syn/quartus/top8/Makefile index 1adeec6a..71d1bd39 100644 --- a/hw/syn/quartus/top8/Makefile +++ b/hw/syn/quartus/top8/Makefile @@ -1,7 +1,7 @@ PROJECT = vortex_afu TOP_LEVEL_ENTITY = vortex_afu SRC_FILE = vortex_afu.sv -FPU_INCLUDE = ../../../rtl/fp_cores;../../../rtl/fp_cores/altera;../../../rtl/fp_cores/fpnew/src;../../../rtl/fp_cores/fpnew/src/fpu_div_sqrt_mvp/hdl;../../../rtl/fp_cores/fpnew/src/common_cells/include;../../../rtl/fp_cores/fpnew/src/common_cells/src +FPU_INCLUDE = ../../../rtl/fp_cores;../../../rtl/fp_cores/altera/stratix10;../../../rtl/fp_cores/fpnew/src;../../../rtl/fp_cores/fpnew/src/fpu_div_sqrt_mvp/hdl;../../../rtl/fp_cores/fpnew/src/common_cells/include;../../../rtl/fp_cores/fpnew/src/common_cells/src RTL_INCLUDE = $(FPU_INCLUDE);../../../rtl;../../../rtl/libs;../../../rtl/interfaces;../../../rtl/cache;../../../rtl/afu;../../../rtl/afu/ccip PROJECT_FILES = $(PROJECT).qpf $(PROJECT).qsf diff --git a/hw/syn/quartus/vortex/Makefile b/hw/syn/quartus/vortex/Makefile index e424db86..17e2023b 100644 --- a/hw/syn/quartus/vortex/Makefile +++ b/hw/syn/quartus/vortex/Makefile @@ -1,7 +1,7 @@ PROJECT = Vortex TOP_LEVEL_ENTITY = Vortex SRC_FILE = Vortex.v -FPU_INCLUDE = ../../../rtl/fp_cores;../../../rtl/fp_cores/altera;../../../rtl/fp_cores/fpnew/src;../../../rtl/fp_cores/fpnew/src/fpu_div_sqrt_mvp/hdl;../../../rtl/fp_cores/fpnew/src/common_cells/include;../../../rtl/fp_cores/fpnew/src/common_cells/src +FPU_INCLUDE = ../../../rtl/fp_cores;../../../rtl/fp_cores/altera/arria10;../../../rtl/fp_cores/fpnew/src;../../../rtl/fp_cores/fpnew/src/fpu_div_sqrt_mvp/hdl;../../../rtl/fp_cores/fpnew/src/common_cells/include;../../../rtl/fp_cores/fpnew/src/common_cells/src RTL_INCLUDE = $(FPU_INCLUDE);../../../rtl;../../../rtl/libs;../../../rtl/interfaces;../../../rtl/cache PROJECT_FILES = $(PROJECT).qpf $(PROJECT).qsf