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update

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This commit is contained in:
Blaise Tine
2020-06-28 21:49:15 -07:00
parent d89931d564
commit 24aabd49d1
1 changed files with 10 additions and 5 deletions
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9
hw/rtl/VX_gpr_ram.v
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@@ -19,16 +19,21 @@ module VX_gpr_ram (
wire [`NUM_THREADS-1:0] write_enable = writeback_if.valid & {`NUM_THREADS{write_ce && (writeback_if.wb != 0)}}; wire [`NUM_THREADS-1:0] write_enable = writeback_if.valid & {`NUM_THREADS{write_ce && (writeback_if.wb != 0)}};
`ifndef ASIC `ifndef ASIC
`UNUSED_VAR(reset)
reg [`NUM_THREADS-1:0][31:0] ram[31:0]; reg [`NUM_THREADS-1:0][31:0] ram[31:0];
`UNUSED_VAR(reset) wire [4:0] waddr = writeback_if.rd;
wire [`NUM_THREADS-1:0][31:0] wdata = writeback_if.data;
genvar i; genvar i;
for (i = 0; i < `NUM_THREADS; i++) begin for (i = 0; i < `NUM_THREADS; i++) begin
always @(posedge clk) begin always @(posedge clk) begin
if (write_enable[i]) begin if (write_enable[i]) begin
ram[writeback_if.rd][i] <= writeback_if.data[i]; ram[waddr][i][0] <= wdata[i][7:0];
ram[waddr][i][1] <= wdata[i][15:8];
ram[waddr][i][2] <= wdata[i][23:16];
ram[waddr][i][3] <= wdata[i][31:24];
end end
end end
end end