GPR back-end with mem

rtl/byte_enabled_simple_dual_port_ram.v

@@ -5,10 +5,10 @@
 module byte_enabled_simple_dual_port_ram
 (
 	input we, clk,
-	input wire[4:0] waddr, raddr1, raddr2,
+	input wire[4:0] waddr, raddr1,
 	input wire[`NT_M1:0] be,
 	input wire[`NT_M1:0][31:0] wdata,
-	output reg[`NT_M1:0][31:0] q1, q2
+	output reg[`NT_M1:0][31:0] q1
 );
 
 		// integer regi;
@@ -42,10 +42,9 @@ module byte_enabled_simple_dual_port_ram
 	end
 	
 	assign q1 = GPR[raddr1];
-	assign q2 = GPR[raddr2];
 
 
 	// assign q1 = (raddr1 == waddr && (we)) ? wdata : GPR[raddr1];
 	// assign q2 = (raddr2 == waddr && (we)) ? wdata : GPR[raddr2];
 
-endmodule
+endmodule