diff --git a/README.md b/README.md index 53f42736..cc6239fb 100644 --- a/README.md +++ b/README.md @@ -5,40 +5,41 @@ Vortex is a full-system RISCV-based GPGPU processor. -Specifications --------------- +## Specifications -- Support RISC-V RV32I ISA -- Fully scalable: 1 to 16 cores with optional L2 and L3 caches -- OpenCL 1.2 Support -- FPGA target: Intel Arria 10 @ 200 MHz peak Freq +- Support RISC-V RV32IMF ISA +- Scalability: 1 to 32 cores with optional L2 and L3 caches +- Software: OpenCL 1.2 Support +- Supported FPGAs: + - Intel Arria 10 + - Intel Stratix 10 -Directory structure -------------------- +## Directory structure -- benchmarks: OpenCL and RISC-V benchmarks - -- docs: [documentation](https://github.com/vortexgpgpu/vortex-dev/blob/master/doc/Vortex.md). +- `doc`: [Documentation](doc/Vortex.md). -- hw: hardware sources. +- `hw`: Hardware sources. -- driver: driver software. +- `driver`: Host driver software. -- runtime: runtime software for kernels. +- `runtime`: Kernel Runtime software. -- simX: Vortex cycle-approximate simulator. +- `simX`: Cycle-approximate simulator. -- evaluation: synthesis and performance data. +- `tests`: Tests repository. -Basic Installation ------------------- +- `ci`: Continuous integration scripts. -Install development tools +- `miscs`: Miscellaneous resources. + +## Basic Installation + +### Install development tools $ sudo apt-get install build-essential $ sudo apt-get install git -Install gnu-riscv-tools +### Install gnu-riscv-tools $ export RISCV_TOOLCHAIN_PATH=/opt/riscv-gnu-toolchain @@ -58,19 +59,17 @@ Install gnu-riscv-tools $ make -j`nproc` $ make -j`nproc` build-qemu -Install Verilator +### Install Verilator You need into build the latest version using the instructions on their website $ https://www.veripool.org/projects/verilator/wiki/Installing -Install Vortex +### Install Vortex $ git clone --recursive https://github.com/vortexgpgpu/vortex.git $ cd Vortex $ make -Quick Test running OpenCL vecadd program +### Quick Test running OpenCL vecadd sample on 2 cores - $ cd /Vortex/benchmarks/opencl/vecadd - $ make - $ make run-rtlsim + $ ./ci/blackbox.sh --cores=2 --app=vecadd diff --git a/ci/blackbox.sh b/ci/blackbox.sh index a2e5bb9b..4d1bbc3a 100755 --- a/ci/blackbox.sh +++ b/ci/blackbox.sh @@ -151,6 +151,10 @@ then OPTS=$ARGS make -C $APP_PATH run-$DRIVER > run.log 2>&1 else make -C $APP_PATH run-$DRIVER > run.log 2>&1 + + if [ -f "$APP_PATH/trace.vcd" ] + then + mv $APP_PATH/trace.vcd . fi else if [ $SCOPE -eq 1 ] diff --git a/doc/Codebase.md b/doc/Codebase.md deleted file mode 100644 index ae1f3d02..00000000 --- a/doc/Codebase.md +++ /dev/null @@ -1,34 +0,0 @@ -# Vortex Codebase - -The directory/file layout of the Vortex codebase is as followed: - -- `hw`: - - `unit_tests`: contains unit test for RTL of cache and queue - - `syn`: contains all synthesis scripts (quartus and yosys) - - `quartus`: contains synthesis scripts for Intel Quartus toolchain - - `opae`: contains synthesis scripts for Intel OPAE FPGA - - `simulate`: contains RTL simulator (verilator) - - `rtl`: contains rtl source code - - `cache`: contains cache subsystem code - - `fp_cores`: contains floating point unit code - - `interfaces`: contains code that handles communication for each of the units of the microarchitecture - - `libs`: contains general-purpose modules (i.e., buffers, encoders, arbiters, pipe registers) -- `driver`: contains driver software implementation (software that is run on the host to communicate with the vortex processor) - - `include`: contains vortex.h which has the vortex API that is used by the drivers - - `opae`: contains code for driver that runs on FPGA - - `rtlsim`: contains code for driver that runs on local machine (driver built using verilator which converts rtl to c++ binary) - - `simx`: contains code for driver that runs on local machine (vortex) -- `runtime`: contains software used inside kernel programs to expose GPGPU capabilities - - `include`: contains vortex API needed for runtime - - `linker`: contains linker file for compiling kernels - - `src`: contains implementation of vortex API (from include folder) -- `simX`: contains simX, the cycle approximate simulator for vortex - - `tests`: contains tests suite - - `runtime`: contains vortex runtime tests - - `driver`: contains vortex driver tests - - `opencl`: contains opencl tests and benchmarks - - `riscv`: contains official riscv tests - - `regression`: contains regression tests - - `vector`: tests for vector instructions (not yet implemented) - - `ci`: contain tests to be run during continuous integration (Travis CI) - - `miscs`: contains miscellaneous stuffs \ No newline at end of file diff --git a/doc/Vortex.md b/doc/Vortex.md index 6ae8881e..2ff5511c 100644 --- a/doc/Vortex.md +++ b/doc/Vortex.md @@ -1,26 +1,24 @@ # Vortex Documentation -### Table of Contents +## Table of Contents -- [Vortex Codebase Layout](https://github.com/vortexgpgpu/vortex-dev/blob/master/doc/Codebase.md) -- [Vortex Microarchitecture and Extended RISC-V ISA](https://github.com/vortexgpgpu/vortex-dev/blob/master/doc/Microarchitecture.md) -- [Vortex Cache Subsystem](https://github.com/vortexgpgpu/vortex-dev/blob/master/doc/Cache_Subsystem.md) -- Vortex Software -- [Vortex Simulation](https://github.com/vortexgpgpu/vortex-dev/blob/master/doc/Simulation.md) -- [FPGA Configuration, Program and Test](https://github.com/vortexgpgpu/vortex-dev/blob/master/doc/FPGA_Startup_Guide.md) -- Debugging -- Useful Links +- [Codebase Layout](codebase.md) +- [Microarchitecture](microarchitecture.md) +- [Cache Subsystem](cache_subsystem.md) +- [Software](software.md) +- [Simulation](simulation.md) +- [FPGA Setup Guide](fpga_setup.md) +- [Debugging](debugging.md) +- [Useful Links](references.md) -### Quick Start -Setup Vortex environment: -``` -$ export RISCV_TOOLCHAIN_PATH=/opt/riscv-gnu-toolchain -$ export PATH=:/opt/verilator/bin:$PATH -$ export VERILATOR_ROOT=/opt/verilator -``` +## Installation -Test Vortex with different drivers and configurations: +- Refer to the install instructions in [README](../README.md). + +## Quick Start Scenarios + +Running Vortex simulators with different configurations: - Run basic driver test with rtlsim driver and Vortex config of 2 clusters, 2 cores, 2 warps, 4 threads $ ./ci/blackbox.sh --clusters=2 --cores=2 --warps=2 --threads=4 --driver=rtlsim --app=basic diff --git a/doc/Cache_Subsystem.md b/doc/cache_subsystem.md similarity index 92% rename from doc/Cache_Subsystem.md rename to doc/cache_subsystem.md index 9de9aef7..41d2fad6 100644 --- a/doc/Cache_Subsystem.md +++ b/doc/cache_subsystem.md @@ -8,7 +8,7 @@ The Vortex Cache Sub-system has the following main properties: ### Cache Hierarchy -![Image of Cache Hierarchy](./Images/cache_hierarchy.png) +![Image of Cache Hierarchy](./images/cache_hierarchy.png) - Cache can be configured to be any level in the hierarchy - Caches communicate via snooping @@ -18,7 +18,7 @@ The Vortex Cache Sub-system has the following main properties: VX.cache.v is the top module of the cache verilog code located in the `/hw/rtl/cache` directory. -![Image of Vortex Cache](./Images/vortex_cache_top_module.png) +![Image of Vortex Cache](./images/vortex_cache_top_module.png) - Configurable (Cache size, number of banks, bank line size, etc.) - I/O signals @@ -44,7 +44,7 @@ VX.cache.v is the top module of the cache verilog code located in the `/hw/rtl/c VX_bank.v is the verilog code that handles cache bank functionality and is located in the `/hw/rtl/cache` directory. -![Image of Vortex Cache Bank](./Images/vortex_bank.png) +![Image of Vortex Cache Bank](./images/vortex_bank.png) - Allows for high throughput​ - Each bank contains queues to hold requests to the cache​ diff --git a/doc/codebase.md b/doc/codebase.md new file mode 100644 index 00000000..4f4db1fc --- /dev/null +++ b/doc/codebase.md @@ -0,0 +1,35 @@ +# Vortex Codebase + +The directory/file layout of the Vortex codebase is as followed: + +- `hw`: + - `rtl`: hardware rtl sources + - `cache`: cache subsystem code + - `fp_cores`: floating point unit code + - `interfaces`: interfaces for inter-module communication + - `libs`: general-purpose modules (i.e., encoder, arbiter, ...) + - `syn`: synthesis directory + - `opae`: OPAE synthesis scripts + - `quartus`: Quartus synthesis scripts + - `synopsys`: Synopsys synthesis scripts + - `yosys`: Yosys synthesis scripts + - `simulate`: baseline RTL simulator (used by RTLSIM) + - `unit_tests`: unit tests for some hardware components +- `driver`: Host driver software + - `include`: Vortex driver public headers + - `opae`: software driver that uses Intel OPAE + - `vlsim`: software driver that simulates Full RTL (include AFU) + - `rtlsim`: software driver that simulates processor RTL + - `simx`: software driver that uses simX simulator +- `runtime`: Kernel runtime software + - `include`: Vortex runtime public headers + - `linker`: linker file for compiling kernels + - `src`: runtime implementation +- `simX`: cycle approximate simulator for vortex +- `tests`: tests repository. + - `runtime`: runtime tests + - `regression`: regression tests + - `riscv`: RISC-V standard tests + - `opencl`: opencl benchmarks and tests +- `ci`: continuous integration scripts +- `miscs`: miscellaneous resources. diff --git a/doc/FPGA_Startup_Guide.md b/doc/fpga_setup.md similarity index 100% rename from doc/FPGA_Startup_Guide.md rename to doc/fpga_setup.md diff --git a/doc/Images/cache_hierarchy.png b/doc/images/cache_hierarchy.png similarity index 100% rename from doc/Images/cache_hierarchy.png rename to doc/images/cache_hierarchy.png diff --git a/doc/Images/vortex_bank.png b/doc/images/vortex_bank.png similarity index 100% rename from doc/Images/vortex_bank.png rename to doc/images/vortex_bank.png diff --git a/doc/Images/vortex_cache_top_module.png b/doc/images/vortex_cache_top_module.png similarity index 100% rename from doc/Images/vortex_cache_top_module.png rename to doc/images/vortex_cache_top_module.png diff --git a/doc/Images/vortex_microarchitecture_v2.png b/doc/images/vortex_microarchitecture_v2.png similarity index 100% rename from doc/Images/vortex_microarchitecture_v2.png rename to doc/images/vortex_microarchitecture_v2.png diff --git a/doc/Microarchitecture.md b/doc/microarchitecture.md similarity index 98% rename from doc/Microarchitecture.md rename to doc/microarchitecture.md index 1b410066..7e7a6a59 100644 --- a/doc/Microarchitecture.md +++ b/doc/microarchitecture.md @@ -32,7 +32,7 @@ Vortex uses the SIMT (Single Instruction, Multiple Threads) execution model with ### Vortex Pipeline/Datapath -![Image of Vortex Microarchitecture](./Images/vortex_microarchitecture_v2.png) +![Image of Vortex Microarchitecture](./images/vortex_microarchitecture_v2.png) Vortex has a 5-stage pipeline: FI | ID | Issue | EX | WB. diff --git a/doc/Simulation.md b/doc/simulation.md similarity index 100% rename from doc/Simulation.md rename to doc/simulation.md diff --git a/driver/simx/Makefile b/driver/simx/Makefile index c33fc242..1a7cf33e 100644 --- a/driver/simx/Makefile +++ b/driver/simx/Makefile @@ -17,15 +17,11 @@ CXXFLAGS += -DDUMP_PERF_STATS LDFLAGS += -shared -pthread #LDFLAGS += -dynamiclib -pthread -DBG_FLAGS += -DDEBUG_LEVEL=3 - SRCS = vortex.cpp ../common/vx_utils.cpp SRCS += $(SIMX_DIR)/util.cpp $(SIMX_DIR)/args.cpp $(SIMX_DIR)/mem.cpp $(SIMX_DIR)/pipeline.cpp $(SIMX_DIR)/warp.cpp $(SIMX_DIR)/core.cpp $(SIMX_DIR)/decode.cpp $(SIMX_DIR)/execute.cpp # Debugigng -ifdef DEBUG - CXXFLAGS += $(DBG_FLAGS) -else +ifndef DEBUG CXXFLAGS += -DNDEBUG endif