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minor update

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This commit is contained in:
Blaise Tine
2020-06-28 22:58:18 -07:00
parent 97668bf6f6
commit 21e04a0cb0
6 changed files with 8 additions and 8 deletions
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6
hw/rtl/VX_gpr_ram.v
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@@ -21,7 +21,7 @@ module VX_gpr_ram (
`ifndef ASIC
`UNUSED_VAR(reset)
reg [`NUM_THREADS-1:0][31:0] ram[31:0];
reg [`NUM_THREADS-1:0][3:0][7:0] ram[31:0];
wire [4:0] waddr = writeback_if.rd;
wire [`NUM_THREADS-1:0][31:0] wdata = writeback_if.data;
@@ -30,8 +30,8 @@ module VX_gpr_ram (
for (i = 0; i < `NUM_THREADS; i++) begin
always @(posedge clk) begin
if (write_enable[i]) begin
ram[waddr][i][0] <= wdata[i][7:0];
ram[waddr][i][1] <= wdata[i][15:8];
ram[waddr][i][0] <= wdata[i][07:00];
ram[waddr][i][1] <= wdata[i][15:08];
ram[waddr][i][2] <= wdata[i][23:16];
ram[waddr][i][3] <= wdata[i][31:24];
end

2
hw/rtl/libs/VX_generic_queue.v
View File

@@ -3,7 +3,7 @@
module VX_generic_queue #(
parameter DATAW,
parameter SIZE = 16,
parameter BUFFERED_OUTPUT = 1
parameter BUFFERED_OUTPUT = (SIZE > 8)
) (
input wire clk,
input wire reset,