From 21566cdcd7d2556a6581ca723a2f5253f5f55308 Mon Sep 17 00:00:00 2001
From: felsabbagh3 <felsabbagh3@gatech.edu>
Date: Sun, 28 Jun 2020 19:38:36 -0700
Subject: [PATCH] Fixed Single Core with Optimizations

---
 hw/rtl/VX_lsu_unit.v                   | 4 ++--
 hw/rtl/cache/VX_cache_core_rsp_merge.v | 8 ++++----
 hw/rtl/libs/VX_fair_arbiter.v          | 5 +++--
 3 files changed, 9 insertions(+), 8 deletions(-)

diff --git a/hw/rtl/VX_lsu_unit.v b/hw/rtl/VX_lsu_unit.v
index 573a4b32..1622facf 100644
--- a/hw/rtl/VX_lsu_unit.v
+++ b/hw/rtl/VX_lsu_unit.v
@@ -21,7 +21,7 @@ module VX_lsu_unit #(
     output wire             delay
 );
 
-    VX_wb_if                mem_wb_if;
+    VX_wb_if                mem_wb_if();
 
     wire[`NUM_THREADS-1:0][31:0]    use_address;
     wire[`NUM_THREADS-1:0][31:0]    use_store_data;
@@ -159,7 +159,7 @@ module VX_lsu_unit #(
     assign mem_wb_if.data  = core_rsp_data;
 
     // Can't accept new response
-    assign dcache_rsp_if.core_rsp_ready = !no_slot_mem & (|mem_wb_if_p1.valid);
+    assign dcache_rsp_if.core_rsp_ready = !(no_slot_mem & (|mem_wb_if_p1.valid));
 
 
 
diff --git a/hw/rtl/cache/VX_cache_core_rsp_merge.v b/hw/rtl/cache/VX_cache_core_rsp_merge.v
index 26241ce5..2f835ce1 100644
--- a/hw/rtl/cache/VX_cache_core_rsp_merge.v
+++ b/hw/rtl/cache/VX_cache_core_rsp_merge.v
@@ -34,7 +34,7 @@ module VX_cache_core_rsp_merge #(
     assign per_bank_core_rsp_ready = per_bank_core_rsp_pop_unqual & {NUM_BANKS{core_rsp_ready}};
 
     wire [`BANK_BITS-1:0] main_bank_index;
-
+    wire                  grant_valid;
     VX_fair_arbiter #(
         .N(NUM_BANKS)
     ) sel_bank (
@@ -42,7 +42,7 @@ module VX_cache_core_rsp_merge #(
         .reset       (reset),
         .requests    (per_bank_core_rsp_valid),
         .grant_index (main_bank_index),
-        `UNUSED_PIN  (grant_valid),
+        .grant_valid (grant_valid),
         `UNUSED_PIN  (grant_onehot)
     );
 
@@ -54,7 +54,7 @@ module VX_cache_core_rsp_merge #(
             core_rsp_valid = 0;
             core_rsp_data = 0;
             for (i = 0; i < NUM_BANKS; i++) begin 
-                if (per_bank_core_rsp_valid[i]                
+                if (grant_valid &&  per_bank_core_rsp_valid[i]                
                  && (per_bank_core_rsp_tag[i][CORE_TAG_ID_BITS-1:0] == per_bank_core_rsp_tag[main_bank_index][CORE_TAG_ID_BITS-1:0])) begin            
                     core_rsp_valid[per_bank_core_rsp_tid[i]] = 1;     
                     core_rsp_data[per_bank_core_rsp_tid[i]]  = per_bank_core_rsp_data[i];
@@ -70,7 +70,7 @@ module VX_cache_core_rsp_merge #(
             core_rsp_data  = 0;
             core_rsp_tag   = 0;
             for (i = 0; i < NUM_BANKS; i++) begin 
-                if (per_bank_core_rsp_valid[i] 
+                if (grant_valid && per_bank_core_rsp_valid[i] 
                  && !core_rsp_valid[per_bank_core_rsp_tid[i]]                     
                  && ((main_bank_index == `BANK_BITS'(i)) 
                   || (per_bank_core_rsp_tid[i] != per_bank_core_rsp_tid[main_bank_index]))) begin            
diff --git a/hw/rtl/libs/VX_fair_arbiter.v b/hw/rtl/libs/VX_fair_arbiter.v
index a9c2571b..ca32a5fc 100644
--- a/hw/rtl/libs/VX_fair_arbiter.v
+++ b/hw/rtl/libs/VX_fair_arbiter.v
@@ -25,6 +25,7 @@ module VX_fair_arbiter #(
 
        reg  [N-1:0] requests_use;
        wire [N-1:0] update_value;
+       wire [N-1:0] late_value;
 
        wire         refill;
        wire [N-1:0] refill_value;
@@ -60,8 +61,8 @@ module VX_fair_arbiter #(
             grant_onehot_r[grant_index] = 1;
         end
         assign grant_onehot = grant_onehot_r;    
-       
-        assign update_value = (requests_use & ~grant_onehot_r) | ((refill_original ^ requests) & ~refill_original);
+        assign late_value   =  ((refill_original ^ requests) & ~refill_original);
+        assign update_value = (requests_use & ~grant_onehot_r) | late_value;
 
     end