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texunit partial update

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This commit is contained in:
Blaise Tine
2021-03-20 10:50:54 -04:00
parent 859877a00d
commit 20ae993e51
17 changed files with 194 additions and 223 deletions
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154
hw/rtl/tex_unit/VX_tex_unit.v
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@@ -19,22 +19,13 @@ module VX_tex_unit #(
VX_tex_rsp_if tex_rsp_if
);
localparam MEM_REQ_TAGW = `NW_BITS + 32 + 1 + `NR_BITS + `NTEX_BITS;
localparam REQ_TAG_WIDTH = `TEX_FORMAT_BITS + `NW_BITS + 32 + `NR_BITS + 1;
`UNUSED_PARAM (CORE_ID)
`UNUSED_VAR (reset)
wire rsp_valid;
wire [`NW_BITS-1:0] rsp_wid;
wire [`NUM_THREADS-1:0] rsp_tmask;
wire [31:0] rsp_PC;
wire [`NR_BITS-1:0] rsp_rd;
wire rsp_wb;
wire [`NUM_THREADS-1:0][31:0] rsp_data;
wire stall_in, stall_out;
reg [`TEX_ADDR_BITS-1:0] tex_addr [`NUM_TEX_UNITS-1: 0];
reg [`TEX_FMT_BITS-1:0] tex_format [`NUM_TEX_UNITS-1: 0];
reg [`TEX_FORMAT_BITS-1:0] tex_format [`NUM_TEX_UNITS-1: 0];
reg [`TEX_WIDTH_BITS-1:0] tex_width [`NUM_TEX_UNITS-1: 0];
reg [`TEX_HEIGHT_BITS-1:0] tex_height [`NUM_TEX_UNITS-1: 0];
reg [`TEX_STRIDE_BITS-1:0] tex_stride [`NUM_TEX_UNITS-1: 0];
@@ -58,14 +49,14 @@ module VX_tex_unit #(
end begin
if (tex_csr_if.write_enable) begin
case (tex_csr_if.write_addr)
`CSR_TEX_ADDR(i) : tex_addr[i] <= tex_csr_if.write_data;
`CSR_TEX_FORMAT(i) : tex_format[i] <= tex_csr_if.write_data;
`CSR_TEX_WIDTH(i) : tex_width[i] <= tex_csr_if.write_data;
`CSR_TEX_HEIGHT(i) : tex_height[i] <= tex_csr_if.write_data;
`CSR_TEX_STRIDE(i) : tex_stride[i] <= tex_csr_if.write_data;
`CSR_TEX_WRAP_U(i) : tex_wrap_u[i] <= tex_csr_if.write_data;
`CSR_TEX_WRAP_V(i) : tex_wrap_v[i] <= tex_csr_if.write_data;
`CSR_TEX_FILTER(i) : tex_filter[i] <= tex_csr_if.write_data;
`CSR_TEX_ADDR(i) : tex_addr[i] <= tex_csr_if.write_data[`TEX_ADDR_BITS-1:0];
`CSR_TEX_FORMAT(i) : tex_format[i] <= tex_csr_if.write_data[`TEX_FORMAT_BITS-1:0];
`CSR_TEX_WIDTH(i) : tex_width[i] <= tex_csr_if.write_data[`TEX_WIDTH_BITS-1:0];
`CSR_TEX_HEIGHT(i) : tex_height[i] <= tex_csr_if.write_data[`TEX_HEIGHT_BITS-1:0];
`CSR_TEX_STRIDE(i) : tex_stride[i] <= tex_csr_if.write_data[`TEX_STRIDE_BITS-1:0];
`CSR_TEX_WRAP_U(i) : tex_wrap_u[i] <= tex_csr_if.write_data[`TEX_WRAP_BITS-1:0];
`CSR_TEX_WRAP_V(i) : tex_wrap_v[i] <= tex_csr_if.write_data[`TEX_WRAP_BITS-1:0];
`CSR_TEX_FILTER(i) : tex_filter[i] <= tex_csr_if.write_data[`TEX_FILTER_BITS-1:0];
default:
assert(tex_csr_if.write_addr >= `CSR_TEX_BEGIN(0)
&& tex_csr_if.write_addr < `CSR_TEX_BEGIN(`CSR_TEX_STATES));
@@ -77,18 +68,23 @@ module VX_tex_unit #(
// address generation
wire [3:0] mem_req_valid;
wire [3:0][31:0] mem_req_addr;
wire [TAG_IN_WIDTH-1:0] mem_req_tag;
wire mem_req_valid;
wire [`NUM_THREADS-1:0] mem_req_tmask;
wire [`TEX_FILTER_BITS-1:0] mem_req_filter;
wire [`NUM_THREADS-1:0][3:0][31:0] mem_req_addr;
wire [REQ_TAG_WIDTH-1:0] mem_req_tag;
wire mem_req_ready;
wire mem_rsp_valid;
wire [3:0][31:0] mem_rsp_data;
wire [TAG_IN_WIDTH-1:0] mem_rsp_tag;
wire [`NUM_THREADS-1:0] mem_rsp_tmask;
wire [`TEX_FILTER_BITS-1:0] mem_rsp_filter;
wire [`NUM_THREADS-1:0][3:0][31:0] mem_rsp_data;
wire [REQ_TAG_WIDTH-1:0] mem_rsp_tag;
wire mem_rsp_ready;
VX_tex_addr_gen #(
.FRAC_BITS(20)
.FRAC_BITS (20),
.REQ_TAG_WIDTH (REQ_TAG_WIDTH)
) tex_addr_gen (
.clk (clk),
.reset (reset),
@@ -96,10 +92,11 @@ module VX_tex_unit #(
.valid_in (tex_req_if.valid),
.ready_in (tex_req_if.ready),
.req_tag ({tex_req_if.wid, tex_req_if.PC, tex_req_if.rd, tex_req_if.wb}),
.filter (tex_filter[tex_req_if.unit]),
.wrap_u (tex_wrap_ufilter[tex_req_if.unit]),
.wrap_u (tex_wrap_u[tex_req_if.unit]),
.wrap_v (tex_wrap_v[tex_req_if.unit]),
.req_tmask (tex_req_if.tmask),
.req_tag ({tex_format[tex_req_if.unit], tex_req_if.wid, tex_req_if.PC, tex_req_if.rd, tex_req_if.wb}),
.base_addr (tex_addr[tex_req_if.unit]),
.log2_stride (tex_stride[tex_req_if.unit]),
@@ -111,6 +108,8 @@ module VX_tex_unit #(
.lod (tex_req_if.lod),
.mem_req_valid (mem_req_valid),
.mem_req_tmask (mem_req_tmask),
.mem_req_filter (mem_req_filter),
.mem_req_tag (mem_req_tag),
.mem_req_addr (mem_req_addr),
.mem_req_ready (mem_req_ready)
@@ -120,7 +119,7 @@ module VX_tex_unit #(
VX_tex_memory #(
.CORE_ID (CORE_ID),
.REQ_TAG_WIDTH (MEM_REQ_TAGW)
.REQ_TAG_WIDTH (REQ_TAG_WIDTH)
) tex_memory (
.clk (clk),
.reset (reset),
@@ -130,77 +129,60 @@ module VX_tex_unit #(
.dcache_rsp_if (dcache_rsp_if),
// inputs
req_valid (mem_req_valid),
req_addr (mem_req_addr),
req_tag (mem_req_tag),
req_ready (mem_req_ready),
.req_valid (mem_req_valid),
.req_tmask (mem_req_tmask),
.req_filter(mem_req_filter),
.req_addr (mem_req_addr),
.req_tag (mem_req_tag),
.req_ready (mem_req_ready),
// outputs
rsp_valid (mem_rsp_valid),
rsp_texel (mem_rsp_data),
rsp_tag (mem_rsp_tag),
rsp_ready (mem_rsp_ready)
.rsp_valid (mem_rsp_valid),
.rsp_tmask (mem_rsp_tmask),
.rsp_filter(mem_rsp_filter),
.rsp_data (mem_rsp_data),
.rsp_tag (mem_rsp_tag),
.rsp_ready (mem_rsp_ready)
);
// apply sampler
wire [`TEX_FORMAT_BITS-1:0] rsp_format;
wire [`NW_BITS-1:0] rsp_wid;
wire [31:0] rsp_PC;
wire [`NR_BITS-1:0] rsp_rd;
wire rsp_wb;
assign {rsp_format, rsp_wid, rsp_PC, rsp_rd, rsp_wb} = mem_rsp_tag;
VX_tex_sampler #(
.CORE_ID (CORE_ID)
) tex_sampler (
.clk (clk),
.reset (reset)
.reset (reset),
// inputs
//.valid_in (mem_rsp_valid),
//.texel (mem_rsp_data),
//.req_wid (mem_rsp_tag),
//.req_PC (mem_rsp_tag),
//.format (mem_rsp_tag),
//.ready_in (mem_rsp_ready),
);
.req_valid (mem_rsp_valid),
.req_tmask (mem_rsp_tmask),
.req_texels (mem_rsp_data),
.req_filter (mem_rsp_filter),
.req_format (rsp_format),
.req_wid (rsp_wid),
.req_PC (rsp_PC),
.req_rd (rsp_rd),
.req_wb (rsp_wb),
.req_ready (mem_rsp_ready),
assign tex_req_if.ready = (& pt_addr_ready);
assign lsu_req_if.valid = (& pt_addr_valid);
assign lsu_req_if.wid = tex_req_if.wid;
assign lsu_req_if.tmask = tex_req_if.tmask;
assign lsu_req_if.PC = tex_req_if.PC;
assign lsu_req_if.rd = tex_req_if.rd;
assign lsu_req_if.wb = tex_req_if.wb;
assign lsu_req_if.offset = 32'h0000;
assign lsu_req_if.op_type = `OP_BITS'({1'b0, 3'b000}); //func3 for word load??
assign lsu_req_if.store_data = {`NUM_THREADS{32'h0000}};
// wait buffer for fragments / replace with cache/state fragment fifo for bilerp
// no filtering for point sampling -> directly from dcache to output response
assign rsp_valid = ld_commit_if.valid;
assign rsp_wid = ld_commit_if.wid;
assign rsp_tmask = ld_commit_if.tmask;
assign rsp_PC = ld_commit_if.PC;
assign rsp_rd = ld_commit_if.rd;
assign rsp_wb = ld_commit_if.wb;
assign rsp_data = ld_commit_if.data;
VX_pipe_register #(
.DATAW (1 + `NW_BITS + `NUM_THREADS + 32 + `NR_BITS + 1 + (`NUM_THREADS * 32)),
.RESETW (1)
) pipe_reg (
.clk (clk),
.reset (reset),
.enable (~stall_out),
.data_in ({rsp_valid, rsp_wid, rsp_tmask, rsp_PC, rsp_rd, rsp_wb, rsp_data}),
.data_out ({tex_rsp_if.valid, tex_rsp_if.wid, tex_rsp_if.tmask, tex_rsp_if.PC, tex_rsp_if.rd, tex_rsp_if.wb, tex_rsp_if.data})
);
// output
assign stall_out = ~tex_rsp_if.ready && tex_rsp_if.valid;
// can accept new request?
assign stall_in = stall_out;
assign ld_commit_if.ready = ~stall_in;
// outputs
.rsp_valid (tex_rsp_if.valid),
.rsp_wid (tex_rsp_if.wid),
.rsp_tmask (tex_rsp_if.tmask),
.rsp_PC (tex_rsp_if.PC),
.rsp_rd (tex_rsp_if.rd),
.rsp_wb (tex_rsp_if.wb),
.rsp_data (tex_rsp_if.data),
.rsp_ready (tex_rsp_if.ready)
);
`ifdef DBG_PRINT_TEX
always @(posedge clk) begin