From 20ae78f43441025e35ac46e0ad37d86c0ecc6dbf Mon Sep 17 00:00:00 2001 From: Blaise Tine Date: Tue, 21 Apr 2020 01:31:32 -0400 Subject: [PATCH] fix simX build --- hw/modelsim/vortex_tb.v | 2 +- hw/rtl/VX_csr_data.v | 2 +- hw/rtl/VX_define.vh | 2 +- hw/rtl/cache/VX_cache_config.vh | 2 +- hw/rtl/interfaces/VX_branch_rsp_if.v | 2 +- hw/rtl/interfaces/VX_csr_req_if.v | 2 +- hw/rtl/interfaces/VX_csr_wb_if.v | 2 +- hw/rtl/interfaces/VX_exec_unit_req_if.v | 2 +- hw/rtl/interfaces/VX_gpr_data_if.v | 2 +- hw/rtl/interfaces/VX_gpr_jal_if.v | 2 +- hw/rtl/interfaces/VX_gpr_read_if.v | 2 +- hw/rtl/interfaces/VX_gpu_inst_req_if.v | 2 +- hw/rtl/interfaces/VX_icache_rsp_if.v | 2 +- hw/rtl/interfaces/VX_inst_exec_wb_if.v | 2 +- hw/rtl/interfaces/VX_inst_mem_wb_if.v | 2 +- hw/rtl/interfaces/VX_inst_meta_if.v | 2 +- hw/rtl/interfaces/VX_jal_rsp_if.v | 2 +- hw/rtl/interfaces/VX_join_if.v | 2 +- hw/rtl/interfaces/VX_lsu_req_if.v | 2 +- hw/rtl/interfaces/VX_mw_wb_if.v | 2 +- hw/rtl/interfaces/VX_warp_ctl_if.v | 2 +- hw/rtl/interfaces/VX_wb_if.v | 2 +- hw/rtl/interfaces/VX_wstall_if.v | 2 +- hw/rtl/libs/VX_generic_priority_encoder.v | 16 ++---- hw/rtl/libs/VX_priority_encoder.v | 1 + hw/rtl/libs/VX_priority_encoder_w_mask.v | 2 + hw/rtl/pipe_regs/VX_d_e_reg.v | 2 +- hw/rtl/pipe_regs/VX_f_d_reg.v | 2 +- hw/rtl/pipe_regs/VX_i_d_reg.v | 2 +- simX/cache_simX.v | 38 +++++++------- simX/core.cpp | 62 +++++++++++------------ 31 files changed, 84 insertions(+), 87 deletions(-) diff --git a/hw/modelsim/vortex_tb.v b/hw/modelsim/vortex_tb.v index 03bd4b1e..56d821f8 100644 --- a/hw/modelsim/vortex_tb.v +++ b/hw/modelsim/vortex_tb.v @@ -1,4 +1,4 @@ -`include "../VX_define.vh" +`include "VX_define.vh" //`define NUM_BANKS 8 //`define NUM_WORDS_PER_BLOCK 4 diff --git a/hw/rtl/VX_csr_data.v b/hw/rtl/VX_csr_data.v index 237cc390..6d7cac1c 100644 --- a/hw/rtl/VX_csr_data.v +++ b/hw/rtl/VX_csr_data.v @@ -1,4 +1,4 @@ -`include "../VX_define.vh" +`include "VX_define.vh" module VX_csr_data ( input wire clk, // Clock diff --git a/hw/rtl/VX_define.vh b/hw/rtl/VX_define.vh index 75b6b7d0..980334e1 100644 --- a/hw/rtl/VX_define.vh +++ b/hw/rtl/VX_define.vh @@ -1,7 +1,7 @@ `ifndef VX_DEFINE `define VX_DEFINE -`include "./VX_config.vh" +`include "VX_config.vh" // `define QUEUE_FORCE_MLAB 1 // `define SYN 1 diff --git a/hw/rtl/cache/VX_cache_config.vh b/hw/rtl/cache/VX_cache_config.vh index fa0cf39e..5ebe24f5 100644 --- a/hw/rtl/cache/VX_cache_config.vh +++ b/hw/rtl/cache/VX_cache_config.vh @@ -1,7 +1,7 @@ `ifndef VX_CACHE_CONFIG `define VX_CACHE_CONFIG -`include "../VX_define.vh" +`include "VX_define.vh" // data tid rd wb warp_num read write `define MRVQ_METADATA_SIZE (`WORD_SIZE + `LOG2UP(NUM_REQUESTS) + 5 + 2 + (`NW_BITS) + 3 + 3) diff --git a/hw/rtl/interfaces/VX_branch_rsp_if.v b/hw/rtl/interfaces/VX_branch_rsp_if.v index 62d23d4e..8ce1234c 100644 --- a/hw/rtl/interfaces/VX_branch_rsp_if.v +++ b/hw/rtl/interfaces/VX_branch_rsp_if.v @@ -1,7 +1,7 @@ `ifndef VX_BRANCH_RSP `define VX_BRANCH_RSP -`include "../VX_define.vh" +`include "VX_define.vh" interface VX_branch_rsp_if (); diff --git a/hw/rtl/interfaces/VX_csr_req_if.v b/hw/rtl/interfaces/VX_csr_req_if.v index 162c8937..0a254bc7 100644 --- a/hw/rtl/interfaces/VX_csr_req_if.v +++ b/hw/rtl/interfaces/VX_csr_req_if.v @@ -1,7 +1,7 @@ `ifndef VX_CSR_REQ `define VX_CSR_REQ -`include "../VX_define.vh" +`include "VX_define.vh" interface VX_csr_req_if (); diff --git a/hw/rtl/interfaces/VX_csr_wb_if.v b/hw/rtl/interfaces/VX_csr_wb_if.v index 45df13d0..1fd61f25 100644 --- a/hw/rtl/interfaces/VX_csr_wb_if.v +++ b/hw/rtl/interfaces/VX_csr_wb_if.v @@ -1,7 +1,7 @@ `ifndef VX_CSR_WB_REQ `define VX_CSR_WB_REQ -`include "../VX_define.vh" +`include "VX_define.vh" interface VX_csr_wb_if (); diff --git a/hw/rtl/interfaces/VX_exec_unit_req_if.v b/hw/rtl/interfaces/VX_exec_unit_req_if.v index f588e41c..4db8d406 100644 --- a/hw/rtl/interfaces/VX_exec_unit_req_if.v +++ b/hw/rtl/interfaces/VX_exec_unit_req_if.v @@ -1,7 +1,7 @@ `ifndef VX_EXE_UNIT_REQ_INTER `define VX_EXE_UNIT_REQ_INTER -`include "../VX_define.vh" +`include "VX_define.vh" interface VX_exec_unit_req_if (); diff --git a/hw/rtl/interfaces/VX_gpr_data_if.v b/hw/rtl/interfaces/VX_gpr_data_if.v index 622f54a5..084a06d2 100644 --- a/hw/rtl/interfaces/VX_gpr_data_if.v +++ b/hw/rtl/interfaces/VX_gpr_data_if.v @@ -2,7 +2,7 @@ `ifndef VX_gpr_data_INTER `define VX_gpr_data_INTER -`include "../VX_define.vh" +`include "VX_define.vh" interface VX_gpr_data_if (); diff --git a/hw/rtl/interfaces/VX_gpr_jal_if.v b/hw/rtl/interfaces/VX_gpr_jal_if.v index 17f68359..4f108895 100644 --- a/hw/rtl/interfaces/VX_gpr_jal_if.v +++ b/hw/rtl/interfaces/VX_gpr_jal_if.v @@ -1,7 +1,7 @@ `ifndef VX_GPR_JAL_INTER `define VX_GPR_JAL_INTER -`include "../VX_define.vh" +`include "VX_define.vh" interface VX_gpr_jal_if (); diff --git a/hw/rtl/interfaces/VX_gpr_read_if.v b/hw/rtl/interfaces/VX_gpr_read_if.v index c5796c45..073720da 100644 --- a/hw/rtl/interfaces/VX_gpr_read_if.v +++ b/hw/rtl/interfaces/VX_gpr_read_if.v @@ -1,7 +1,7 @@ `ifndef VX_GPR_READ `define VX_GPR_READ -`include "../VX_define.vh" +`include "VX_define.vh" interface VX_gpr_read_if (); diff --git a/hw/rtl/interfaces/VX_gpu_inst_req_if.v b/hw/rtl/interfaces/VX_gpu_inst_req_if.v index a394b12d..33be1482 100644 --- a/hw/rtl/interfaces/VX_gpu_inst_req_if.v +++ b/hw/rtl/interfaces/VX_gpu_inst_req_if.v @@ -1,7 +1,7 @@ `ifndef VX_GPU_INST_REQ_IN `define VX_GPU_INST_REQ_IN -`include "../VX_define.vh" +`include "VX_define.vh" interface VX_gpu_inst_req_if(); diff --git a/hw/rtl/interfaces/VX_icache_rsp_if.v b/hw/rtl/interfaces/VX_icache_rsp_if.v index d4bd7a41..1bd49010 100644 --- a/hw/rtl/interfaces/VX_icache_rsp_if.v +++ b/hw/rtl/interfaces/VX_icache_rsp_if.v @@ -1,7 +1,7 @@ `ifndef VX_ICACHE_RSP `define VX_ICACHE_RSP -`include "../VX_define.vh" +`include "VX_define.vh" interface VX_icache_rsp_if (); diff --git a/hw/rtl/interfaces/VX_inst_exec_wb_if.v b/hw/rtl/interfaces/VX_inst_exec_wb_if.v index 47581879..dae7aac9 100644 --- a/hw/rtl/interfaces/VX_inst_exec_wb_if.v +++ b/hw/rtl/interfaces/VX_inst_exec_wb_if.v @@ -2,7 +2,7 @@ `ifndef VX_EXEC_UNIT_WB_INST_INTER `define VX_EXEC_UNIT_WB_INST_INTER -`include "../VX_define.vh" +`include "VX_define.vh" interface VX_inst_exec_wb_if (); diff --git a/hw/rtl/interfaces/VX_inst_mem_wb_if.v b/hw/rtl/interfaces/VX_inst_mem_wb_if.v index ed30b3cf..a0969584 100644 --- a/hw/rtl/interfaces/VX_inst_mem_wb_if.v +++ b/hw/rtl/interfaces/VX_inst_mem_wb_if.v @@ -2,7 +2,7 @@ `ifndef VX_MEM_WB_INST_INTER `define VX_MEM_WB_INST_INTER -`include "../VX_define.vh" +`include "VX_define.vh" interface VX_inst_mem_wb_if (); diff --git a/hw/rtl/interfaces/VX_inst_meta_if.v b/hw/rtl/interfaces/VX_inst_meta_if.v index f925a3be..138369fe 100644 --- a/hw/rtl/interfaces/VX_inst_meta_if.v +++ b/hw/rtl/interfaces/VX_inst_meta_if.v @@ -1,7 +1,7 @@ `ifndef VX_F_D_INTER `define VX_F_D_INTER -`include "../VX_define.vh" +`include "VX_define.vh" interface VX_inst_meta_if (); diff --git a/hw/rtl/interfaces/VX_jal_rsp_if.v b/hw/rtl/interfaces/VX_jal_rsp_if.v index 1a796777..7eb8a17b 100644 --- a/hw/rtl/interfaces/VX_jal_rsp_if.v +++ b/hw/rtl/interfaces/VX_jal_rsp_if.v @@ -2,7 +2,7 @@ `ifndef VX_JAL_RSP `define VX_JAL_RSP -`include "../VX_define.vh" +`include "VX_define.vh" interface VX_jal_rsp_if (); diff --git a/hw/rtl/interfaces/VX_join_if.v b/hw/rtl/interfaces/VX_join_if.v index fa712bd1..9c89ffec 100644 --- a/hw/rtl/interfaces/VX_join_if.v +++ b/hw/rtl/interfaces/VX_join_if.v @@ -2,7 +2,7 @@ `ifndef VX_JOIN_INTER `define VX_JOIN_INTER -`include "../VX_define.vh" +`include "VX_define.vh" interface VX_join_if (); diff --git a/hw/rtl/interfaces/VX_lsu_req_if.v b/hw/rtl/interfaces/VX_lsu_req_if.v index 9db222ad..30074e06 100644 --- a/hw/rtl/interfaces/VX_lsu_req_if.v +++ b/hw/rtl/interfaces/VX_lsu_req_if.v @@ -2,7 +2,7 @@ `ifndef VX_LSU_REQ_INTER `define VX_LSU_REQ_INTER -`include "../VX_define.vh" +`include "VX_define.vh" interface VX_lsu_req_if (); diff --git a/hw/rtl/interfaces/VX_mw_wb_if.v b/hw/rtl/interfaces/VX_mw_wb_if.v index a0d3f5ea..6afbe580 100644 --- a/hw/rtl/interfaces/VX_mw_wb_if.v +++ b/hw/rtl/interfaces/VX_mw_wb_if.v @@ -2,7 +2,7 @@ `ifndef VX_MW_WB_INTER `define VX_MW_WB_INTER -`include "../VX_define.vh" +`include "VX_define.vh" interface VX_mw_wb_if (); diff --git a/hw/rtl/interfaces/VX_warp_ctl_if.v b/hw/rtl/interfaces/VX_warp_ctl_if.v index 254e0a90..14c43f50 100644 --- a/hw/rtl/interfaces/VX_warp_ctl_if.v +++ b/hw/rtl/interfaces/VX_warp_ctl_if.v @@ -2,7 +2,7 @@ `ifndef VX_WARP_CTL_INTER `define VX_WARP_CTL_INTER -`include "../VX_define.vh" +`include "VX_define.vh" interface VX_warp_ctl_if (); diff --git a/hw/rtl/interfaces/VX_wb_if.v b/hw/rtl/interfaces/VX_wb_if.v index a87ee192..6f20e3d4 100644 --- a/hw/rtl/interfaces/VX_wb_if.v +++ b/hw/rtl/interfaces/VX_wb_if.v @@ -1,7 +1,7 @@ `ifndef VX_WB_INTER `define VX_WB_INTER -`include "../VX_define.vh" +`include "VX_define.vh" interface VX_wb_if (); diff --git a/hw/rtl/interfaces/VX_wstall_if.v b/hw/rtl/interfaces/VX_wstall_if.v index b981cd91..cad6c1c9 100644 --- a/hw/rtl/interfaces/VX_wstall_if.v +++ b/hw/rtl/interfaces/VX_wstall_if.v @@ -1,7 +1,7 @@ `ifndef VX_WSTALL_INTER `define VX_WSTALL_INTER -`include "../VX_define.vh" +`include "VX_define.vh" interface VX_wstall_if(); diff --git a/hw/rtl/libs/VX_generic_priority_encoder.v b/hw/rtl/libs/VX_generic_priority_encoder.v index fb852564..35007e70 100644 --- a/hw/rtl/libs/VX_generic_priority_encoder.v +++ b/hw/rtl/libs/VX_generic_priority_encoder.v @@ -1,13 +1,8 @@ -`ifndef VX_GENERIC_PRIORITY_ENCODER -`define VX_GENERIC_PRIORITY_ENCODER - `include "VX_define.vh" -module VX_generic_priority_encoder - #( - parameter N = 1 - ) - ( +module VX_generic_priority_encoder #( + parameter N = 1 +) ( input wire[N-1:0] valids, //output reg[$clog2(N)-1:0] index, output reg[(`LOG2UP(N))-1:0] index, @@ -27,6 +22,5 @@ module VX_generic_priority_encoder end end end -endmodule - -`endif \ No newline at end of file + +endmodule \ No newline at end of file diff --git a/hw/rtl/libs/VX_priority_encoder.v b/hw/rtl/libs/VX_priority_encoder.v index b6e04433..17b9d679 100644 --- a/hw/rtl/libs/VX_priority_encoder.v +++ b/hw/rtl/libs/VX_priority_encoder.v @@ -17,4 +17,5 @@ module VX_priority_encoder ( end end end + endmodule \ No newline at end of file diff --git a/hw/rtl/libs/VX_priority_encoder_w_mask.v b/hw/rtl/libs/VX_priority_encoder_w_mask.v index d6a2405c..bd7e6abb 100644 --- a/hw/rtl/libs/VX_priority_encoder_w_mask.v +++ b/hw/rtl/libs/VX_priority_encoder_w_mask.v @@ -1,4 +1,5 @@ `include "VX_define.vh" + module VX_priority_encoder_w_mask #( parameter N = 10 ) ( @@ -27,4 +28,5 @@ module VX_priority_encoder_w_mask #( end assign mask = found ? (1 << index) : 0; + endmodule \ No newline at end of file diff --git a/hw/rtl/pipe_regs/VX_d_e_reg.v b/hw/rtl/pipe_regs/VX_d_e_reg.v index 4c3018cf..4f187843 100644 --- a/hw/rtl/pipe_regs/VX_d_e_reg.v +++ b/hw/rtl/pipe_regs/VX_d_e_reg.v @@ -1,4 +1,4 @@ -`include "../VX_define.vh" +`include "VX_define.vh" module VX_d_e_reg ( input wire clk, diff --git a/hw/rtl/pipe_regs/VX_f_d_reg.v b/hw/rtl/pipe_regs/VX_f_d_reg.v index 166254cb..21bc0343 100644 --- a/hw/rtl/pipe_regs/VX_f_d_reg.v +++ b/hw/rtl/pipe_regs/VX_f_d_reg.v @@ -1,4 +1,4 @@ -`include "../VX_define.vh" +`include "VX_define.vh" module VX_f_d_reg ( input wire clk, diff --git a/hw/rtl/pipe_regs/VX_i_d_reg.v b/hw/rtl/pipe_regs/VX_i_d_reg.v index ce0e650c..9a9c1317 100644 --- a/hw/rtl/pipe_regs/VX_i_d_reg.v +++ b/hw/rtl/pipe_regs/VX_i_d_reg.v @@ -1,4 +1,4 @@ -`include "../VX_define.vh" +`include "VX_define.vh" module VX_i_d_reg ( input wire clk, diff --git a/simX/cache_simX.v b/simX/cache_simX.v index dd343fdb..a00613e3 100644 --- a/simX/cache_simX.v +++ b/simX/cache_simX.v @@ -1,11 +1,11 @@ -`include "VX_define.vh" +`include "VX_define.v" module cache_simX ( input wire clk, // Clock input wire reset, // Icache - input wire[31:0] cache_pc_addr, + input wire[31:0] icache_pc_addr, input wire icache_valid_pc_addr, output wire icache_stall, @@ -18,17 +18,17 @@ module cache_simX ( ); //////////////////// ICACHE /////////////////// - VX_icache_request_if VX_icache_req; - assign VX_icache_req.pc_address = cache_pc_addr; - assign VX_icache_req.cache_driver_in_mem_read_o = (icache_valid_pc_addr) ? `LW_MEM_READ : `NO_MEM_READ; - assign VX_icache_req.cache_driver_in_mem_write_o = `NO_MEM_WRITE; - assign VX_icache_req.cache_driver_in_valid_o = icache_valid_pc_addr; - assign VX_icache_req.cache_driver_in_data_o = 0; + VX_icache_request_inter VX_icache_req; + assign VX_icache_req.pc_address = icache_pc_addr; + assign VX_icache_req.out_cache_driver_in_mem_read = (icache_valid_pc_addr) ? `LW_MEM_READ : `NO_MEM_READ; + assign VX_icache_req.out_cache_driver_in_mem_write = `NO_MEM_WRITE; + assign VX_icache_req.out_cache_driver_in_valid = icache_valid_pc_addr; + assign VX_icache_req.out_cache_driver_in_data = 0; - VX_icache_rsp_if VX_icache_rsp; + VX_icache_response_inter VX_icache_rsp; assign icache_stall = VX_icache_rsp.delay; - VX_dram_req_rsp_if #( + VX_dram_req_rsp_inter #( .NUMBER_BANKS(`ICACHE_BANKS), .NUM_WORDS_PER_BLOCK(`ICACHE_NUM_WORDS_PER_BLOCK) @@ -41,22 +41,22 @@ module cache_simX ( //////////////////// DCACHE /////////////////// - VX_dcache_request_if VX_dcache_req; - assign VX_dcache_req.cache_driver_in_mem_read_o = dcache_mem_read; - assign VX_dcache_req.cache_driver_in_mem_write_o = dcache_mem_write; - assign VX_dcache_req.cache_driver_in_data_o = 0; + VX_dcache_request_inter VX_dcache_req; + assign VX_dcache_req.out_cache_driver_in_mem_read = dcache_mem_read; + assign VX_dcache_req.out_cache_driver_in_mem_write = dcache_mem_write; + assign VX_dcache_req.out_cache_driver_in_data = 0; genvar curr_t; for (curr_t = 0; curr_t < `NT; curr_t=curr_t+1) begin - assign VX_dcache_req.cache_driver_in_address_o[curr_t] = dcache_in_addr[curr_t]; - assign VX_dcache_req.cache_driver_in_valid_o[curr_t] = dcache_in_valid[curr_t]; + assign VX_dcache_req.out_cache_driver_in_address[curr_t] = dcache_in_addr[curr_t]; + assign VX_dcache_req.out_cache_driver_in_valid[curr_t] = dcache_in_valid[curr_t]; end - VX_dcache_response_if VX_dcache_rsp; + VX_dcache_response_inter VX_dcache_rsp; assign dcache_stall = VX_dcache_rsp.delay; - VX_dram_req_rsp_if #( + VX_dram_req_rsp_inter #( .NUMBER_BANKS(`DCACHE_BANKS), .NUM_WORDS_PER_BLOCK(`DCACHE_NUM_WORDS_PER_BLOCK) @@ -66,7 +66,7 @@ module cache_simX ( reg dcache_i_m_ready; assign VX_dram_req_rsp.i_m_ready = dcache_i_m_ready; - VX_dmem_ctrl dmem_controller ( + VX_dmem_controller dmem_ctrl ( .clk (clk), .reset (reset), .VX_dram_req_rsp (VX_dram_req_rsp), diff --git a/simX/core.cpp b/simX/core.cpp index bc4a5ffa..efd7cdb3 100644 --- a/simX/core.cpp +++ b/simX/core.cpp @@ -255,16 +255,16 @@ void Core::getCacheDelays(trace_inst_t * trace_inst) cache_simulator->eval(); // m_trace->dump(2*curr_cycle); - cache_simulator->in_icache_pc_addr = trace_inst->pc; - cache_simulator->in_icache_valid_pc_addr = 1; + cache_simulator->icache_pc_addr = trace_inst->pc; + cache_simulator->icache_valid_pc_addr = 1; // DCache start - cache_simulator->in_dcache_mem_read = in_dcache_mem_read; - cache_simulator->in_dcache_mem_write = in_dcache_mem_write; + cache_simulator->dcache_mem_read = in_dcache_mem_read; + cache_simulator->dcache_mem_write = in_dcache_mem_write; for (int cur_t = 0; cur_t < a.getNThds(); cur_t++) { - cache_simulator->in_dcache_in_valid[cur_t] = in_dcache_in_valid[cur_t]; - cache_simulator->in_dcache_in_address[cur_t] = in_dcache_in_address[cur_t]; + cache_simulator->dcache_in_valid[cur_t] = in_dcache_in_valid[cur_t]; + cache_simulator->dcache_in_addr[cur_t] = in_dcache_in_address[cur_t]; } // DCache end cache_simulator->clk = 0; @@ -273,39 +273,39 @@ void Core::getCacheDelays(trace_inst_t * trace_inst) curr_cycle++; - while((cache_simulator->out_icache_stall || cache_simulator->out_dcache_stall)) + while((cache_simulator->icache_stall || cache_simulator->dcache_stall)) { ////////// Feed input - if (cache_simulator->out_icache_stall) + if (cache_simulator->icache_stall) { - cache_simulator->in_icache_pc_addr = trace_inst->pc; - cache_simulator->in_icache_valid_pc_addr = 1; + cache_simulator->icache_pc_addr = trace_inst->pc; + cache_simulator->icache_valid_pc_addr = 1; trace_inst->fetch_stall_cycles++; } else { - cache_simulator->in_icache_valid_pc_addr = 0; + cache_simulator->icache_valid_pc_addr = 0; } - if (cache_simulator->out_dcache_stall) + if (cache_simulator->dcache_stall) { - cache_simulator->in_dcache_mem_read = in_dcache_mem_read; - cache_simulator->in_dcache_mem_write = in_dcache_mem_write; + cache_simulator->dcache_mem_read = in_dcache_mem_read; + cache_simulator->dcache_mem_write = in_dcache_mem_write; for (int cur_t = 0; cur_t < a.getNThds(); cur_t++) { - cache_simulator->in_dcache_in_valid[cur_t] = in_dcache_in_valid[cur_t]; - cache_simulator->in_dcache_in_address[cur_t] = in_dcache_in_address[cur_t]; + cache_simulator->dcache_in_valid[cur_t] = in_dcache_in_valid[cur_t]; + cache_simulator->dcache_in_addr[cur_t] = in_dcache_in_address[cur_t]; } trace_inst->mem_stall_cycles++; } else { - cache_simulator->in_dcache_mem_read = NO_MEM_READ; - cache_simulator->in_dcache_mem_write = NO_MEM_WRITE; + cache_simulator->dcache_mem_read = NO_MEM_READ; + cache_simulator->dcache_mem_write = NO_MEM_WRITE; for (int cur_t = 0; cur_t < a.getNThds(); cur_t++) { - cache_simulator->in_dcache_in_valid[cur_t] = 0; + cache_simulator->dcache_in_valid[cur_t] = 0; } } @@ -314,33 +314,33 @@ void Core::getCacheDelays(trace_inst_t * trace_inst) // m_trace->dump(2*curr_cycle); //////// Feed input - if (cache_simulator->out_icache_stall) + if (cache_simulator->icache_stall) { - cache_simulator->in_icache_pc_addr = trace_inst->pc; - cache_simulator->in_icache_valid_pc_addr = 1; + cache_simulator->icache_pc_addr = trace_inst->pc; + cache_simulator->icache_valid_pc_addr = 1; } else { - cache_simulator->in_icache_valid_pc_addr = 0; + cache_simulator->icache_valid_pc_addr = 0; } - if (cache_simulator->out_dcache_stall) + if (cache_simulator->dcache_stall) { - cache_simulator->in_dcache_mem_read = in_dcache_mem_read; - cache_simulator->in_dcache_mem_write = in_dcache_mem_write; + cache_simulator->dcache_mem_read = in_dcache_mem_read; + cache_simulator->dcache_mem_write = in_dcache_mem_write; for (int cur_t = 0; cur_t < a.getNThds(); cur_t++) { - cache_simulator->in_dcache_in_valid[cur_t] = in_dcache_in_valid[cur_t]; - cache_simulator->in_dcache_in_address[cur_t] = in_dcache_in_address[cur_t]; + cache_simulator->dcache_in_valid[cur_t] = in_dcache_in_valid[cur_t]; + cache_simulator->dcache_in_addr[cur_t] = in_dcache_in_address[cur_t]; } } else { - cache_simulator->in_dcache_mem_read = NO_MEM_READ; - cache_simulator->in_dcache_mem_write = NO_MEM_WRITE; + cache_simulator->dcache_mem_read = NO_MEM_READ; + cache_simulator->dcache_mem_write = NO_MEM_WRITE; for (int cur_t = 0; cur_t < a.getNThds(); cur_t++) { - cache_simulator->in_dcache_in_valid[cur_t] = 0; + cache_simulator->dcache_in_valid[cur_t] = 0; } }