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minor updates

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This commit is contained in:
Blaise Tine
2021-01-06 07:18:14 -08:00
parent 31ff70fd4e
commit 2058718f0f
13 changed files with 263 additions and 47 deletions
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6
hw/rtl/cache/VX_bank.v vendored
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@@ -110,7 +110,8 @@ module VX_bank #(
VX_input_queue #(
.DATAW ($bits(dram_rsp_data)),
.SIZE (DRSQ_SIZE)
.SIZE (DRSQ_SIZE),
.FASTRAM (1)
) dram_rsp_queue (
.clk (clk),
.reset (reset),
@@ -164,7 +165,8 @@ module VX_bank #(
VX_input_queue #(
.DATAW (CORE_TAG_WIDTH + `REQS_BITS + 1 + WORD_SIZE + `WORD_ADDR_WIDTH + `WORD_WIDTH),
.SIZE (CREQ_SIZE)
.SIZE (CREQ_SIZE),
.FASTRAM (1)
) core_req_queue (
.clk (clk),
.reset (reset),

14
hw/rtl/cache/VX_cache_core_req_bank_sel.v vendored
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@@ -2,18 +2,18 @@
module VX_cache_core_req_bank_sel #(
// Size of line inside a bank in bytes
parameter CACHE_LINE_SIZE= 1,
parameter CACHE_LINE_SIZE = 64,
// Size of a word in bytes
parameter WORD_SIZE = 1,
parameter WORD_SIZE = 4,
// Number of banks
parameter NUM_BANKS = 1,
parameter NUM_BANKS = 4,
// Number of Word requests per cycle
parameter NUM_REQS = 1,
parameter NUM_REQS = 4,
// core request tag size
parameter CORE_TAG_WIDTH = 1,
parameter CORE_TAG_WIDTH = 3,
// bank offset from beginning of index range
parameter BANK_ADDR_OFFSET = 0
parameter BANK_ADDR_OFFSET = 0
) (
input wire clk,
input wire reset,
@@ -62,7 +62,7 @@ module VX_cache_core_req_bank_sel #(
per_bank_core_req_addr_r = 'x;
per_bank_core_req_tag_r = 'x;
per_bank_core_req_data_r = 'x;
for (integer i = NUM_REQS-1; i >= 0; --i) begin
if (core_req_valid[i]) begin
per_bank_core_req_valid_r[core_req_bid[i]] = 1;

5
hw/rtl/cache/VX_input_queue.v vendored
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@@ -4,7 +4,8 @@ module VX_input_queue #(
parameter DATAW = 1,
parameter SIZE = 2,
parameter ADDRW = $clog2(SIZE),
parameter SIZEW = $clog2(SIZE+1)
parameter SIZEW = $clog2(SIZE+1),
parameter FASTRAM = 0
) (
input wire clk,
input wire reset,
@@ -97,7 +98,7 @@ module VX_input_queue #(
.SIZE(SIZE),
.BUFFERED(0),
.RWCHECK(1),
.FASTRAM(1)
.FASTRAM(FASTRAM)
) dp_ram (
.clk(clk),
.waddr(wr_ptr_r),

2
hw/rtl/cache/VX_miss_resrv.v vendored
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@@ -55,7 +55,7 @@ module VX_miss_resrv #(
// dequeue
input wire dequeue
);
`USE_FAST_BRAM reg [MSHR_SIZE-1:0][`LINE_ADDR_WIDTH-1:0] addr_table;
reg [MSHR_SIZE-1:0][`LINE_ADDR_WIDTH-1:0] addr_table;
reg [MSHR_SIZE-1:0] valid_table;
reg [MSHR_SIZE-1:0] ready_table;