minor updates

hw/rtl/VX_databus_arb.v

@@ -69,37 +69,48 @@ module VX_databus_arb (
     // handle responses
     //
 
-    wire [1:0][RSP_DATAW-1:0] rsp_data_in;
-    wire [1:0] rsp_valid_in;
-    wire [1:0] rsp_ready_in;
-    
-    wire core_rsp_valid;
-    wire [`NUM_THREADS-1:0] core_rsp_valid_tmask;
+    if (`SM_ENABLE ) begin
 
-    assign rsp_data_in[0] = {cache_rsp_if.valid, cache_rsp_if.data, cache_rsp_if.tag};
-    assign rsp_data_in[1] = {smem_rsp_if.valid,  smem_rsp_if.data,  smem_rsp_if.tag};
+        wire [1:0][RSP_DATAW-1:0] rsp_data_in;
+        wire [1:0] rsp_valid_in;
+        wire [1:0] rsp_ready_in;
+        
+        wire core_rsp_valid;
+        wire [`NUM_THREADS-1:0] core_rsp_valid_tmask;
 
-    assign rsp_valid_in[0] = (| cache_rsp_if.valid);
-    assign rsp_valid_in[1] = (| smem_rsp_if.valid) & `SM_ENABLE;
+        assign rsp_data_in[0] = {cache_rsp_if.valid, cache_rsp_if.data, cache_rsp_if.tag};
+        assign rsp_data_in[1] = {smem_rsp_if.valid,  smem_rsp_if.data,  smem_rsp_if.tag};
 
-    VX_stream_arbiter #(
-        .NUM_REQS ((`SM_ENABLE ? 2 : 1)),
-        .DATAW    (RSP_DATAW),        
-        .BUFFERED (0)
-    ) rsp_arb (
-        .clk        (clk),
-        .reset      (reset),
-        .valid_in   (rsp_valid_in),
-        .data_in    (rsp_data_in),
-        .ready_in   (rsp_ready_in),
-        .valid_out  (core_rsp_valid),
-        .data_out   ({core_rsp_valid_tmask, core_rsp_if.data, core_rsp_if.tag}),
-        .ready_out  (core_rsp_if.ready)
-    );
+        assign rsp_valid_in[0] = (| cache_rsp_if.valid);
+        assign rsp_valid_in[1] = (| smem_rsp_if.valid) & `SM_ENABLE;
 
-    assign cache_rsp_if.ready = rsp_ready_in[0];
-    assign smem_rsp_if.ready  = rsp_ready_in[1];
+        VX_stream_arbiter #(
+            .NUM_REQS (2),
+            .DATAW    (RSP_DATAW),    
+            .BUFFERED (0)
+        ) rsp_arb (
+            .clk        (clk),
+            .reset      (reset),
+            .valid_in   (rsp_valid_in),
+            .data_in    (rsp_data_in),
+            .ready_in   (rsp_ready_in),
+            .valid_out  (core_rsp_valid),
+            .data_out   ({core_rsp_valid_tmask, core_rsp_if.data, core_rsp_if.tag}),
+            .ready_out  (core_rsp_if.ready)
+        );
 
-    assign core_rsp_if.valid  = {`NUM_THREADS{core_rsp_valid}} & core_rsp_valid_tmask;
+        assign cache_rsp_if.ready = rsp_ready_in[0];
+        assign smem_rsp_if.ready  = rsp_ready_in[1];
+
+        assign core_rsp_if.valid  = {`NUM_THREADS{core_rsp_valid}} & core_rsp_valid_tmask;
+
+    end else begin
+
+        assign core_rsp_if.valid  = cache_rsp_if.valid;
+        assign core_rsp_if.tag    = cache_rsp_if.tag;
+        assign core_rsp_if.data   = cache_rsp_if.data;
+        assign cache_rsp_if.ready = core_rsp_if.ready;
+
+    end
 
 endmodule

hw/rtl/cache/VX_bank.v

@@ -110,7 +110,8 @@ module VX_bank #(
 
         VX_input_queue #(
             .DATAW    ($bits(dram_rsp_data)), 
-            .SIZE     (DRSQ_SIZE)
+            .SIZE     (DRSQ_SIZE),
+            .FASTRAM  (1)
         ) dram_rsp_queue (
             .clk     (clk),
             .reset   (reset),
@@ -164,7 +165,8 @@ module VX_bank #(
 
     VX_input_queue #(
         .DATAW    (CORE_TAG_WIDTH + `REQS_BITS + 1 + WORD_SIZE + `WORD_ADDR_WIDTH + `WORD_WIDTH), 
-        .SIZE     (CREQ_SIZE)
+        .SIZE     (CREQ_SIZE),
+        .FASTRAM  (1)
     ) core_req_queue (
         .clk     (clk),
         .reset   (reset),

hw/rtl/cache/VX_cache_core_req_bank_sel.v

@@ -2,18 +2,18 @@
 
 module VX_cache_core_req_bank_sel #(  
     // Size of line inside a bank in bytes
-    parameter CACHE_LINE_SIZE= 1, 
+    parameter CACHE_LINE_SIZE   = 64, 
     // Size of a word in bytes
-    parameter WORD_SIZE      = 1, 
+    parameter WORD_SIZE         = 4, 
     // Number of banks
-    parameter NUM_BANKS      = 1, 
+    parameter NUM_BANKS         = 4, 
     // Number of Word requests per cycle
-    parameter NUM_REQS       = 1,
+    parameter NUM_REQS          = 4,
     // core request tag size
-    parameter CORE_TAG_WIDTH = 1,
+    parameter CORE_TAG_WIDTH    = 3,
 
     // bank offset from beginning of index range
-    parameter BANK_ADDR_OFFSET = 0
+    parameter BANK_ADDR_OFFSET  = 0
 ) (
     input wire                                      clk,
     input wire                                      reset,
@@ -62,7 +62,7 @@ module VX_cache_core_req_bank_sel #(
             per_bank_core_req_addr_r  = 'x;
             per_bank_core_req_tag_r   = 'x;
             per_bank_core_req_data_r  = 'x;
-            
+
             for (integer i = NUM_REQS-1; i >= 0; --i) begin                                                
                 if (core_req_valid[i]) begin                    
                     per_bank_core_req_valid_r[core_req_bid[i]] = 1;

hw/rtl/cache/VX_input_queue.v

@@ -4,7 +4,8 @@ module VX_input_queue #(
     parameter DATAW    = 1,
     parameter SIZE     = 2,
     parameter ADDRW    = $clog2(SIZE),
-    parameter SIZEW    = $clog2(SIZE+1)
+    parameter SIZEW    = $clog2(SIZE+1),
+    parameter FASTRAM  = 0
 ) ( 
     input  wire             clk,
     input  wire             reset,    
@@ -97,7 +98,7 @@ module VX_input_queue #(
         .SIZE(SIZE),
         .BUFFERED(0),
         .RWCHECK(1),
-        .FASTRAM(1)
+        .FASTRAM(FASTRAM)
     ) dp_ram (
         .clk(clk),
         .waddr(wr_ptr_r),                                

hw/rtl/cache/VX_miss_resrv.v

@@ -55,7 +55,7 @@ module VX_miss_resrv #(
     // dequeue
     input wire                          dequeue
 );
-    `USE_FAST_BRAM reg [MSHR_SIZE-1:0][`LINE_ADDR_WIDTH-1:0] addr_table;
+    reg [MSHR_SIZE-1:0][`LINE_ADDR_WIDTH-1:0] addr_table;
     
     reg [MSHR_SIZE-1:0]          valid_table;
     reg [MSHR_SIZE-1:0]          ready_table;