wu-arch/vortex
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minor udpate

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This commit is contained in:
Blaise Tine
2021-06-28 09:14:06 -07:00
parent 3a0a9edaca
commit 201aa2c6ad
2 changed files with 21 additions and 26 deletions
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39
hw/rtl/VX_decode.v
View File

@@ -56,7 +56,7 @@ module VX_decode #(
`endif `endif
wire [19:0] upper_imm = {func7, rs2, rs1, func3}; wire [19:0] upper_imm = {func7, rs2, rs1, func3};
wire [11:0] alu_imm = ((func3 == 3'h1) || (func3 == 3'h5)) ? {{7{1'b0}}, rs2} : u_12; wire [11:0] alu_imm = (func3[0] && ~func3[1]) ? {{7{1'b0}}, rs2} : u_12;
wire [20:0] jal_imm = {instr[31], instr[19:12], instr[20], instr[30:21], 1'b0}; wire [20:0] jal_imm = {instr[31], instr[19:12], instr[20], instr[30:21], 1'b0};
wire [11:0] jalr_imm = {func7, rs2}; wire [11:0] jalr_imm = {func7, rs2};
@@ -203,10 +203,22 @@ module VX_decode #(
end end
`INST_F: begin `INST_F: begin
ex_type = `EX_LSU; ex_type = `EX_LSU;
op_mod = `MOD_BITS'(0 == func3); // data fence op_mod = `MOD_BITS'(!func3[0]); // data fence
end end
`INST_SYS : begin `INST_SYS : begin
if (func3 == 0) begin if (func3[1:0] != 0) begin
ex_type = `EX_CSR;
op_type = `OP_BITS'(func3[1:0]);
use_rd = 1;
use_imm = func3[2];
imm = 32'(u_12); // addr
`USED_REG (rd_r, 1'b0, rd);
if (func3[2]) begin
`SET_REG(rs1_r, 1'b0, rs1); // imm
end else begin
`USED_REG (rs1_r, 1'b0, rs1);
end
end else begin
ex_type = `EX_ALU; ex_type = `EX_ALU;
case (u_12) case (u_12)
12'h000: op_type = `OP_BITS'(`BR_ECALL); 12'h000: op_type = `OP_BITS'(`BR_ECALL);
@@ -222,23 +234,6 @@ module VX_decode #(
use_PC = 1; use_PC = 1;
imm = 32'd4; imm = 32'd4;
`USED_REG (rd_r, 1'b0, rd); `USED_REG (rd_r, 1'b0, rd);
end else begin
ex_type = `EX_CSR;
case (func3[1:0])
2'h1: op_type = `OP_BITS'(`CSR_RW);
2'h2: op_type = `OP_BITS'(`CSR_RS);
2'h3: op_type = `OP_BITS'(`CSR_RC);
default:;
endcase
use_rd = 1;
use_imm = func3[2];
imm = 32'(u_12); // addr
`USED_REG (rd_r, 1'b0, rd);
if (func3[2]) begin
`SET_REG(rs1_r, 1'b0, rs1); // imm
end else begin
`USED_REG (rs1_r, 1'b0, rs1);
end
end end
end end
`ifdef EXT_F_ENABLE `ifdef EXT_F_ENABLE
@@ -250,7 +245,7 @@ module VX_decode #(
op_mod = 0; op_mod = 0;
use_rd = 1; use_rd = 1;
imm = {{20{u_12[11]}}, u_12}; imm = {{20{u_12[11]}}, u_12};
`USED_REG (rd_r, (opcode == `INST_FL), rd); `USED_REG (rd_r, opcode[2], rd);
`USED_REG (rs1_r, 1'b0, rs1); `USED_REG (rs1_r, 1'b0, rs1);
end end
`ifdef EXT_F_ENABLE `ifdef EXT_F_ENABLE
@@ -262,7 +257,7 @@ module VX_decode #(
op_mod = 0; op_mod = 0;
imm = {{20{func7[6]}}, func7, rd}; imm = {{20{func7[6]}}, func7, rd};
`USED_REG (rs1_r, 1'b0, rs1); `USED_REG (rs1_r, 1'b0, rs1);
`USED_REG (rs2_r, (opcode == `INST_FS), rs2); `USED_REG (rs2_r, opcode[2], rs2);
end end
`ifdef EXT_F_ENABLE `ifdef EXT_F_ENABLE
`INST_FMADD, `INST_FMADD,

8
hw/rtl/VX_define.vh
View File

@@ -154,10 +154,10 @@
`define LSU_OP(x) x[`LSU_BITS-1:0] `define LSU_OP(x) x[`LSU_BITS-1:0]
`define LSU_IS_FENCE(x) x[0] `define LSU_IS_FENCE(x) x[0]
`define CSR_RW 2'h0 `define CSR_RW 2'h1
`define CSR_RS 2'h1 `define CSR_RS 2'h2
`define CSR_RC 2'h2 `define CSR_RC 2'h3
`define CSR_OTHER 2'h3 `define CSR_OTHER 2'h0
`define CSR_BITS 2 `define CSR_BITS 2
`define CSR_OP(x) x[`CSR_BITS-1:0] `define CSR_OP(x) x[`CSR_BITS-1:0]