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new fpu implementation

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This commit is contained in:
Blaise Tine
2020-07-24 00:00:37 -04:00
parent f83521b7c6
commit 1f63f9da25
30 changed files with 318 additions and 258 deletions
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11
hw/rtl/VX_csr_unit.v
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@@ -6,7 +6,9 @@ module VX_csr_unit #(
input wire clk,
input wire reset,
VX_perf_cntrs_if perf_cntrs_if,
VX_perf_cntrs_if perf_cntrs_if,
VX_fpu_from_csr_if fpu_from_csr_if,
VX_fpu_to_csr_if fpu_to_csr_if,
VX_csr_io_req_if csr_io_req_if,
@@ -48,13 +50,16 @@ module VX_csr_unit #(
.CORE_ID(CORE_ID)
) csr_data (
.clk (clk),
.reset (reset),
.perf_cntrs_if (perf_cntrs_if),
.fpu_to_csr_if (fpu_to_csr_if),
.fpu_from_csr_if(fpu_from_csr_if),
.read_addr (csr_pipe_req_if.csr_addr),
.read_data (csr_read_data_unqual),
.write_enable (is_csr_s2),
.write_data (csr_updated_data_s2[`CSR_WIDTH-1:0]),
.write_addr (csr_addr_s2),
.warp_num (csr_pipe_req_if.warp_num),
.perf_cntrs_if (perf_cntrs_if)
.warp_num (csr_pipe_req_if.warp_num)
);
wire csr_hazard = (csr_addr_s2 == csr_pipe_req_if.csr_addr)