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FIxed first circular issue

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This commit is contained in:
felsabbagh3
2019-10-24 10:38:04 -04:00
parent de8de00f6e
commit 1e648c5819
19 changed files with 2302 additions and 2799 deletions
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2
rtl/simulate/VX_define.h
View File

@@ -3,6 +3,8 @@
#define NW 8
#define CACHE_NUM_BANKS 8
#define CACHE_WORDS_PER_BLOCK 4
#define R_INST 51
#define L_INST 3

3
rtl/simulate/test_bench.cpp
View File

@@ -5,11 +5,12 @@
int main(int argc, char **argv)
{
Verilated::debug(1);
Verilated::commandArgs(argc, argv);
Verilated::traceEverOn(true);
// Verilated::debug(1);
// bool passed = true;

284
rtl/simulate/test_bench.h
View File

@@ -45,6 +45,8 @@ class Vortex
VVortex * vortex;
unsigned start_pc;
bool refill;
unsigned refill_addr;
long int curr_cycle;
bool stop;
bool unit_test;
@@ -190,120 +192,196 @@ bool Vortex::ibus_driver()
bool Vortex::dbus_driver()
{
uint32_t data_read;
uint32_t data_write;
uint32_t addr;
// std::cout << "DBUS DRIVER\n" << std::endl;
////////////////////// DBUS //////////////////////
bool did = false;
for (unsigned curr_th = 0; curr_th < NT; curr_th++)
if (this->refill)
{
if ((vortex->out_cache_driver_in_mem_write != NO_MEM_WRITE) && vortex->out_cache_driver_in_valid[curr_th])
this->refill = false;
unsigned unordered_mem[32];
int num_iter = 0;
for (int i = 0; i < CACHE_WORDS_PER_BLOCK; i++)
{
did = true;
data_write = (uint32_t) vortex->out_cache_driver_in_data[curr_th];
addr = (uint32_t) vortex->out_cache_driver_in_address[curr_th];
if (addr == 0x00010000)
{
std::cerr << (char) data_write;
}
// if ((addr >= 0x810002cc) && (addr < 0x810002d0))
// {
// int index = (addr - 0x810002cc) / 4;
// // std::cerr << GREEN << "1done[" << index << "] = " << data_write << DEFAULT << "\n";
// }
// if ((addr >= 0x810059f4) && (addr < 0x810059f4))
// {
// int index = (addr - 0x810059f4) / 4;
// // std::cerr << RED << "2done[" << index << "] = " << data_write << DEFAULT << "\n";
// }
if (vortex->out_cache_driver_in_mem_write == SB_MEM_WRITE)
{
data_write = ( data_write) & 0xFF;
ram.writeByte( addr, &data_write);
} else if (vortex->out_cache_driver_in_mem_write == SH_MEM_WRITE)
{
data_write = ( data_write) & 0xFFFF;
ram.writeHalf( addr, &data_write);
} else if (vortex->out_cache_driver_in_mem_write == SW_MEM_WRITE)
{
// printf("STORING %x in %x \n", data_write, addr);
data_write = data_write;
ram.writeWord( addr, &data_write);
}
}
}
// printf("----\n");
for (unsigned curr_th = 0; curr_th < NT; curr_th++)
{
if ((vortex->out_cache_driver_in_mem_read != NO_MEM_READ) && vortex->out_cache_driver_in_valid[curr_th])
{
did = true;
addr = (uint32_t) vortex->out_cache_driver_in_address[curr_th];
for (int j = 0; j < (CACHE_NUM_BANKS*8); j+=8)
{
unsigned addr = this->refill_addr + (4*num_iter);
unsigned data_read;
ram.getWord(addr, &data_read);
if (vortex->out_cache_driver_in_mem_read == LB_MEM_READ)
{
vortex->in_cache_driver_out_data[curr_th] = (data_read & 0x80) ? (data_read | 0xFFFFFF00) : (data_read & 0xFF);
} else if (vortex->out_cache_driver_in_mem_read == LH_MEM_READ)
{
vortex->in_cache_driver_out_data[curr_th] = (data_read & 0x8000) ? (data_read | 0xFFFF0000) : (data_read & 0xFFFF);
} else if (vortex->out_cache_driver_in_mem_read == LW_MEM_READ)
{
// printf("Reading mem - Addr: %x = %x\n", addr, data_read);
// std::cout << "READING - Addr: " << std::hex << addr << " = " << data_read << "\n";
// std::cout << std::dec;
vortex->in_cache_driver_out_data[curr_th] = data_read;
} else if (vortex->out_cache_driver_in_mem_read == LBU_MEM_READ)
{
vortex->in_cache_driver_out_data[curr_th] = (data_read & 0xFF);
} else if (vortex->out_cache_driver_in_mem_read == LHU_MEM_READ)
{
vortex->in_cache_driver_out_data[curr_th] = (data_read & 0xFFFF);
}
else
{
vortex->in_cache_driver_out_data[curr_th] = 0xbabebabe;
}
unordered_mem[i+j] = data_read;
num_iter++;
}
}
else
vortex->i_m_ready = 1;
for (int i = 0; i < CACHE_NUM_BANKS; i++)
{
vortex->in_cache_driver_out_data[curr_th] = 0xbabebabe;
for (int j = 0; j < CACHE_WORDS_PER_BLOCK; j++)
{
vortex->i_m_readdata[i][j] = unordered_mem[(i*CACHE_WORDS_PER_BLOCK)+j];
}
}
}
if (did && (NW > 1))
else
{
if (NW < NT)
if (vortex->o_m_valid)
{
this->stats_total_cycles += NT % (NW -1);
if (vortex->o_m_read_or_write)
{
unsigned ordered_mem[32];
// Create unordered mem
unsigned unordered_mem[32];
for (int i = 0; i < CACHE_NUM_BANKS; i++)
{
for (int j = 0; j < CACHE_WORDS_PER_BLOCK; j++)
{
unordered_mem[(i*CACHE_WORDS_PER_BLOCK)+j] = vortex->o_m_writedata[i][j];
}
}
// Order the memory
int num_iter = 0;
for (int i = 0; i < CACHE_NUM_BANKS; i++)
{
for (int j = 0; j < (CACHE_NUM_BANKS*CACHE_WORDS_PER_BLOCK); j+=CACHE_WORDS_PER_BLOCK)
{
printf("i: %d, j: %d, num_iter: %d\n", i, j, num_iter);
ordered_mem[i+j] = unordered_mem[num_iter];
num_iter++;
}
}
// Save the memory
for (int i = 0; i < (CACHE_WORDS_PER_BLOCK * CACHE_NUM_BANKS); i++)
{
unsigned addr = (vortex->o_m_evict_addr) + (4*i);
unsigned * data_addr = ordered_mem + i;
ram.writeWord( addr, data_addr);
}
}
// Respond next cycle
this->refill = true;
this->refill_addr = vortex->o_m_read_addr;
}
}
// uint32_t data_read;
// uint32_t data_write;
// uint32_t addr;
// // std::cout << "DBUS DRIVER\n" << std::endl;
// ////////////////////// DBUS //////////////////////
// bool did = false;
// for (unsigned curr_th = 0; curr_th < NT; curr_th++)
// {
// if ((vortex->out_cache_driver_in_mem_write != NO_MEM_WRITE) && vortex->out_cache_driver_in_valid[curr_th])
// {
// did = true;
// data_write = (uint32_t) vortex->out_cache_driver_in_data[curr_th];
// addr = (uint32_t) vortex->out_cache_driver_in_address[curr_th];
// if (addr == 0x00010000)
// {
// std::cerr << (char) data_write;
// }
// // if ((addr >= 0x810002cc) && (addr < 0x810002d0))
// // {
// // int index = (addr - 0x810002cc) / 4;
// // // std::cerr << GREEN << "1done[" << index << "] = " << data_write << DEFAULT << "\n";
// // }
// // if ((addr >= 0x810059f4) && (addr < 0x810059f4))
// // {
// // int index = (addr - 0x810059f4) / 4;
// // // std::cerr << RED << "2done[" << index << "] = " << data_write << DEFAULT << "\n";
// // }
// if (vortex->out_cache_driver_in_mem_write == SB_MEM_WRITE)
// {
// data_write = ( data_write) & 0xFF;
// ram.writeByte( addr, &data_write);
// } else if (vortex->out_cache_driver_in_mem_write == SH_MEM_WRITE)
// {
// data_write = ( data_write) & 0xFFFF;
// ram.writeHalf( addr, &data_write);
// } else if (vortex->out_cache_driver_in_mem_write == SW_MEM_WRITE)
// {
// // printf("STORING %x in %x \n", data_write, addr);
// data_write = data_write;
// ram.writeWord( addr, &data_write);
// }
// }
// }
// // printf("----\n");
// for (unsigned curr_th = 0; curr_th < NT; curr_th++)
// {
// if ((vortex->out_cache_driver_in_mem_read != NO_MEM_READ) && vortex->out_cache_driver_in_valid[curr_th])
// {
// did = true;
// addr = (uint32_t) vortex->out_cache_driver_in_address[curr_th];
// ram.getWord(addr, &data_read);
// if (vortex->out_cache_driver_in_mem_read == LB_MEM_READ)
// {
// vortex->in_cache_driver_out_data[curr_th] = (data_read & 0x80) ? (data_read | 0xFFFFFF00) : (data_read & 0xFF);
// } else if (vortex->out_cache_driver_in_mem_read == LH_MEM_READ)
// {
// vortex->in_cache_driver_out_data[curr_th] = (data_read & 0x8000) ? (data_read | 0xFFFF0000) : (data_read & 0xFFFF);
// } else if (vortex->out_cache_driver_in_mem_read == LW_MEM_READ)
// {
// // printf("Reading mem - Addr: %x = %x\n", addr, data_read);
// // std::cout << "READING - Addr: " << std::hex << addr << " = " << data_read << "\n";
// // std::cout << std::dec;
// vortex->in_cache_driver_out_data[curr_th] = data_read;
// } else if (vortex->out_cache_driver_in_mem_read == LBU_MEM_READ)
// {
// vortex->in_cache_driver_out_data[curr_th] = (data_read & 0xFF);
// } else if (vortex->out_cache_driver_in_mem_read == LHU_MEM_READ)
// {
// vortex->in_cache_driver_out_data[curr_th] = (data_read & 0xFFFF);
// }
// else
// {
// vortex->in_cache_driver_out_data[curr_th] = 0xbabebabe;
// }
// }
// else
// {
// vortex->in_cache_driver_out_data[curr_th] = 0xbabebabe;
// }
// }
// if (did && (NW > 1))
// {
// if (NW < NT)
// {
// this->stats_total_cycles += NT % (NW -1);
// }
// }
// printf("******\n");
@@ -376,15 +454,17 @@ bool Vortex::simulate(std::string file_to_simulate)
vortex->reset = 1;
vortex->clk = 0;
vortex->eval();
// m_trace->dump(10);
vortex->reset = 1;
vortex->clk = 1;
vortex->eval();
// m_trace->dump(11);
vortex->reset = 0;
vortex->clk = 0;
// unsigned cycles;
counter = 0;
this->stats_total_cycles = 10;
this->stats_total_cycles = 12;
while (this->stop && ((counter < 2)))
// while (this->stats_total_cycles < 10)
{