FIxed first circular issue

rtl/Vortex.v

@@ -8,7 +8,8 @@ module Vortex(
 	input  wire[31:0] icache_response_instruction,
 	output wire[31:0] icache_request_pc_address,
 	// Req
-    output reg [31:0]  o_m_addr,
+    output reg [31:0]  o_m_read_addr,
+    output reg [31:0]  o_m_evict_addr,
     output reg         o_m_valid,
     output reg [31:0]  o_m_writedata[`NUMBER_BANKS - 1:0][`NUM_WORDS_PER_BLOCK-1:0],
     output reg         o_m_read_or_write,
@@ -16,32 +17,9 @@ module Vortex(
     // Rsp
     input  wire [31:0] i_m_readdata[`NUMBER_BANKS - 1:0][`NUM_WORDS_PER_BLOCK-1:0],
     input  wire        i_m_ready,
-	// Remove Start
-	input  wire[31:0]     in_cache_driver_out_data[`NT_M1:0],
-	output wire[31:0]     out_cache_driver_in_address[`NT_M1:0],
-	output wire[2:0]      out_cache_driver_in_mem_read,
-	output wire[2:0]      out_cache_driver_in_mem_write,
-	output wire           out_cache_driver_in_valid[`NT_M1:0],
-	output wire[31:0]     out_cache_driver_in_data[`NT_M1:0],
-	// Remove end
-	output wire           out_ebreak
+	output wire        out_ebreak
 	);
 
-// assign out_cache_driver_in_address   = 0;
-assign out_cache_driver_in_mem_read  = `NO_MEM_READ;
-assign out_cache_driver_in_mem_write = `NO_MEM_WRITE;
-// assign out_cache_driver_in_valid     = 0;
-// assign out_cache_driver_in_data      = 0;
-
-// assign out_cache_driver_in_address   = VX_dcache_req.out_cache_driver_in_address;
-// assign out_cache_driver_in_mem_read  = VX_dcache_req.out_cache_driver_in_mem_read;
-// assign out_cache_driver_in_mem_write = VX_dcache_req.out_cache_driver_in_mem_write;
-// assign out_cache_driver_in_valid     = VX_dcache_req.out_cache_driver_in_valid;
-// assign out_cache_driver_in_data      = VX_dcache_req.out_cache_driver_in_data;
-
-// assign VX_dcache_rsp.in_cache_driver_out_data = in_cache_driver_out_data;
-
-
 // Dcache Interface
 
 VX_dcache_response_inter VX_dcache_rsp();
@@ -50,7 +28,8 @@ VX_dcache_request_inter  VX_dcache_req();
 
 VX_dram_req_rsp_inter    VX_dram_req_rsp();
 
-assign o_m_addr          = VX_dram_req_rsp.o_m_addr;
+assign o_m_read_addr     = VX_dram_req_rsp.o_m_read_addr;
+assign o_m_evict_addr    = VX_dram_req_rsp.o_m_evict_addr;
 assign o_m_valid         = VX_dram_req_rsp.o_m_valid;
 assign o_m_read_or_write = VX_dram_req_rsp.o_m_read_or_write;
 
@@ -61,7 +40,6 @@ genvar curr_word;
 for (curr_bank = 0; curr_bank < `NUMBER_BANKS; curr_bank = curr_bank + 1) begin
 
 	for (curr_word = 0; curr_word < `NUM_WORDS_PER_BLOCK; curr_word = curr_word + 1) begin
-
 		assign o_m_writedata[curr_bank][curr_word]                = VX_dram_req_rsp.o_m_writedata[curr_bank][curr_word];
 		assign VX_dram_req_rsp.i_m_readdata[curr_bank][curr_word] = i_m_readdata[curr_bank][curr_word];