tensor: Bore tensor regfile IO to execute units
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@@ -14,7 +14,7 @@
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`include "VX_define.vh"
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`include "VX_trace.vh"
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module VX_issue #(
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module VX_issue import VX_gpu_pkg::*; #(
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parameter CORE_ID = 0
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) (
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`SCOPE_IO_DECL
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@@ -36,6 +36,9 @@ module VX_issue #(
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`endif
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`ifdef EXT_T_ENABLE
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VX_dispatch_if.master tensor_dispatch_if [`ISSUE_WIDTH],
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`ifdef EXT_T_HOPPER
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VX_tc_rf_if.slave tensor_regfile_if,
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`endif
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`endif
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VX_dispatch_if.master sfu_dispatch_if [`ISSUE_WIDTH]
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);
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@@ -75,22 +78,6 @@ module VX_issue #(
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.scoreboard_if (scoreboard_if)
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);
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// /*
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// fake fsm driving tc output
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reg [11:0] counter;
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wire tc_rf_valid;
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wire [4:0] tc_rf_addr;
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always @(posedge clk) begin
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if (reset) begin
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counter <= 12'd1;
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end else begin
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counter <= counter + 12'd1;
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end
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end
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assign tc_rf_valid = (counter[6:0] == 7'd0);
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assign tc_rf_addr = counter[11:7];
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// */
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`ifdef GPR_DUPLICATED
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VX_operands_dup #(
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`else
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@@ -104,11 +91,7 @@ module VX_issue #(
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.writeback_if (writeback_if),
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.scoreboard_if (scoreboard_if),
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.operands_if (operands_if),
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`ifdef GPR_DUPLICATED
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.tc_rf_valid ('{`ISSUE_WIDTH{tc_rf_valid}}),
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.tc_rf_addr ('{`ISSUE_WIDTH{tc_rf_addr}}),
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.tc_rf_data ()
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`endif
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.tensor_regfile_if (tensor_regfile_if)
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);
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VX_dispatch #(
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